2 // Register Declarations for Microchip 16F877A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define CMCON_ADDR 0x009C
76 #define CVRCON_ADDR 0x009D
77 #define ADRESL_ADDR 0x009E
78 #define ADCON1_ADDR 0x009F
79 #define EEDATA_ADDR 0x010C
80 #define EEADR_ADDR 0x010D
81 #define EEDATH_ADDR 0x010E
82 #define EEADRH_ADDR 0x010F
83 #define EECON1_ADDR 0x018C
84 #define EECON2_ADDR 0x018D
87 // Memory organization.
90 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
91 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
92 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
93 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
94 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
95 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
96 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
97 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
98 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
99 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
100 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
101 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
102 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
103 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
104 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
105 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
106 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
107 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
108 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
109 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
110 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
111 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
112 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
113 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
114 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
115 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
116 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
117 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
118 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
119 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
120 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
121 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
122 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
123 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
124 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
125 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
126 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
127 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
128 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
129 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
130 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
131 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
132 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
133 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
134 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
135 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
136 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
137 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
138 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
139 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
140 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
141 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
142 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
143 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
144 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
145 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
146 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
150 // P16F877A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
153 // This header file defines configurations, registers, and other useful bits of
154 // information for the PIC16F877A microcontroller. These names are taken to match
155 // the data sheets as closely as possible.
157 // Note that the processor must be selected before this file is
158 // included. The processor may be selected the following ways:
160 // 1. Command line switch:
161 // C:\ MPASM MYFILE.ASM /PIC16F877A
162 // 2. LIST directive in the source file
164 // 3. Processor Type entry in the MPASM full-screen interface
166 //==========================================================================
170 //==========================================================================
173 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
174 //1.01 09/13/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
175 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc)
177 //==========================================================================
181 //==========================================================================
184 // MESSG "Processor-header file mismatch. Verify selected processor."
187 //==========================================================================
189 // Register Definitions
191 //==========================================================================
196 //----- Register Files------------------------------------------------------
198 extern data __at (INDF_ADDR) volatile char INDF;
199 extern sfr __at (TMR0_ADDR) TMR0;
200 extern data __at (PCL_ADDR) volatile char PCL;
201 extern sfr __at (STATUS_ADDR) STATUS;
202 extern sfr __at (FSR_ADDR) FSR;
203 extern sfr __at (PORTA_ADDR) PORTA;
204 extern sfr __at (PORTB_ADDR) PORTB;
205 extern sfr __at (PORTC_ADDR) PORTC;
206 extern sfr __at (PORTD_ADDR) PORTD;
207 extern sfr __at (PORTE_ADDR) PORTE;
208 extern sfr __at (PCLATH_ADDR) PCLATH;
209 extern sfr __at (INTCON_ADDR) INTCON;
210 extern sfr __at (PIR1_ADDR) PIR1;
211 extern sfr __at (PIR2_ADDR) PIR2;
212 extern sfr __at (TMR1L_ADDR) TMR1L;
213 extern sfr __at (TMR1H_ADDR) TMR1H;
214 extern sfr __at (T1CON_ADDR) T1CON;
215 extern sfr __at (TMR2_ADDR) TMR2;
216 extern sfr __at (T2CON_ADDR) T2CON;
217 extern sfr __at (SSPBUF_ADDR) SSPBUF;
218 extern sfr __at (SSPCON_ADDR) SSPCON;
219 extern sfr __at (CCPR1L_ADDR) CCPR1L;
220 extern sfr __at (CCPR1H_ADDR) CCPR1H;
221 extern sfr __at (CCP1CON_ADDR) CCP1CON;
222 extern sfr __at (RCSTA_ADDR) RCSTA;
223 extern sfr __at (TXREG_ADDR) TXREG;
224 extern sfr __at (RCREG_ADDR) RCREG;
225 extern sfr __at (CCPR2L_ADDR) CCPR2L;
226 extern sfr __at (CCPR2H_ADDR) CCPR2H;
227 extern sfr __at (CCP2CON_ADDR) CCP2CON;
228 extern sfr __at (ADRESH_ADDR) ADRESH;
229 extern sfr __at (ADCON0_ADDR) ADCON0;
231 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
232 extern sfr __at (TRISA_ADDR) TRISA;
233 extern sfr __at (TRISB_ADDR) TRISB;
234 extern sfr __at (TRISC_ADDR) TRISC;
235 extern sfr __at (TRISD_ADDR) TRISD;
236 extern sfr __at (TRISE_ADDR) TRISE;
237 extern sfr __at (PIE1_ADDR) PIE1;
238 extern sfr __at (PIE2_ADDR) PIE2;
239 extern sfr __at (PCON_ADDR) PCON;
240 extern sfr __at (SSPCON2_ADDR) SSPCON2;
241 extern sfr __at (PR2_ADDR) PR2;
242 extern sfr __at (SSPADD_ADDR) SSPADD;
243 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
244 extern sfr __at (TXSTA_ADDR) TXSTA;
245 extern sfr __at (SPBRG_ADDR) SPBRG;
246 extern sfr __at (CMCON_ADDR) CMCON;
247 extern sfr __at (CVRCON_ADDR) CVRCON;
248 extern sfr __at (ADRESL_ADDR) ADRESL;
249 extern sfr __at (ADCON1_ADDR) ADCON1;
251 extern sfr __at (EEDATA_ADDR) EEDATA;
252 extern sfr __at (EEADR_ADDR) EEADR;
253 extern sfr __at (EEDATH_ADDR) EEDATH;
254 extern sfr __at (EEADRH_ADDR) EEADRH;
256 extern sfr __at (EECON1_ADDR) EECON1;
257 extern sfr __at (EECON2_ADDR) EECON2;
259 //----- STATUS Bits --------------------------------------------------------
262 //----- INTCON Bits --------------------------------------------------------
265 //----- PIR1 Bits ----------------------------------------------------------
268 //----- PIR2 Bits ----------------------------------------------------------
271 //----- T1CON Bits ---------------------------------------------------------
274 //----- T2CON Bits ---------------------------------------------------------
277 //----- SSPCON Bits --------------------------------------------------------
280 //----- CCP1CON Bits -------------------------------------------------------
283 //----- RCSTA Bits ---------------------------------------------------------
286 //----- CCP2CON Bits -------------------------------------------------------
289 //----- ADCON0 Bits --------------------------------------------------------
292 //----- OPTION Bits -----------------------------------------------------
295 //----- TRISE Bits ---------------------------------------------------------
298 //----- PIE1 Bits ----------------------------------------------------------
301 //----- PIE2 Bits ----------------------------------------------------------
304 //----- PCON Bits ----------------------------------------------------------
307 //----- SSPCON2 Bits --------------------------------------------------------
310 //----- SSPSTAT Bits -------------------------------------------------------
313 //----- TXSTA Bits ---------------------------------------------------------
317 //----- CMCON Bits ---------------------------------------------------------
319 //----- CVRCON Bits --------------------------------------------------------
321 //----- ADCON1 Bits --------------------------------------------------------
324 //----- EECON1 Bits --------------------------------------------------------
327 //==========================================================================
331 //==========================================================================
334 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
335 // __BADRAM H'105', H'107'-H'109'
336 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
338 //==========================================================================
340 // Configuration Bits
342 //==========================================================================
344 #define _CP_ALL 0x1FFF
345 #define _CP_OFF 0x3FFF
346 #define _DEBUG_OFF 0x3FFF
347 #define _DEBUG_ON 0x37FF
348 #define _WRT_OFF 0x3FFF // No prog memmory write protection
349 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
350 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
351 #define _WRT_HALF 0x39FF // First half memmory write protected
352 #define _CPD_OFF 0x3FFF
353 #define _CPD_ON 0x3EFF
354 #define _LVP_ON 0x3FFF
355 #define _LVP_OFF 0x3F7F
356 #define _BODEN_ON 0x3FFF
357 #define _BODEN_OFF 0x3FBF
358 #define _PWRTE_OFF 0x3FFF
359 #define _PWRTE_ON 0x3FF7
360 #define _WDT_ON 0x3FFF
361 #define _WDT_OFF 0x3FFB
362 #define _RC_OSC 0x3FFF
363 #define _HS_OSC 0x3FFE
364 #define _XT_OSC 0x3FFD
365 #define _LP_OSC 0x3FFC
369 // ----- ADCON0 bits --------------------
372 unsigned char ADON:1;
375 unsigned char CHS0:1;
376 unsigned char CHS1:1;
377 unsigned char CHS2:1;
378 unsigned char ADCS0:1;
379 unsigned char ADCS1:1;
384 unsigned char NOT_DONE:1;
394 unsigned char GO_DONE:1;
402 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
404 #define ADON ADCON0_bits.ADON
405 #define GO ADCON0_bits.GO
406 #define NOT_DONE ADCON0_bits.NOT_DONE
407 #define GO_DONE ADCON0_bits.GO_DONE
408 #define CHS0 ADCON0_bits.CHS0
409 #define CHS1 ADCON0_bits.CHS1
410 #define CHS2 ADCON0_bits.CHS2
411 #define ADCS0 ADCON0_bits.ADCS0
412 #define ADCS1 ADCON0_bits.ADCS1
414 // ----- ADCON1 bits --------------------
417 unsigned char PCFG0:1;
418 unsigned char PCFG1:1;
419 unsigned char PCFG2:1;
420 unsigned char PCFG3:1;
424 unsigned char ADFM:1;
427 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
429 #define PCFG0 ADCON1_bits.PCFG0
430 #define PCFG1 ADCON1_bits.PCFG1
431 #define PCFG2 ADCON1_bits.PCFG2
432 #define PCFG3 ADCON1_bits.PCFG3
433 #define ADFM ADCON1_bits.ADFM
435 // ----- CCP1CON bits --------------------
438 unsigned char CCP1M0:1;
439 unsigned char CCP1M1:1;
440 unsigned char CCP1M2:1;
441 unsigned char CCP1M3:1;
442 unsigned char CCP1Y:1;
443 unsigned char CCP1X:1;
448 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
450 #define CCP1M0 CCP1CON_bits.CCP1M0
451 #define CCP1M1 CCP1CON_bits.CCP1M1
452 #define CCP1M2 CCP1CON_bits.CCP1M2
453 #define CCP1M3 CCP1CON_bits.CCP1M3
454 #define CCP1Y CCP1CON_bits.CCP1Y
455 #define CCP1X CCP1CON_bits.CCP1X
457 // ----- CCP2CON bits --------------------
460 unsigned char CCP2M0:1;
461 unsigned char CCP2M1:1;
462 unsigned char CCP2M2:1;
463 unsigned char CCP2M3:1;
464 unsigned char CCP2Y:1;
465 unsigned char CCP2X:1;
470 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
472 #define CCP2M0 CCP2CON_bits.CCP2M0
473 #define CCP2M1 CCP2CON_bits.CCP2M1
474 #define CCP2M2 CCP2CON_bits.CCP2M2
475 #define CCP2M3 CCP2CON_bits.CCP2M3
476 #define CCP2Y CCP2CON_bits.CCP2Y
477 #define CCP2X CCP2CON_bits.CCP2X
479 // ----- CMCON bits --------------------
486 unsigned char C1INV:1;
487 unsigned char C2INV:1;
488 unsigned char C1OUT:1;
489 unsigned char C2OUT:1;
492 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
494 #define CM0 CMCON_bits.CM0
495 #define CM1 CMCON_bits.CM1
496 #define CM2 CMCON_bits.CM2
497 #define CIS CMCON_bits.CIS
498 #define C1INV CMCON_bits.C1INV
499 #define C2INV CMCON_bits.C2INV
500 #define C1OUT CMCON_bits.C1OUT
501 #define C2OUT CMCON_bits.C2OUT
503 // ----- CVRCON bits --------------------
506 unsigned char CVR0:1;
507 unsigned char CVR1:1;
508 unsigned char CVR2:1;
509 unsigned char CVR3:1;
511 unsigned char CVRR:1;
512 unsigned char CVROE:1;
513 unsigned char CVREN:1;
516 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
518 #define CVR0 CVRCON_bits.CVR0
519 #define CVR1 CVRCON_bits.CVR1
520 #define CVR2 CVRCON_bits.CVR2
521 #define CVR3 CVRCON_bits.CVR3
522 #define CVRR CVRCON_bits.CVRR
523 #define CVROE CVRCON_bits.CVROE
524 #define CVREN CVRCON_bits.CVREN
526 // ----- EECON1 bits --------------------
531 unsigned char WREN:1;
532 unsigned char WRERR:1;
536 unsigned char EEPGD:1;
539 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
541 #define RD EECON1_bits.RD
542 #define WR EECON1_bits.WR
543 #define WREN EECON1_bits.WREN
544 #define WRERR EECON1_bits.WRERR
545 #define EEPGD EECON1_bits.EEPGD
547 // ----- INTCON bits --------------------
550 unsigned char RBIF:1;
551 unsigned char INTF:1;
552 unsigned char T0IF:1;
553 unsigned char RBIE:1;
554 unsigned char INTE:1;
555 unsigned char T0IE:1;
556 unsigned char PEIE:1;
562 unsigned char TMR0IF:1;
565 unsigned char TMR0IE:1;
570 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
572 #define RBIF INTCON_bits.RBIF
573 #define INTF INTCON_bits.INTF
574 #define T0IF INTCON_bits.T0IF
575 #define TMR0IF INTCON_bits.TMR0IF
576 #define RBIE INTCON_bits.RBIE
577 #define INTE INTCON_bits.INTE
578 #define T0IE INTCON_bits.T0IE
579 #define TMR0IE INTCON_bits.TMR0IE
580 #define PEIE INTCON_bits.PEIE
581 #define GIE INTCON_bits.GIE
583 // ----- OPTION_REG bits --------------------
590 unsigned char T0SE:1;
591 unsigned char T0CS:1;
592 unsigned char INTEDG:1;
593 unsigned char NOT_RBPU:1;
595 } __OPTION_REG_bits_t;
596 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
598 #define PS0 OPTION_REG_bits.PS0
599 #define PS1 OPTION_REG_bits.PS1
600 #define PS2 OPTION_REG_bits.PS2
601 #define PSA OPTION_REG_bits.PSA
602 #define T0SE OPTION_REG_bits.T0SE
603 #define T0CS OPTION_REG_bits.T0CS
604 #define INTEDG OPTION_REG_bits.INTEDG
605 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
607 // ----- PCON bits --------------------
610 unsigned char NOT_BO:1;
611 unsigned char NOT_POR:1;
620 unsigned char NOT_BOR:1;
630 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
632 #define NOT_BO PCON_bits.NOT_BO
633 #define NOT_BOR PCON_bits.NOT_BOR
634 #define NOT_POR PCON_bits.NOT_POR
636 // ----- PIE1 bits --------------------
639 unsigned char TMR1IE:1;
640 unsigned char TMR2IE:1;
641 unsigned char CCP1IE:1;
642 unsigned char SSPIE:1;
643 unsigned char TXIE:1;
644 unsigned char RCIE:1;
645 unsigned char ADIE:1;
646 unsigned char PSPIE:1;
649 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
651 #define TMR1IE PIE1_bits.TMR1IE
652 #define TMR2IE PIE1_bits.TMR2IE
653 #define CCP1IE PIE1_bits.CCP1IE
654 #define SSPIE PIE1_bits.SSPIE
655 #define TXIE PIE1_bits.TXIE
656 #define RCIE PIE1_bits.RCIE
657 #define ADIE PIE1_bits.ADIE
658 #define PSPIE PIE1_bits.PSPIE
660 // ----- PIE2 bits --------------------
663 unsigned char CCP2IE:1;
666 unsigned char BCLIE:1;
667 unsigned char EEIE:1;
669 unsigned char CMIE:1;
673 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
675 #define CCP2IE PIE2_bits.CCP2IE
676 #define BCLIE PIE2_bits.BCLIE
677 #define EEIE PIE2_bits.EEIE
678 #define CMIE PIE2_bits.CMIE
680 // ----- PIR1 bits --------------------
683 unsigned char TMR1IF:1;
684 unsigned char TMR2IF:1;
685 unsigned char CCP1IF:1;
686 unsigned char SSPIF:1;
687 unsigned char TXIF:1;
688 unsigned char RCIF:1;
689 unsigned char ADIF:1;
690 unsigned char PSPIF:1;
693 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
695 #define TMR1IF PIR1_bits.TMR1IF
696 #define TMR2IF PIR1_bits.TMR2IF
697 #define CCP1IF PIR1_bits.CCP1IF
698 #define SSPIF PIR1_bits.SSPIF
699 #define TXIF PIR1_bits.TXIF
700 #define RCIF PIR1_bits.RCIF
701 #define ADIF PIR1_bits.ADIF
702 #define PSPIF PIR1_bits.PSPIF
704 // ----- PIR2 bits --------------------
707 unsigned char CCP2IF:1;
710 unsigned char BCLIF:1;
711 unsigned char EEIF:1;
713 unsigned char CMIF:1;
717 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
719 #define CCP2IF PIR2_bits.CCP2IF
720 #define BCLIF PIR2_bits.BCLIF
721 #define EEIF PIR2_bits.EEIF
722 #define CMIF PIR2_bits.CMIF
724 // ----- RCSTA bits --------------------
727 unsigned char RX9D:1;
728 unsigned char OERR:1;
729 unsigned char FERR:1;
730 unsigned char ADDEN:1;
731 unsigned char CREN:1;
732 unsigned char SREN:1;
734 unsigned char SPEN:1;
737 unsigned char RCD8:1;
753 unsigned char NOT_RC8:1;
763 unsigned char RC8_9:1;
767 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
769 #define RX9D RCSTA_bits.RX9D
770 #define RCD8 RCSTA_bits.RCD8
771 #define OERR RCSTA_bits.OERR
772 #define FERR RCSTA_bits.FERR
773 #define ADDEN RCSTA_bits.ADDEN
774 #define CREN RCSTA_bits.CREN
775 #define SREN RCSTA_bits.SREN
776 #define RX9 RCSTA_bits.RX9
777 #define RC9 RCSTA_bits.RC9
778 #define NOT_RC8 RCSTA_bits.NOT_RC8
779 #define RC8_9 RCSTA_bits.RC8_9
780 #define SPEN RCSTA_bits.SPEN
782 // ----- SSPCON bits --------------------
785 unsigned char SSPM0:1;
786 unsigned char SSPM1:1;
787 unsigned char SSPM2:1;
788 unsigned char SSPM3:1;
790 unsigned char SSPEN:1;
791 unsigned char SSPOV:1;
792 unsigned char WCOL:1;
795 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
797 #define SSPM0 SSPCON_bits.SSPM0
798 #define SSPM1 SSPCON_bits.SSPM1
799 #define SSPM2 SSPCON_bits.SSPM2
800 #define SSPM3 SSPCON_bits.SSPM3
801 #define CKP SSPCON_bits.CKP
802 #define SSPEN SSPCON_bits.SSPEN
803 #define SSPOV SSPCON_bits.SSPOV
804 #define WCOL SSPCON_bits.WCOL
806 // ----- SSPCON2 bits --------------------
810 unsigned char RSEN:1;
812 unsigned char RCEN:1;
813 unsigned char ACKEN:1;
814 unsigned char ACKDT:1;
815 unsigned char ACKSTAT:1;
816 unsigned char GCEN:1;
819 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
821 #define SEN SSPCON2_bits.SEN
822 #define RSEN SSPCON2_bits.RSEN
823 #define PEN SSPCON2_bits.PEN
824 #define RCEN SSPCON2_bits.RCEN
825 #define ACKEN SSPCON2_bits.ACKEN
826 #define ACKDT SSPCON2_bits.ACKDT
827 #define ACKSTAT SSPCON2_bits.ACKSTAT
828 #define GCEN SSPCON2_bits.GCEN
830 // ----- SSPSTAT bits --------------------
845 unsigned char I2C_READ:1;
846 unsigned char I2C_START:1;
847 unsigned char I2C_STOP:1;
848 unsigned char I2C_DATA:1;
855 unsigned char NOT_W:1;
858 unsigned char NOT_A:1;
865 unsigned char NOT_WRITE:1;
868 unsigned char NOT_ADDRESS:1;
885 unsigned char READ_WRITE:1;
888 unsigned char DATA_ADDRESS:1;
893 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
895 #define BF SSPSTAT_bits.BF
896 #define UA SSPSTAT_bits.UA
897 #define R SSPSTAT_bits.R
898 #define I2C_READ SSPSTAT_bits.I2C_READ
899 #define NOT_W SSPSTAT_bits.NOT_W
900 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
901 #define R_W SSPSTAT_bits.R_W
902 #define READ_WRITE SSPSTAT_bits.READ_WRITE
903 #define S SSPSTAT_bits.S
904 #define I2C_START SSPSTAT_bits.I2C_START
905 #define P SSPSTAT_bits.P
906 #define I2C_STOP SSPSTAT_bits.I2C_STOP
907 #define D SSPSTAT_bits.D
908 #define I2C_DATA SSPSTAT_bits.I2C_DATA
909 #define NOT_A SSPSTAT_bits.NOT_A
910 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
911 #define D_A SSPSTAT_bits.D_A
912 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
913 #define CKE SSPSTAT_bits.CKE
914 #define SMP SSPSTAT_bits.SMP
916 // ----- STATUS bits --------------------
922 unsigned char NOT_PD:1;
923 unsigned char NOT_TO:1;
929 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
931 #define C STATUS_bits.C
932 #define DC STATUS_bits.DC
933 #define Z STATUS_bits.Z
934 #define NOT_PD STATUS_bits.NOT_PD
935 #define NOT_TO STATUS_bits.NOT_TO
936 #define RP0 STATUS_bits.RP0
937 #define RP1 STATUS_bits.RP1
938 #define IRP STATUS_bits.IRP
940 // ----- T1CON bits --------------------
943 unsigned char TMR1ON:1;
944 unsigned char TMR1CS:1;
945 unsigned char NOT_T1SYNC:1;
946 unsigned char T1OSCEN:1;
947 unsigned char T1CKPS0:1;
948 unsigned char T1CKPS1:1;
955 unsigned char T1INSYNC:1;
965 unsigned char T1SYNC:1;
973 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
975 #define TMR1ON T1CON_bits.TMR1ON
976 #define TMR1CS T1CON_bits.TMR1CS
977 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
978 #define T1INSYNC T1CON_bits.T1INSYNC
979 #define T1SYNC T1CON_bits.T1SYNC
980 #define T1OSCEN T1CON_bits.T1OSCEN
981 #define T1CKPS0 T1CON_bits.T1CKPS0
982 #define T1CKPS1 T1CON_bits.T1CKPS1
984 // ----- T2CON bits --------------------
987 unsigned char T2CKPS0:1;
988 unsigned char T2CKPS1:1;
989 unsigned char TMR2ON:1;
990 unsigned char TOUTPS0:1;
991 unsigned char TOUTPS1:1;
992 unsigned char TOUTPS2:1;
993 unsigned char TOUTPS3:1;
997 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
999 #define T2CKPS0 T2CON_bits.T2CKPS0
1000 #define T2CKPS1 T2CON_bits.T2CKPS1
1001 #define TMR2ON T2CON_bits.TMR2ON
1002 #define TOUTPS0 T2CON_bits.TOUTPS0
1003 #define TOUTPS1 T2CON_bits.TOUTPS1
1004 #define TOUTPS2 T2CON_bits.TOUTPS2
1005 #define TOUTPS3 T2CON_bits.TOUTPS3
1007 // ----- TRISE bits --------------------
1010 unsigned char TRISE0:1;
1011 unsigned char TRISE1:1;
1012 unsigned char TRISE2:1;
1014 unsigned char PSPMODE:1;
1015 unsigned char IBOV:1;
1016 unsigned char OBF:1;
1017 unsigned char IBF:1;
1020 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1022 #define TRISE0 TRISE_bits.TRISE0
1023 #define TRISE1 TRISE_bits.TRISE1
1024 #define TRISE2 TRISE_bits.TRISE2
1025 #define PSPMODE TRISE_bits.PSPMODE
1026 #define IBOV TRISE_bits.IBOV
1027 #define OBF TRISE_bits.OBF
1028 #define IBF TRISE_bits.IBF
1030 // ----- TXSTA bits --------------------
1033 unsigned char TX9D:1;
1034 unsigned char TRMT:1;
1035 unsigned char BRGH:1;
1037 unsigned char SYNC:1;
1038 unsigned char TXEN:1;
1039 unsigned char TX9:1;
1040 unsigned char CSRC:1;
1043 unsigned char TXD8:1;
1049 unsigned char NOT_TX8:1;
1059 unsigned char TX8_9:1;
1063 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1065 #define TX9D TXSTA_bits.TX9D
1066 #define TXD8 TXSTA_bits.TXD8
1067 #define TRMT TXSTA_bits.TRMT
1068 #define BRGH TXSTA_bits.BRGH
1069 #define SYNC TXSTA_bits.SYNC
1070 #define TXEN TXSTA_bits.TXEN
1071 #define TX9 TXSTA_bits.TX9
1072 #define NOT_TX8 TXSTA_bits.NOT_TX8
1073 #define TX8_9 TXSTA_bits.TX8_9
1074 #define CSRC TXSTA_bits.CSRC