2 // Register Declarations for Microchip 16F877A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define CMCON_ADDR 0x009C
76 #define CVRCON_ADDR 0x009D
77 #define ADRESL_ADDR 0x009E
78 #define ADCON1_ADDR 0x009F
79 #define EEDATA_ADDR 0x010C
80 #define EEADR_ADDR 0x010D
81 #define EEDATH_ADDR 0x010E
82 #define EEADRH_ADDR 0x010F
83 #define EECON1_ADDR 0x018C
84 #define EECON2_ADDR 0x018D
87 // Memory organization.
93 // P16F877A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F877A microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F877A
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
116 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
117 //1.01 09/13/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
118 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc)
120 //==========================================================================
124 //==========================================================================
127 // MESSG "Processor-header file mismatch. Verify selected processor."
130 //==========================================================================
132 // Register Definitions
134 //==========================================================================
139 //----- Register Files------------------------------------------------------
141 extern __data __at (INDF_ADDR) volatile char INDF;
142 extern __sfr __at (TMR0_ADDR) TMR0;
143 extern __data __at (PCL_ADDR) volatile char PCL;
144 extern __sfr __at (STATUS_ADDR) STATUS;
145 extern __sfr __at (FSR_ADDR) FSR;
146 extern __sfr __at (PORTA_ADDR) PORTA;
147 extern __sfr __at (PORTB_ADDR) PORTB;
148 extern __sfr __at (PORTC_ADDR) PORTC;
149 extern __sfr __at (PORTD_ADDR) PORTD;
150 extern __sfr __at (PORTE_ADDR) PORTE;
151 extern __sfr __at (PCLATH_ADDR) PCLATH;
152 extern __sfr __at (INTCON_ADDR) INTCON;
153 extern __sfr __at (PIR1_ADDR) PIR1;
154 extern __sfr __at (PIR2_ADDR) PIR2;
155 extern __sfr __at (TMR1L_ADDR) TMR1L;
156 extern __sfr __at (TMR1H_ADDR) TMR1H;
157 extern __sfr __at (T1CON_ADDR) T1CON;
158 extern __sfr __at (TMR2_ADDR) TMR2;
159 extern __sfr __at (T2CON_ADDR) T2CON;
160 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
161 extern __sfr __at (SSPCON_ADDR) SSPCON;
162 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
163 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
164 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
165 extern __sfr __at (RCSTA_ADDR) RCSTA;
166 extern __sfr __at (TXREG_ADDR) TXREG;
167 extern __sfr __at (RCREG_ADDR) RCREG;
168 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
169 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
170 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
171 extern __sfr __at (ADRESH_ADDR) ADRESH;
172 extern __sfr __at (ADCON0_ADDR) ADCON0;
174 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
175 extern __sfr __at (TRISA_ADDR) TRISA;
176 extern __sfr __at (TRISB_ADDR) TRISB;
177 extern __sfr __at (TRISC_ADDR) TRISC;
178 extern __sfr __at (TRISD_ADDR) TRISD;
179 extern __sfr __at (TRISE_ADDR) TRISE;
180 extern __sfr __at (PIE1_ADDR) PIE1;
181 extern __sfr __at (PIE2_ADDR) PIE2;
182 extern __sfr __at (PCON_ADDR) PCON;
183 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
184 extern __sfr __at (PR2_ADDR) PR2;
185 extern __sfr __at (SSPADD_ADDR) SSPADD;
186 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
187 extern __sfr __at (TXSTA_ADDR) TXSTA;
188 extern __sfr __at (SPBRG_ADDR) SPBRG;
189 extern __sfr __at (CMCON_ADDR) CMCON;
190 extern __sfr __at (CVRCON_ADDR) CVRCON;
191 extern __sfr __at (ADRESL_ADDR) ADRESL;
192 extern __sfr __at (ADCON1_ADDR) ADCON1;
194 extern __sfr __at (EEDATA_ADDR) EEDATA;
195 extern __sfr __at (EEADR_ADDR) EEADR;
196 extern __sfr __at (EEDATH_ADDR) EEDATH;
197 extern __sfr __at (EEADRH_ADDR) EEADRH;
199 extern __sfr __at (EECON1_ADDR) EECON1;
200 extern __sfr __at (EECON2_ADDR) EECON2;
202 //----- STATUS Bits --------------------------------------------------------
205 //----- INTCON Bits --------------------------------------------------------
208 //----- PIR1 Bits ----------------------------------------------------------
211 //----- PIR2 Bits ----------------------------------------------------------
214 //----- T1CON Bits ---------------------------------------------------------
217 //----- T2CON Bits ---------------------------------------------------------
220 //----- SSPCON Bits --------------------------------------------------------
223 //----- CCP1CON Bits -------------------------------------------------------
226 //----- RCSTA Bits ---------------------------------------------------------
229 //----- CCP2CON Bits -------------------------------------------------------
232 //----- ADCON0 Bits --------------------------------------------------------
235 //----- OPTION Bits -----------------------------------------------------
238 //----- TRISE Bits ---------------------------------------------------------
241 //----- PIE1 Bits ----------------------------------------------------------
244 //----- PIE2 Bits ----------------------------------------------------------
247 //----- PCON Bits ----------------------------------------------------------
250 //----- SSPCON2 Bits --------------------------------------------------------
253 //----- SSPSTAT Bits -------------------------------------------------------
256 //----- TXSTA Bits ---------------------------------------------------------
260 //----- CMCON Bits ---------------------------------------------------------
262 //----- CVRCON Bits --------------------------------------------------------
264 //----- ADCON1 Bits --------------------------------------------------------
267 //----- EECON1 Bits --------------------------------------------------------
270 //==========================================================================
274 //==========================================================================
277 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
278 // __BADRAM H'105', H'107'-H'109'
279 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
281 //==========================================================================
283 // Configuration Bits
285 //==========================================================================
287 #define _CP_ALL 0x1FFF
288 #define _CP_OFF 0x3FFF
289 #define _DEBUG_OFF 0x3FFF
290 #define _DEBUG_ON 0x37FF
291 #define _WRT_OFF 0x3FFF // No prog memmory write protection
292 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
293 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
294 #define _WRT_HALF 0x39FF // First half memmory write protected
295 #define _CPD_OFF 0x3FFF
296 #define _CPD_ON 0x3EFF
297 #define _LVP_ON 0x3FFF
298 #define _LVP_OFF 0x3F7F
299 #define _BODEN_ON 0x3FFF
300 #define _BODEN_OFF 0x3FBF
301 #define _PWRTE_OFF 0x3FFF
302 #define _PWRTE_ON 0x3FF7
303 #define _WDT_ON 0x3FFF
304 #define _WDT_OFF 0x3FFB
305 #define _RC_OSC 0x3FFF
306 #define _HS_OSC 0x3FFE
307 #define _XT_OSC 0x3FFD
308 #define _LP_OSC 0x3FFC
312 // ----- ADCON0 bits --------------------
315 unsigned char ADON:1;
318 unsigned char CHS0:1;
319 unsigned char CHS1:1;
320 unsigned char CHS2:1;
321 unsigned char ADCS0:1;
322 unsigned char ADCS1:1;
327 unsigned char NOT_DONE:1;
337 unsigned char GO_DONE:1;
345 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
347 #define ADON ADCON0_bits.ADON
348 #define GO ADCON0_bits.GO
349 #define NOT_DONE ADCON0_bits.NOT_DONE
350 #define GO_DONE ADCON0_bits.GO_DONE
351 #define CHS0 ADCON0_bits.CHS0
352 #define CHS1 ADCON0_bits.CHS1
353 #define CHS2 ADCON0_bits.CHS2
354 #define ADCS0 ADCON0_bits.ADCS0
355 #define ADCS1 ADCON0_bits.ADCS1
357 // ----- ADCON1 bits --------------------
360 unsigned char PCFG0:1;
361 unsigned char PCFG1:1;
362 unsigned char PCFG2:1;
363 unsigned char PCFG3:1;
367 unsigned char ADFM:1;
370 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
372 #define PCFG0 ADCON1_bits.PCFG0
373 #define PCFG1 ADCON1_bits.PCFG1
374 #define PCFG2 ADCON1_bits.PCFG2
375 #define PCFG3 ADCON1_bits.PCFG3
376 #define ADFM ADCON1_bits.ADFM
378 // ----- CCP1CON bits --------------------
381 unsigned char CCP1M0:1;
382 unsigned char CCP1M1:1;
383 unsigned char CCP1M2:1;
384 unsigned char CCP1M3:1;
385 unsigned char CCP1Y:1;
386 unsigned char CCP1X:1;
391 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
393 #define CCP1M0 CCP1CON_bits.CCP1M0
394 #define CCP1M1 CCP1CON_bits.CCP1M1
395 #define CCP1M2 CCP1CON_bits.CCP1M2
396 #define CCP1M3 CCP1CON_bits.CCP1M3
397 #define CCP1Y CCP1CON_bits.CCP1Y
398 #define CCP1X CCP1CON_bits.CCP1X
400 // ----- CCP2CON bits --------------------
403 unsigned char CCP2M0:1;
404 unsigned char CCP2M1:1;
405 unsigned char CCP2M2:1;
406 unsigned char CCP2M3:1;
407 unsigned char CCP2Y:1;
408 unsigned char CCP2X:1;
413 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
415 #define CCP2M0 CCP2CON_bits.CCP2M0
416 #define CCP2M1 CCP2CON_bits.CCP2M1
417 #define CCP2M2 CCP2CON_bits.CCP2M2
418 #define CCP2M3 CCP2CON_bits.CCP2M3
419 #define CCP2Y CCP2CON_bits.CCP2Y
420 #define CCP2X CCP2CON_bits.CCP2X
422 // ----- CMCON bits --------------------
429 unsigned char C1INV:1;
430 unsigned char C2INV:1;
431 unsigned char C1OUT:1;
432 unsigned char C2OUT:1;
435 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
437 #define CM0 CMCON_bits.CM0
438 #define CM1 CMCON_bits.CM1
439 #define CM2 CMCON_bits.CM2
440 #define CIS CMCON_bits.CIS
441 #define C1INV CMCON_bits.C1INV
442 #define C2INV CMCON_bits.C2INV
443 #define C1OUT CMCON_bits.C1OUT
444 #define C2OUT CMCON_bits.C2OUT
446 // ----- CVRCON bits --------------------
449 unsigned char CVR0:1;
450 unsigned char CVR1:1;
451 unsigned char CVR2:1;
452 unsigned char CVR3:1;
454 unsigned char CVRR:1;
455 unsigned char CVROE:1;
456 unsigned char CVREN:1;
459 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
461 #define CVR0 CVRCON_bits.CVR0
462 #define CVR1 CVRCON_bits.CVR1
463 #define CVR2 CVRCON_bits.CVR2
464 #define CVR3 CVRCON_bits.CVR3
465 #define CVRR CVRCON_bits.CVRR
466 #define CVROE CVRCON_bits.CVROE
467 #define CVREN CVRCON_bits.CVREN
469 // ----- EECON1 bits --------------------
474 unsigned char WREN:1;
475 unsigned char WRERR:1;
479 unsigned char EEPGD:1;
482 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
484 #define RD EECON1_bits.RD
485 #define WR EECON1_bits.WR
486 #define WREN EECON1_bits.WREN
487 #define WRERR EECON1_bits.WRERR
488 #define EEPGD EECON1_bits.EEPGD
490 // ----- INTCON bits --------------------
493 unsigned char RBIF:1;
494 unsigned char INTF:1;
495 unsigned char T0IF:1;
496 unsigned char RBIE:1;
497 unsigned char INTE:1;
498 unsigned char T0IE:1;
499 unsigned char PEIE:1;
505 unsigned char TMR0IF:1;
508 unsigned char TMR0IE:1;
513 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
515 #define RBIF INTCON_bits.RBIF
516 #define INTF INTCON_bits.INTF
517 #define T0IF INTCON_bits.T0IF
518 #define TMR0IF INTCON_bits.TMR0IF
519 #define RBIE INTCON_bits.RBIE
520 #define INTE INTCON_bits.INTE
521 #define T0IE INTCON_bits.T0IE
522 #define TMR0IE INTCON_bits.TMR0IE
523 #define PEIE INTCON_bits.PEIE
524 #define GIE INTCON_bits.GIE
526 // ----- OPTION_REG bits --------------------
533 unsigned char T0SE:1;
534 unsigned char T0CS:1;
535 unsigned char INTEDG:1;
536 unsigned char NOT_RBPU:1;
538 } __OPTION_REG_bits_t;
539 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
541 #define PS0 OPTION_REG_bits.PS0
542 #define PS1 OPTION_REG_bits.PS1
543 #define PS2 OPTION_REG_bits.PS2
544 #define PSA OPTION_REG_bits.PSA
545 #define T0SE OPTION_REG_bits.T0SE
546 #define T0CS OPTION_REG_bits.T0CS
547 #define INTEDG OPTION_REG_bits.INTEDG
548 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
550 // ----- PCON bits --------------------
553 unsigned char NOT_BO:1;
554 unsigned char NOT_POR:1;
563 unsigned char NOT_BOR:1;
573 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
575 #define NOT_BO PCON_bits.NOT_BO
576 #define NOT_BOR PCON_bits.NOT_BOR
577 #define NOT_POR PCON_bits.NOT_POR
579 // ----- PIE1 bits --------------------
582 unsigned char TMR1IE:1;
583 unsigned char TMR2IE:1;
584 unsigned char CCP1IE:1;
585 unsigned char SSPIE:1;
586 unsigned char TXIE:1;
587 unsigned char RCIE:1;
588 unsigned char ADIE:1;
589 unsigned char PSPIE:1;
592 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
594 #define TMR1IE PIE1_bits.TMR1IE
595 #define TMR2IE PIE1_bits.TMR2IE
596 #define CCP1IE PIE1_bits.CCP1IE
597 #define SSPIE PIE1_bits.SSPIE
598 #define TXIE PIE1_bits.TXIE
599 #define RCIE PIE1_bits.RCIE
600 #define ADIE PIE1_bits.ADIE
601 #define PSPIE PIE1_bits.PSPIE
603 // ----- PIE2 bits --------------------
606 unsigned char CCP2IE:1;
609 unsigned char BCLIE:1;
610 unsigned char EEIE:1;
612 unsigned char CMIE:1;
616 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
618 #define CCP2IE PIE2_bits.CCP2IE
619 #define BCLIE PIE2_bits.BCLIE
620 #define EEIE PIE2_bits.EEIE
621 #define CMIE PIE2_bits.CMIE
623 // ----- PIR1 bits --------------------
626 unsigned char TMR1IF:1;
627 unsigned char TMR2IF:1;
628 unsigned char CCP1IF:1;
629 unsigned char SSPIF:1;
630 unsigned char TXIF:1;
631 unsigned char RCIF:1;
632 unsigned char ADIF:1;
633 unsigned char PSPIF:1;
636 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
638 #define TMR1IF PIR1_bits.TMR1IF
639 #define TMR2IF PIR1_bits.TMR2IF
640 #define CCP1IF PIR1_bits.CCP1IF
641 #define SSPIF PIR1_bits.SSPIF
642 #define TXIF PIR1_bits.TXIF
643 #define RCIF PIR1_bits.RCIF
644 #define ADIF PIR1_bits.ADIF
645 #define PSPIF PIR1_bits.PSPIF
647 // ----- PIR2 bits --------------------
650 unsigned char CCP2IF:1;
653 unsigned char BCLIF:1;
654 unsigned char EEIF:1;
656 unsigned char CMIF:1;
660 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
662 #define CCP2IF PIR2_bits.CCP2IF
663 #define BCLIF PIR2_bits.BCLIF
664 #define EEIF PIR2_bits.EEIF
665 #define CMIF PIR2_bits.CMIF
667 // ----- RCSTA bits --------------------
670 unsigned char RX9D:1;
671 unsigned char OERR:1;
672 unsigned char FERR:1;
673 unsigned char ADDEN:1;
674 unsigned char CREN:1;
675 unsigned char SREN:1;
677 unsigned char SPEN:1;
680 unsigned char RCD8:1;
696 unsigned char NOT_RC8:1;
706 unsigned char RC8_9:1;
710 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
712 #define RX9D RCSTA_bits.RX9D
713 #define RCD8 RCSTA_bits.RCD8
714 #define OERR RCSTA_bits.OERR
715 #define FERR RCSTA_bits.FERR
716 #define ADDEN RCSTA_bits.ADDEN
717 #define CREN RCSTA_bits.CREN
718 #define SREN RCSTA_bits.SREN
719 #define RX9 RCSTA_bits.RX9
720 #define RC9 RCSTA_bits.RC9
721 #define NOT_RC8 RCSTA_bits.NOT_RC8
722 #define RC8_9 RCSTA_bits.RC8_9
723 #define SPEN RCSTA_bits.SPEN
725 // ----- SSPCON bits --------------------
728 unsigned char SSPM0:1;
729 unsigned char SSPM1:1;
730 unsigned char SSPM2:1;
731 unsigned char SSPM3:1;
733 unsigned char SSPEN:1;
734 unsigned char SSPOV:1;
735 unsigned char WCOL:1;
738 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
740 #define SSPM0 SSPCON_bits.SSPM0
741 #define SSPM1 SSPCON_bits.SSPM1
742 #define SSPM2 SSPCON_bits.SSPM2
743 #define SSPM3 SSPCON_bits.SSPM3
744 #define CKP SSPCON_bits.CKP
745 #define SSPEN SSPCON_bits.SSPEN
746 #define SSPOV SSPCON_bits.SSPOV
747 #define WCOL SSPCON_bits.WCOL
749 // ----- SSPCON2 bits --------------------
753 unsigned char RSEN:1;
755 unsigned char RCEN:1;
756 unsigned char ACKEN:1;
757 unsigned char ACKDT:1;
758 unsigned char ACKSTAT:1;
759 unsigned char GCEN:1;
762 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
764 #define SEN SSPCON2_bits.SEN
765 #define RSEN SSPCON2_bits.RSEN
766 #define PEN SSPCON2_bits.PEN
767 #define RCEN SSPCON2_bits.RCEN
768 #define ACKEN SSPCON2_bits.ACKEN
769 #define ACKDT SSPCON2_bits.ACKDT
770 #define ACKSTAT SSPCON2_bits.ACKSTAT
771 #define GCEN SSPCON2_bits.GCEN
773 // ----- SSPSTAT bits --------------------
788 unsigned char I2C_READ:1;
789 unsigned char I2C_START:1;
790 unsigned char I2C_STOP:1;
791 unsigned char I2C_DATA:1;
798 unsigned char NOT_W:1;
801 unsigned char NOT_A:1;
808 unsigned char NOT_WRITE:1;
811 unsigned char NOT_ADDRESS:1;
828 unsigned char READ_WRITE:1;
831 unsigned char DATA_ADDRESS:1;
836 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
838 #define BF SSPSTAT_bits.BF
839 #define UA SSPSTAT_bits.UA
840 #define R SSPSTAT_bits.R
841 #define I2C_READ SSPSTAT_bits.I2C_READ
842 #define NOT_W SSPSTAT_bits.NOT_W
843 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
844 #define R_W SSPSTAT_bits.R_W
845 #define READ_WRITE SSPSTAT_bits.READ_WRITE
846 #define S SSPSTAT_bits.S
847 #define I2C_START SSPSTAT_bits.I2C_START
848 #define P SSPSTAT_bits.P
849 #define I2C_STOP SSPSTAT_bits.I2C_STOP
850 #define D SSPSTAT_bits.D
851 #define I2C_DATA SSPSTAT_bits.I2C_DATA
852 #define NOT_A SSPSTAT_bits.NOT_A
853 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
854 #define D_A SSPSTAT_bits.D_A
855 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
856 #define CKE SSPSTAT_bits.CKE
857 #define SMP SSPSTAT_bits.SMP
859 // ----- STATUS bits --------------------
865 unsigned char NOT_PD:1;
866 unsigned char NOT_TO:1;
872 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
874 #define C STATUS_bits.C
875 #define DC STATUS_bits.DC
876 #define Z STATUS_bits.Z
877 #define NOT_PD STATUS_bits.NOT_PD
878 #define NOT_TO STATUS_bits.NOT_TO
879 #define RP0 STATUS_bits.RP0
880 #define RP1 STATUS_bits.RP1
881 #define IRP STATUS_bits.IRP
883 // ----- T1CON bits --------------------
886 unsigned char TMR1ON:1;
887 unsigned char TMR1CS:1;
888 unsigned char NOT_T1SYNC:1;
889 unsigned char T1OSCEN:1;
890 unsigned char T1CKPS0:1;
891 unsigned char T1CKPS1:1;
898 unsigned char T1INSYNC:1;
908 unsigned char T1SYNC:1;
916 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
918 #define TMR1ON T1CON_bits.TMR1ON
919 #define TMR1CS T1CON_bits.TMR1CS
920 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
921 #define T1INSYNC T1CON_bits.T1INSYNC
922 #define T1SYNC T1CON_bits.T1SYNC
923 #define T1OSCEN T1CON_bits.T1OSCEN
924 #define T1CKPS0 T1CON_bits.T1CKPS0
925 #define T1CKPS1 T1CON_bits.T1CKPS1
927 // ----- T2CON bits --------------------
930 unsigned char T2CKPS0:1;
931 unsigned char T2CKPS1:1;
932 unsigned char TMR2ON:1;
933 unsigned char TOUTPS0:1;
934 unsigned char TOUTPS1:1;
935 unsigned char TOUTPS2:1;
936 unsigned char TOUTPS3:1;
940 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
942 #define T2CKPS0 T2CON_bits.T2CKPS0
943 #define T2CKPS1 T2CON_bits.T2CKPS1
944 #define TMR2ON T2CON_bits.TMR2ON
945 #define TOUTPS0 T2CON_bits.TOUTPS0
946 #define TOUTPS1 T2CON_bits.TOUTPS1
947 #define TOUTPS2 T2CON_bits.TOUTPS2
948 #define TOUTPS3 T2CON_bits.TOUTPS3
950 // ----- TRISE bits --------------------
953 unsigned char TRISE0:1;
954 unsigned char TRISE1:1;
955 unsigned char TRISE2:1;
957 unsigned char PSPMODE:1;
958 unsigned char IBOV:1;
963 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
965 #define TRISE0 TRISE_bits.TRISE0
966 #define TRISE1 TRISE_bits.TRISE1
967 #define TRISE2 TRISE_bits.TRISE2
968 #define PSPMODE TRISE_bits.PSPMODE
969 #define IBOV TRISE_bits.IBOV
970 #define OBF TRISE_bits.OBF
971 #define IBF TRISE_bits.IBF
973 // ----- TXSTA bits --------------------
976 unsigned char TX9D:1;
977 unsigned char TRMT:1;
978 unsigned char BRGH:1;
980 unsigned char SYNC:1;
981 unsigned char TXEN:1;
983 unsigned char CSRC:1;
986 unsigned char TXD8:1;
992 unsigned char NOT_TX8:1;
1002 unsigned char TX8_9:1;
1006 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1008 #define TX9D TXSTA_bits.TX9D
1009 #define TXD8 TXSTA_bits.TXD8
1010 #define TRMT TXSTA_bits.TRMT
1011 #define BRGH TXSTA_bits.BRGH
1012 #define SYNC TXSTA_bits.SYNC
1013 #define TXEN TXSTA_bits.TXEN
1014 #define TX9 TXSTA_bits.TX9
1015 #define NOT_TX8 TXSTA_bits.NOT_TX8
1016 #define TX8_9 TXSTA_bits.TX8_9
1017 #define CSRC TXSTA_bits.CSRC