3 Small Device C Compiler (SDCC) - PIC16F877 Device Library Header 2004
5 Note an alterative header file can be generated from
6 inc files using peal script support/scripts/inc2h.pl
14 /*****************************************************************************
16 *****************************************************************************/
20 #pragma memmap 0x0020 0x006f RAM 0x000
21 #pragma memmap 0x0070 0x007f RAM 0x180
22 #pragma memmap 0x00a0 0x00ef RAM 0x000
23 #pragma memmap 0x0110 0x016f RAM 0x000
24 #pragma memmap 0x0190 0x01ef RAM 0x000
27 /*****************************************************************************
28 Special Function Register Addresses
29 *****************************************************************************/
55 ccp1con_addr = 0x0017,
61 ccp2con_addr = 0x001d,
64 option_reg_addr = 0x0081,
73 sspcon2_addr = 0x0091,
76 sspstat_addr = 0x0094,
90 /* Special function register memory map - memmap start_addr end_addr type bank_mask */
91 #pragma memmap 0x001 0x001 SFR 0x080
92 #pragma memmap 0x002 0x004 SFR 0x180
93 #pragma memmap 0x005 0x005 SFR 0x000
94 #pragma memmap 0x006 0x006 SFR 0x080
95 #pragma memmap 0x007 0x009 SFR 0x000
96 #pragma memmap 0x00a 0x00b SFR 0x180
97 #pragma memmap 0x00c 0x01f SFR 0x000
98 #pragma memmap 0x081 0x081 SFR 0x100
99 #pragma memmap 0x085 0x085 SFR 0x000
100 #pragma memmap 0x086 0x086 SFR 0x100
101 #pragma memmap 0x087 0x089 SFR 0x000
102 #pragma memmap 0x08c 0x08e SFR 0x000
103 #pragma memmap 0x091 0x094 SFR 0x000
104 #pragma memmap 0x098 0x099 SFR 0x000
105 #pragma memmap 0x09c 0x09f SFR 0x000
106 #pragma memmap 0x10c 0x10f SFR 0x000
107 #pragma memmap 0x18c 0x18d SFR 0x000
110 /*****************************************************************************
112 *****************************************************************************/
114 /* ---- STATUS Bits -------------------------------------------------------- */
117 unsigned c :1; /* Carry/borrow bit (ADDWF,ADDLW,SUBWF,SUBLW instructions) */
118 unsigned dc :1; /* Digit carry/borrow bit (ADDWF,ADDLW,SUBWF,SUBLW instructions) */
119 unsigned z :1; /* Zero bit */
120 unsigned not_pd :1; /* Power down bit */
121 unsigned not_to :1; /* Timeout bit */
122 unsigned rp0 :1; /* Register bank select bits for direct addressing */
124 unsigned irp :1; /* Register bank select bits for indirect addressing */
129 static volatile status_t at status_addr status_b;
131 #define DC status_b.dc
133 #define NOT_PD status_b.not_pd
134 #define NOT_TO status_b.not_to
135 #define RP0 status_b.rp0
136 #define RP1 status_b.rp1
137 #define IRP status_b.irp
139 /* ---- OPTION_REG Bits ----------------------------------------------------- */
142 unsigned ps0 :1; /* Prescaler rate select bits */
145 unsigned psa :1; /* Prescaler assignment bit */
146 unsigned t0se :1; /* TMR0 source edge select bit */
147 unsigned t0cs :1; /* TMR0 clock source select bit */
148 unsigned intedg :1; /* Interrupt edge select bit */
149 unsigned not_rbpu :1; /* PortB pullup enable bit */
157 static volatile option_reg_t at option_reg_addr option_reg_b;
158 #define PS0 option_reg_b.ps0
159 #define PS1 option_reg_b.ps1
160 #define PS2 option_reg_b.ps2
161 #define PSA option_reg_b.psa
162 #define T0SE option_reg_b.t0se
163 #define T0CS option_reg_b.t0cs
164 #define INTEDG option_reg_b.intedg
165 #define NOT_RBPU option_reg_b.not_rbpu
167 /* ---- PCON Bits ---------------------------------------------------------- */
170 unsigned not_bor :1; /* Brown out reset status bit */
171 unsigned not_por :1; /* Power on reset bit */
176 static volatile pcon_t at pcon_addr pcon_b;
177 #define NOT_BOR pcon_b.not_bor
178 #define NOT_POR pcon_b.not_por
180 /* ---- Misc Registers ----------------------------------------------------- */
181 static volatile unsigned char at indf_addr indf;
182 sfr at status_addr status;
184 sfr at pclath_addr pclath;
186 sfr at option_reg_addr option_reg;
187 sfr at pcon_addr pcon;
191 #define STATUS status
193 #define PCLATH pclath
195 #define OPTION_REG option_reg
201 /*****************************************************************************
203 *****************************************************************************/
226 /* --- PORTA Bits ---------------------------------------------------------- */
227 static volatile port_t at porta_addr porta_b;
228 #define PA0 porta_b.b0
229 #define PA1 porta_b.b1
230 #define PA2 porta_b.b2
231 #define PA3 porta_b.b3
232 #define PA4 porta_b.b4
233 #define PA5 porta_b.b5
234 #define PA6 porta_b.b6
235 #define PA7 porta_b.b7
237 /* --- PORTB Bits ---------------------------------------------------------- */
238 static volatile port_t at portb_addr portb_b;
239 #define PB0 portb_b.b0
240 #define PB1 portb_b.b1
241 #define PB2 portb_b.b2
242 #define PB3 portb_b.b3
243 #define PB4 portb_b.b4
244 #define PB5 portb_b.b5
245 #define PB6 portb_b.b6
246 #define PB7 portb_b.b7
248 /* --- PORTC Bits ---------------------------------------------------------- */
249 static volatile port_t at portc_addr portc_b;
250 #define PC0 portc_b.b0
251 #define PC1 portc_b.b1
252 #define PC2 portc_b.b2
253 #define PC3 portc_b.b3
254 #define PC4 portc_b.b4
255 #define PC5 portc_b.b5
256 #define PC6 portc_b.b6
257 #define PC7 portc_b.b7
259 /* --- PORTD Bits ---------------------------------------------------------- */
260 static volatile port_t at portd_addr portd_b;
261 #define PD0 portd_b.b0
262 #define PD1 portd_b.b1
263 #define PD2 portd_b.b2
264 #define PD3 portd_b.b3
265 #define PD4 portd_b.b4
266 #define PD5 portd_b.b5
267 #define PD6 portd_b.b6
268 #define PD7 portd_b.b7
270 /* --- PORTE Bits ---------------------------------------------------------- */
271 static volatile port_t at porte_addr porte_b;
272 #define RE0 porte_b.b0
273 #define RE1 porte_b.b1
274 #define RE2 porte_b.b2
276 /* --- TRISA Bits ---------------------------------------------------------- */
277 static volatile tris_t at trisa_addr trisa_b;
278 #define TRISA0 trisa_b.b0
279 #define TRISA1 trisa_b.b1
280 #define TRISA2 trisa_b.b2
281 #define TRISA3 trisa_b.b3
282 #define TRISA4 trisa_b.b4
283 #define TRISA5 trisa_b.b5
284 #define TRISA6 trisa_b.b6
285 #define TRISA7 trisa_b.b7
287 /* --- TRISB Bits ---------------------------------------------------------- */
288 static tris_t at trisb_addr trisb_b;
289 #define TRISB0 trisb_b.b0
290 #define TRISB1 trisb_b.b1
291 #define TRISB2 trisb_b.b2
292 #define TRISB3 trisb_b.b3
293 #define TRISB4 trisb_b.b4
294 #define TRISB5 trisb_b.b5
295 #define TRISB6 trisb_b.b6
296 #define TRISB7 trisb_b.b7
298 /* --- TRISC Bits ---------------------------------------------------------- */
299 static volatile tris_t at trisc_addr trisc_b;
300 #define TRISC0 trisc_b.b0
301 #define TRISC1 trisc_b.b1
302 #define TRISC2 trisc_b.b2
303 #define TRISC3 trisc_b.b3
304 #define TRISC4 trisc_b.b4
305 #define TRISC5 trisc_b.b5
306 #define TRISC6 trisc_b.b6
307 #define TRISC7 trisc_b.b7
309 /* --- TRISD Bits ---------------------------------------------------------- */
310 static volatile tris_t at trisd_addr trisd_b;
311 #define TRISD0 trisd_b.b0
312 #define TRISD1 trisd_b.b1
313 #define TRISD2 trisd_b.b2
314 #define TRISD3 trisd_b.b3
315 #define TRISD4 trisd_b.b4
316 #define TRISD5 trisd_b.b5
317 #define TRISD6 trisd_b.b6
318 #define TRISD7 trisd_b.b7
320 /* --- TRISE Bits ---------------------------------------------------------- */
323 unsigned bit0 :1; /* Data direction bits */
327 unsigned pspmode :1; /* Parrallel slave port mode select bit */
328 unsigned ibov :1; /* Input buffer overflow detect bit */
329 unsigned obf :1; /* Output buffer full status bit */
330 unsigned ibf :1; /* Input buffer full status bit */
339 static volatile trise_t at trise_addr trise_b;
340 #define TRISE0 trise_b.bit0
341 #define TRISE1 trise_b.bit1
342 #define TRISE2 trise_b.bit2
343 #define PSPMODE trise_b.pspmode
344 #define IBOV trise_b.ibov
345 #define OBF trise_b.obf
346 #define IBF trise_b.ibf
348 /* ---- Port Registers ----------------------------------------------------- */
349 sfr at porta_addr porta;
350 sfr at portb_addr portb;
351 sfr at portc_addr portc;
352 sfr at portd_addr portd;
353 sfr at porte_addr porte;
354 sfr at trisa_addr trisa;
355 sfr at trisb_addr trisb;
356 sfr at trisc_addr trisc;
357 sfr at trisd_addr trisd;
358 sfr at trise_addr trise;
371 /*****************************************************************************
373 *****************************************************************************/
375 /* ---- INTCON Bits -------------------------------------------------------- */
378 unsigned rbif :1; /* RB port change interrupt flag bit */
379 unsigned ntf :1; /* RB0/INT external interrupt flag bit */
380 unsigned tmr0if :1; /* TMR0 overflow interrupt flag bit */
381 unsigned rbie :1; /* RB port change interrupt enable bit */
382 unsigned inte :1; /* RB0/INT external interrupt enable */
383 unsigned tmr0ie :1; /* TMR0 over flow interrupt enble bit */
384 unsigned peie :1; /* Peripheral interrupt enable bit */
385 unsigned gie :1; /* Global interrupt enable bit */
390 static volatile intcon_t at intcon_addr intcon_b;
391 #define RBIF intcon_b.rbif
392 #define NTF intcon_b.ntf
393 #define T0IF intcon_b.tmr0if
394 #define RBIE intcon_b.rbie
395 #define INTE intcon_b.inte
396 #define T0IE intcon_b.tmr0ie
397 #define PEIE intcon_b.peie
398 #define GIE intcon_b.gie
400 /* ---- PIR1 Bits ---------------------------------------------------------- */
403 unsigned tmr1if :1; /* Tmr1 overflow interrupt flag bit */
404 unsigned tmr2if :1; /* TMR2 to PR2 match interrupt flag bit */
405 unsigned ccp1if :1; /* CCP1 interrupt flag bit */
406 unsigned sspif :1; /* Synchronous serial port interrupt flag bit */
407 unsigned txif :1; /* USART transmit interrupt flag bit */
408 unsigned rcif :1; /* USART receiver interrupt flag bit */
409 unsigned adif :1; /* A/D converter interrupt flag bit */
410 unsigned pspif :1; /* Parrallel slave port read/write interrupt flag bit */
415 static volatile pir1_t at pir1_addr pir1_b;
416 #define TMR1IF pir1_b.tmr1if
417 #define TMR2IF pir1_b.tmr2if
418 #define CCP1IF pir1_b.ccp1if
419 #define SSPIF pir1_b.sspif
420 #define TXIF pir1_b.txif
421 #define RCIF pir1_b.rcif
422 #define ADIF pir1_b.adif
423 #define PSPIF pir1_b.pspif
425 /* ---- PIR2 Bits ---------------------------------------------------------- */
428 unsigned ccp2if :1; /* CCP2 interrupt enable bit */
431 unsigned bclif :1; /* Bus collision interrupt enable bit */
432 unsigned eeif :1; /* EEPROM write operation interrupt enable bit */
434 unsigned cmif :1; /* Comparitor interrupt flag bit */
439 static volatile pir2_t at pir2_addr pir2_b;
440 #define CCP2IF pir2_b.ccp2if
441 #define BCLIF pir2_b.bclif
442 #define EEIF pir2_b.eeif
444 /* ---- PIE1 Bits ---------------------------------------------------------- */
447 unsigned tmr1ie :1; /* Tmr1 overflow interrupt enable bit */
448 unsigned tmr2ie :1; /* TMR2 to PR2 match interrupt enable bit */
449 unsigned ccp1ie :1; /* CCP1 interrupt enable bit */
450 unsigned sspie :1; /* Synchronous serial port interrupt enable bit */
451 unsigned txie :1; /* USART transmit interrupt enable bit */
452 unsigned rcie :1; /* USART receiver interrupt enable bit */
453 unsigned adie :1; /* A/D converter interrupt enable bit */
454 unsigned pspie :1; /* Parrallel slave port read/write interrupt enable bit */
459 static volatile pie1_t at pie1_addr pie1_b;
460 #define TMR1IE pie1_b.tmr1ie
461 #define TMR2IE pie1_b.tmr2ie
462 #define CCP1IE pie1_b.ccp1ie
463 #define SSPIE pie1_b.sspie
464 #define TXIE pie1_b.txie
465 #define RCIE pie1_b.rcie
466 #define ADIE pie1_b.adie
467 #define PSPIE pie1_b.pspie
469 /* ---- PIE2 Bits ---------------------------------------------------------- */
472 unsigned ccp2ie :1; /* CCP2 interrupt enable bit */
475 unsigned bclie :1; /* Bus collision interrupt enable bit */
476 unsigned eeie :1; /* EEPROM write operation interrupt enable bit */
478 unsigned cmie :1; /* Comparitor interrupt enable bit */
483 static volatile pie2_t at pie2_addr pie2_b;
484 #define CCP2IE pie2_b.ccp2ie
485 #define BCLIE pie2_b.bclie
486 #define EEIE pie2_b.eeie
487 #define CMIE pie2_b.cmie
489 /* ---- Interrupt Registers ------------------------------------------------ */
490 sfr at intcon_addr intcon;
491 sfr at pir1_addr pir1;
492 sfr at pir2_addr pir2;
493 sfr at pie1_addr pie1;
494 sfr at pie2_addr pie2;
496 #define INTCON intcon
502 /*****************************************************************************
504 *****************************************************************************/
506 /* ---- T1CON Bits --------------------------------------------------------- */
509 unsigned tmr1on :1; /* Timer1 on bit */
510 unsigned tmr1cs :1; /* Timer1 clock source select bit */
511 unsigned t1sync :1; /* Timer1 external clock input synchronization control bit */
512 unsigned t1oscen :1; /* Timer1 oscilator enable control bit */
513 unsigned t1ckps0 :1; /* Timer1 input clock prescale select bits */
521 unsigned t1ckps :2; /* Timer1 input clock prescale select bits */
527 static volatile t1con_t at t1con_addr t1con_b;
528 #define TMR1ON t1con_b.tmr1on
529 #define TMR1CS t1con_b.tmr1cs
530 #define T1SYNC t1con_b.t1sync
531 #define NOT_T1SYNC t1con_b.t1sync
532 #define T1OSCEN t1con_b.t1oscen
533 #define T1CKPS0 t1con_b.t1ckps0
534 #define T1CKPS1 t1con_b.t1ckps1
536 /* ---- T2CON Bits --------------------------------------------------------- */
539 unsigned t2ckps0 :1; /* Timer2 clock prescale select bits */
541 unsigned tmr2on :1; /* Timer2 on bit */
543 unsigned toutps1 :1; /* Timer2 output postscale selet bits */
548 unsigned t2ckps :2; /* Timer2 clock prescale select bits */
550 unsigned toutps :4; /* Timer2 output postscale selet bits */
555 static volatile t2con_t at t2con_addr t2con_b;
556 #define T2CKPS0 t2con_b.t2ckps0
557 #define T2CKPS1 t2con_b.t2ckps1
558 #define TMR2ON t2con_b.tmr2on
559 #define TOUTPS0 t2con_b.toutps0
560 #define TOUTPS1 t2con_b.toutps1
561 #define TOUTPS2 t2con_b.toutps2
562 #define TOUTPS3 t2con_b.toutps3
564 /* ---- Timer Registers ---------------------------------------------------- */
565 sfr at tmr0_addr tmr0;
566 sfr at tmr1l_addr tmr1l;
567 sfr at tmr1h_addr tmr1h;
568 sfr at tmr2_addr tmr2;
569 sfr at t1con_addr t1con;
570 sfr at t2con_addr t2con;
580 /*****************************************************************************
582 *****************************************************************************/
584 /* ----- CCPCON Bits -------------------------------------------------------- */
587 unsigned ccpm0 :1; /* CCPx mode select bits */
591 unsigned ccpy :1; /* PWM least significant bits */
595 unsigned ccpm :4; /* CCPx mode select bits */
600 static volatile ccpcon_t at ccp1con_addr ccp1con_b;
601 #define CCP1M0 ccp1con_b.ccpm0
602 #define CCP1M1 ccp1con_b.ccpm1
603 #define CCP1M2 ccp1con_b.ccpm2
604 #define CCP1M3 ccp1con_b.ccpm3
605 #define CCP1Y ccp1con_b.ccpy
606 #define CCP1X ccp1con_b.ccpx
608 static volatile ccpcon_t at ccp2con_addr ccp2con_b;
609 #define CCP2M0 ccp2con_b.ccpm0
610 #define CCP2M1 ccp2con_b.ccpm1
611 #define CCP2M2 ccp2con_b.ccpm2
612 #define CCP2M3 ccp2con_b.ccpm3
613 #define CCP2Y ccp2con_b.ccpy
614 #define CCP2X ccp2con_b.ccpx
616 /* ---- Timer Registers ---------------------------------------------------- */
617 sfr at ccpr1l_addr CCPR1L;
618 sfr at ccpr1h_addr CCPR1H;
619 sfr at ccp1con_addr CCP1CON;
620 sfr at ccpr2l_addr CCPR2L;
621 sfr at ccpr2h_addr CCPR2H;
622 sfr at ccp2con_addr CCP2CON;
625 /*****************************************************************************
627 *****************************************************************************/
629 /* ---- SSPCON Bits -------------------------------------------------------- */
632 unsigned sspm0 :1; /* Synchronous serial port mode select bits */
636 unsigned ckp :1; /* Clock polarity select bits */
637 unsigned sspen :1; /* Synchronous serial port enable bits */
638 unsigned sspov :1; /* Receive overflow indicator bit */
639 unsigned wcol :1; /* Write collision dedect bit */
642 unsigned sspm :4; /* Synchronous serial port mode select bits */
647 static volatile sspcon_t at sspcon_addr sspcon_b;
648 #define SSPM0 sspcon_b.sspm0
649 #define SSPM1 sspcon_b.sspm1
650 #define SSPM2 sspcon_b.sspm2
651 #define SSPM3 sspcon_b.sspm3
652 #define CKP sspcon_b.ckp
653 #define SSPEN sspcon_b.sspen
654 #define SSPOV sspcon_b.sspov
655 #define WCOL sspcon_b.wcol
657 /* ---- SSPCON2 Bits -------------------------------------------------------- */
660 unsigned sen :1; /* START condition enabled/stretch enabled bit */
661 unsigned rsen :1; /* Repeated START condition enabled bit */
662 unsigned pen :1; /* STOP condition enable bit */
663 unsigned rcen :1; /* Receive enable bit */
664 unsigned acken :1; /* Acknowledge sequence enable bit */
665 unsigned ackdt :1; /* Acknowledge data bit (master receive mode only) */
666 unsigned ackstat :1; /* Acknowledge status bit (master transmit mode only) */
667 unsigned gcen :1; /* General call enable bit */
672 static volatile sspcon2_t at sspcon2_addr sspcon2_b;
673 #define SEN sspcon2_b.sen
674 #define RSEN sspcon2_b.rsen
675 #define PEN sspcon2_b.pen
676 #define RCEN sspcon2_b.rcen
677 #define ACKEN sspcon2_b.acken
678 #define ACKDT sspcon2_b.ackdt
679 #define ACKSTAT sspcon2_b.ackstat
680 #define GCEN sspcon2_b.gcen
682 /* ---- SSPSTAT Bits ------------------------------------------------------- */
685 unsigned bf :1; /* Buffer full status bit (Receive mode only) */
686 unsigned ua :1; /* Update address bit used in I2C mode only */
687 unsigned r_w :1; /* Read write bit information used in I2C mode only */
688 unsigned s :1; /* Start bit used in I2C mode only */
689 unsigned p :1; /* Stop bit used in I2C mode only */
690 unsigned d_a :1; /* Data address bit used in I2C mode only */
691 unsigned cke :1; /* SPI clock select edge bit */
692 unsigned smp :1; /* Sample bit */
697 static volatile sspstat_t at sspstat_addr sspstat_b;
698 #define BF sspstat_b.bf
699 #define UA sspstat_b.ua
700 #define R_W sspstat_b.r_w
701 #define R sspstat_b.r_w
702 #define I2C_READ sspstat_b.r_w
703 #define NOT_W sspstat_b.r_w
704 #define NOT_WRITE sspstat_b.r_w
705 #define READ_WRITE sspstat_b.r_w
706 #define S sspstat_b.s
707 #define I2C_START sspstat_b.s
708 #define P sspstat_b.p
709 #define I2C_STOP sspstat_b.p
710 #define D_A sspstat_b.d_a
711 #define D sspstat_b.d_a
712 #define I2C_DATA sspstat_b.d_a
713 #define NOT_A sspstat_b.d_a
714 #define NOT_ADDRESS sspstat_b.d_a
715 #define DATA_ADDRESS sspstat_b.d_a
716 #define CKE sspstat_b.cke
717 #define SMP sspstat_b.smp
719 /* ---- SSP Registers ------------------------------------------------------ */
720 sfr at sspbuf_addr sspbuf;
721 sfr at sspcon_addr sspcon;
722 sfr at sspcon2_addr sspcon2;
723 sfr at sspadd_addr sspadd;
724 sfr at sspstat_addr sspstat;
725 sfr at sspstat_addr sspstat;
726 sfr at sspcon2_addr sspcon2;
727 sfr at sspcon_addr sspcon;
729 #define SSPBUF sspbuf
730 #define SSPCON sspcon
731 #define SSPCON2 sspcon2
732 #define SSPADD sspadd
733 #define SSPSTAT sspstat
735 /*****************************************************************************
737 *****************************************************************************/
739 /* ---- RCSTA Bits --------------------------------------------------------- */
742 unsigned rx9d :1; /* 9the bit of received data (can be parity bit but must be calculated by user firmware */
743 unsigned oerr :1; /* Overrun error bit */
744 unsigned ferr :1; /* Framing error bit */
745 unsigned adden :1; /* Address detect enable bit */
746 unsigned cren :1; /* Continuous receive enable bit */
747 unsigned sren :1; /* Single receive enable bit */
748 unsigned rx9 :1; /* 9th bit receive enable bit */
749 unsigned spen :1; /* Serial port enbale bit */
754 static volatile rcsta_t at rcsta_addr rcsta_b;
755 #define SPEN rcsta_b.spen
756 #define RX9 rcsta_b.rx9
757 #define SREN rcsta_b.sren
758 #define CREN rcsta_b.cren
759 #define ADDEN rcsta_b.adden
760 #define FERR rcsta_b.ferr
761 #define OERR rcsta_b.oerr
762 #define RX9D rcsta_b.rx9d
764 /* ---- TXSTA Bits --------------------------------------------------------- */
767 unsigned tx9d :1; /* 9th bit of transmit data, can be parity */
768 unsigned trmt :1; /* Transmit shift register status bit */
769 unsigned brgh :1; /* High baud rate select bit */
771 unsigned sync :1; /* USART mode select bit */
772 unsigned txen :1; /* Transmit enable bit */
773 unsigned tx9 :1; /* 9th bit transmit enable */
774 unsigned csrc :1; /* Clock source select bit */
779 static volatile txsta_t at txsta_addr txsta_b;
780 #define CSRC txsta_b.csrc
781 #define TX9 txsta_b.tx9
782 #define TXEN txsta_b.txen
783 #define SYNC txsta_b.sync
784 #define BRGH txsta_b.brgh
785 #define TRMT txsta_b.trmt
786 #define TX9D txsta_b.tx9d
788 /* ---- USART Registers ---------------------------------------------------- */
789 sfr at spbrg_addr spbrg;
790 sfr at rcreg_addr rcreg;
791 sfr at txreg_addr txreg;
792 sfr at rcsta_addr rcsta;
793 sfr at txsta_addr txsta;
801 /*****************************************************************************
803 *****************************************************************************/
805 /* ---- ADCON0 Bits -------------------------------------------------------- */
808 unsigned adon :1; /* A/D on bit */
810 unsigned go_done :1; /* A/D conversion start bit and not done status bit */
811 unsigned chs0 :1; /* Analog chanel select bits */
814 unsigned adcs0 :1; /* A/D conversion clock select bits */
820 unsigned chs :3; /* Analog chanel select bits */
821 unsigned adcs :2; /* A/D conversion clock select bits */
826 static volatile adcon0_t at adcon0_addr adcon0_b;
827 #define GO adcon0_b.go_done
828 #define NOT_DONE adcon0_b.go_done
829 #define GO_DONE adcon0_b.go_done
830 #define ADON adcon0_b.adon
831 #define CHS0 adcon0_b.chs0
832 #define CHS1 adcon0_b.chs1
833 #define CHS2 adcon0_b.chs2
834 #define ADCS0 adcon0_b.adcs0
835 #define ADCS1 adcon0_b.adcs1
837 /* ---- ADCON1 Bits -------------------------------------------------------- */
840 unsigned pcfg0 :1; /* A/D port configuration control bits */
845 unsigned adcs2 :1; /* A/D convertion clock select bit */
846 unsigned adfm :1; /* A/D result format select bit */
849 unsigned pcfg :4; /* A/D port configuration control bits */
854 static volatile adcon1_t at adcon1_addr adcon1_b;
855 #define PCFG0 adcon1_b.pcfg0
856 #define PCFG1 adcon1_b.pcfg1
857 #define PCFG2 adcon1_b.pcfg2
858 #define PCFG3 adcon1_b.pcfg3
859 #define ADFM adcon1_b.adfm
861 /* ---- ADC Registers ---------------------------------------------------- */
862 sfr at adresh_addr adresh;
863 sfr at adresh_addr adresl;
864 sfr at adcon0_addr adcon0;
865 sfr at adcon1_addr adcon1;
866 #define ADRESH adresh
867 #define ADRESL adresl
868 #define ADCON0 adcon0
869 #define ADCON1 adcon1
872 /*****************************************************************************
874 *****************************************************************************/
876 /* ---- EECON1 Bits -------------------------------------------------------- */
879 unsigned rd :1; /* Read control bit */
880 unsigned wr :1; /* Write control bit */
881 unsigned wren :1; /* EEPROM write enable bit */
882 unsigned wrerr :1; /* EEPROM error flag bit */
884 unsigned eepgd :1; /* Program data EEPROM select bit */
889 static volatile eecon1_t at eecon1_addr eecon1_b;
890 #define RD eecon1_b.rd
891 #define WR eecon1_b.wr
892 #define WREN eecon1_b.wren
893 #define WRERR eecon1_b.wrerr
894 #define EEPGD eecon1_b.eepgd
896 /* ---- EEPROM Registers ------------------------------------------------- */
897 sfr at eedata_addr eedata;
898 sfr at eeadr_addr eeadr;
899 sfr at eedath_addr eedath;
900 sfr at eeadrh_addr eeadrh;
901 sfr at eecon1_addr eecon1;
902 sfr at eecon2_addr eecon2;
904 #define EEDATA eedata
906 #define EEDATH eedath
907 #define EEADRH eeadrh
908 #define EECON1 eecon1
909 #define EECON2 eecon2
912 /*****************************************************************************
914 *****************************************************************************/
918 cp_upper_256 = 0x2fef,
922 wrt_enable_on = 0x3fff,
923 wrt_enable_off = 0x3dff,
940 #endif /* PIC16F877_H */