2 // Register Declarations for Microchip 16F877 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define ADRESL_ADDR 0x009E
76 #define ADCON1_ADDR 0x009F
77 #define EEDATA_ADDR 0x010C
78 #define EEADR_ADDR 0x010D
79 #define EEDATH_ADDR 0x010E
80 #define EEADRH_ADDR 0x010F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
85 // Memory organization.
91 // P16F877.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
94 // This header file defines configurations, registers, and other useful bits of
95 // information for the PIC16F877 microcontroller. These names are taken to match
96 // the data sheets as closely as possible.
98 // Note that the processor must be selected before this file is
99 // included. The processor may be selected the following ways:
101 // 1. Command line switch:
102 // C:\ MPASM MYFILE.ASM /PIC16F877
103 // 2. LIST directive in the source file
105 // 3. Processor Type entry in the MPASM full-screen interface
107 //==========================================================================
111 //==========================================================================
115 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
116 // to match datasheet (DS30292B)
117 //1.00 08/07/98 Initial Release
119 //==========================================================================
123 //==========================================================================
126 // MESSG "Processor-header file mismatch. Verify selected processor."
129 //==========================================================================
131 // Register Definitions
133 //==========================================================================
138 //----- Register Files------------------------------------------------------
140 extern __data __at (INDF_ADDR) volatile char INDF;
141 extern __sfr __at (TMR0_ADDR) TMR0;
142 extern __data __at (PCL_ADDR) volatile char PCL;
143 extern __sfr __at (STATUS_ADDR) STATUS;
144 extern __sfr __at (FSR_ADDR) FSR;
145 extern __sfr __at (PORTA_ADDR) PORTA;
146 extern __sfr __at (PORTB_ADDR) PORTB;
147 extern __sfr __at (PORTC_ADDR) PORTC;
148 extern __sfr __at (PORTD_ADDR) PORTD;
149 extern __sfr __at (PORTE_ADDR) PORTE;
150 extern __sfr __at (PCLATH_ADDR) PCLATH;
151 extern __sfr __at (INTCON_ADDR) INTCON;
152 extern __sfr __at (PIR1_ADDR) PIR1;
153 extern __sfr __at (PIR2_ADDR) PIR2;
154 extern __sfr __at (TMR1L_ADDR) TMR1L;
155 extern __sfr __at (TMR1H_ADDR) TMR1H;
156 extern __sfr __at (T1CON_ADDR) T1CON;
157 extern __sfr __at (TMR2_ADDR) TMR2;
158 extern __sfr __at (T2CON_ADDR) T2CON;
159 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
160 extern __sfr __at (SSPCON_ADDR) SSPCON;
161 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
162 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
163 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
164 extern __sfr __at (RCSTA_ADDR) RCSTA;
165 extern __sfr __at (TXREG_ADDR) TXREG;
166 extern __sfr __at (RCREG_ADDR) RCREG;
167 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
168 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
169 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
170 extern __sfr __at (ADRESH_ADDR) ADRESH;
171 extern __sfr __at (ADCON0_ADDR) ADCON0;
173 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
174 extern __sfr __at (TRISA_ADDR) TRISA;
175 extern __sfr __at (TRISB_ADDR) TRISB;
176 extern __sfr __at (TRISC_ADDR) TRISC;
177 extern __sfr __at (TRISD_ADDR) TRISD;
178 extern __sfr __at (TRISE_ADDR) TRISE;
179 extern __sfr __at (PIE1_ADDR) PIE1;
180 extern __sfr __at (PIE2_ADDR) PIE2;
181 extern __sfr __at (PCON_ADDR) PCON;
182 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
183 extern __sfr __at (PR2_ADDR) PR2;
184 extern __sfr __at (SSPADD_ADDR) SSPADD;
185 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
186 extern __sfr __at (TXSTA_ADDR) TXSTA;
187 extern __sfr __at (SPBRG_ADDR) SPBRG;
188 extern __sfr __at (ADRESL_ADDR) ADRESL;
189 extern __sfr __at (ADCON1_ADDR) ADCON1;
191 extern __sfr __at (EEDATA_ADDR) EEDATA;
192 extern __sfr __at (EEADR_ADDR) EEADR;
193 extern __sfr __at (EEDATH_ADDR) EEDATH;
194 extern __sfr __at (EEADRH_ADDR) EEADRH;
196 extern __sfr __at (EECON1_ADDR) EECON1;
197 extern __sfr __at (EECON2_ADDR) EECON2;
199 //----- STATUS Bits --------------------------------------------------------
202 //----- INTCON Bits --------------------------------------------------------
205 //----- PIR1 Bits ----------------------------------------------------------
208 //----- PIR2 Bits ----------------------------------------------------------
211 //----- T1CON Bits ---------------------------------------------------------
214 //----- T2CON Bits ---------------------------------------------------------
217 //----- SSPCON Bits --------------------------------------------------------
220 //----- CCP1CON Bits -------------------------------------------------------
223 //----- RCSTA Bits ---------------------------------------------------------
226 //----- CCP2CON Bits -------------------------------------------------------
229 //----- ADCON0 Bits --------------------------------------------------------
232 //----- OPTION Bits -----------------------------------------------------
235 //----- TRISE Bits ---------------------------------------------------------
238 //----- PIE1 Bits ----------------------------------------------------------
241 //----- PIE2 Bits ----------------------------------------------------------
244 //----- PCON Bits ----------------------------------------------------------
247 //----- SSPCON2 Bits --------------------------------------------------------
250 //----- SSPSTAT Bits -------------------------------------------------------
253 //----- TXSTA Bits ---------------------------------------------------------
256 //----- ADCON1 Bits --------------------------------------------------------
259 //----- EECON1 Bits --------------------------------------------------------
262 //==========================================================================
266 //==========================================================================
269 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
270 // __BADRAM H'105', H'107'-H'109'
271 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
273 //==========================================================================
275 // Configuration Bits
277 //==========================================================================
279 #define _CP_ALL 0x0FCF
280 #define _CP_HALF 0x1FDF
281 #define _CP_UPPER_256 0x2FEF
282 #define _CP_OFF 0x3FFF
283 #define _DEBUG_ON 0x37FF
284 #define _DEBUG_OFF 0x3FFF
285 #define _WRT_ENABLE_ON 0x3FFF
286 #define _WRT_ENABLE_OFF 0x3DFF
287 #define _CPD_ON 0x3EFF
288 #define _CPD_OFF 0x3FFF
289 #define _LVP_ON 0x3FFF
290 #define _LVP_OFF 0x3F7F
291 #define _BODEN_ON 0x3FFF
292 #define _BODEN_OFF 0x3FBF
293 #define _PWRTE_OFF 0x3FFF
294 #define _PWRTE_ON 0x3FF7
295 #define _WDT_ON 0x3FFF
296 #define _WDT_OFF 0x3FFB
297 #define _LP_OSC 0x3FFC
298 #define _XT_OSC 0x3FFD
299 #define _HS_OSC 0x3FFE
300 #define _RC_OSC 0x3FFF
304 // ----- ADCON0 bits --------------------
307 unsigned char ADON:1;
310 unsigned char CHS0:1;
311 unsigned char CHS1:1;
312 unsigned char CHS2:1;
313 unsigned char ADCS0:1;
314 unsigned char ADCS1:1;
319 unsigned char NOT_DONE:1;
329 unsigned char GO_DONE:1;
337 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
339 #define ADON ADCON0_bits.ADON
340 #define GO ADCON0_bits.GO
341 #define NOT_DONE ADCON0_bits.NOT_DONE
342 #define GO_DONE ADCON0_bits.GO_DONE
343 #define CHS0 ADCON0_bits.CHS0
344 #define CHS1 ADCON0_bits.CHS1
345 #define CHS2 ADCON0_bits.CHS2
346 #define ADCS0 ADCON0_bits.ADCS0
347 #define ADCS1 ADCON0_bits.ADCS1
349 // ----- ADCON1 bits --------------------
352 unsigned char PCFG0:1;
353 unsigned char PCFG1:1;
354 unsigned char PCFG2:1;
355 unsigned char PCFG3:1;
359 unsigned char ADFM:1;
362 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
364 #define PCFG0 ADCON1_bits.PCFG0
365 #define PCFG1 ADCON1_bits.PCFG1
366 #define PCFG2 ADCON1_bits.PCFG2
367 #define PCFG3 ADCON1_bits.PCFG3
368 #define ADFM ADCON1_bits.ADFM
370 // ----- CCP1CON bits --------------------
373 unsigned char CCP1M0:1;
374 unsigned char CCP1M1:1;
375 unsigned char CCP1M2:1;
376 unsigned char CCP1M3:1;
377 unsigned char CCP1Y:1;
378 unsigned char CCP1X:1;
383 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
385 #define CCP1M0 CCP1CON_bits.CCP1M0
386 #define CCP1M1 CCP1CON_bits.CCP1M1
387 #define CCP1M2 CCP1CON_bits.CCP1M2
388 #define CCP1M3 CCP1CON_bits.CCP1M3
389 #define CCP1Y CCP1CON_bits.CCP1Y
390 #define CCP1X CCP1CON_bits.CCP1X
392 // ----- CCP2CON bits --------------------
395 unsigned char CCP2M0:1;
396 unsigned char CCP2M1:1;
397 unsigned char CCP2M2:1;
398 unsigned char CCP2M3:1;
399 unsigned char CCP2Y:1;
400 unsigned char CCP2X:1;
405 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
407 #define CCP2M0 CCP2CON_bits.CCP2M0
408 #define CCP2M1 CCP2CON_bits.CCP2M1
409 #define CCP2M2 CCP2CON_bits.CCP2M2
410 #define CCP2M3 CCP2CON_bits.CCP2M3
411 #define CCP2Y CCP2CON_bits.CCP2Y
412 #define CCP2X CCP2CON_bits.CCP2X
414 // ----- EECON1 bits --------------------
419 unsigned char WREN:1;
420 unsigned char WRERR:1;
424 unsigned char EEPGD:1;
427 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
429 #define RD EECON1_bits.RD
430 #define WR EECON1_bits.WR
431 #define WREN EECON1_bits.WREN
432 #define WRERR EECON1_bits.WRERR
433 #define EEPGD EECON1_bits.EEPGD
435 // ----- INTCON bits --------------------
438 unsigned char RBIF:1;
439 unsigned char INTF:1;
440 unsigned char T0IF:1;
441 unsigned char RBIE:1;
442 unsigned char INTE:1;
443 unsigned char T0IE:1;
444 unsigned char PEIE:1;
448 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
450 #define RBIF INTCON_bits.RBIF
451 #define INTF INTCON_bits.INTF
452 #define T0IF INTCON_bits.T0IF
453 #define RBIE INTCON_bits.RBIE
454 #define INTE INTCON_bits.INTE
455 #define T0IE INTCON_bits.T0IE
456 #define PEIE INTCON_bits.PEIE
457 #define GIE INTCON_bits.GIE
459 // ----- OPTION_REG bits --------------------
466 unsigned char T0SE:1;
467 unsigned char T0CS:1;
468 unsigned char INTEDG:1;
469 unsigned char NOT_RBPU:1;
471 } __OPTION_REG_bits_t;
472 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
474 #define PS0 OPTION_REG_bits.PS0
475 #define PS1 OPTION_REG_bits.PS1
476 #define PS2 OPTION_REG_bits.PS2
477 #define PSA OPTION_REG_bits.PSA
478 #define T0SE OPTION_REG_bits.T0SE
479 #define T0CS OPTION_REG_bits.T0CS
480 #define INTEDG OPTION_REG_bits.INTEDG
481 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
483 // ----- PCON bits --------------------
486 unsigned char NOT_BO:1;
487 unsigned char NOT_POR:1;
496 unsigned char NOT_BOR:1;
506 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
508 #define NOT_BO PCON_bits.NOT_BO
509 #define NOT_BOR PCON_bits.NOT_BOR
510 #define NOT_POR PCON_bits.NOT_POR
512 // ----- PIE1 bits --------------------
515 unsigned char TMR1IE:1;
516 unsigned char TMR2IE:1;
517 unsigned char CCP1IE:1;
518 unsigned char SSPIE:1;
519 unsigned char TXIE:1;
520 unsigned char RCIE:1;
521 unsigned char ADIE:1;
522 unsigned char PSPIE:1;
525 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
527 #define TMR1IE PIE1_bits.TMR1IE
528 #define TMR2IE PIE1_bits.TMR2IE
529 #define CCP1IE PIE1_bits.CCP1IE
530 #define SSPIE PIE1_bits.SSPIE
531 #define TXIE PIE1_bits.TXIE
532 #define RCIE PIE1_bits.RCIE
533 #define ADIE PIE1_bits.ADIE
534 #define PSPIE PIE1_bits.PSPIE
536 // ----- PIE2 bits --------------------
539 unsigned char CCP2IE:1;
542 unsigned char BCLIE:1;
543 unsigned char EEIE:1;
549 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
551 #define CCP2IE PIE2_bits.CCP2IE
552 #define BCLIE PIE2_bits.BCLIE
553 #define EEIE PIE2_bits.EEIE
555 // ----- PIR1 bits --------------------
558 unsigned char TMR1IF:1;
559 unsigned char TMR2IF:1;
560 unsigned char CCP1IF:1;
561 unsigned char SSPIF:1;
562 unsigned char TXIF:1;
563 unsigned char RCIF:1;
564 unsigned char ADIF:1;
565 unsigned char PSPIF:1;
568 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
570 #define TMR1IF PIR1_bits.TMR1IF
571 #define TMR2IF PIR1_bits.TMR2IF
572 #define CCP1IF PIR1_bits.CCP1IF
573 #define SSPIF PIR1_bits.SSPIF
574 #define TXIF PIR1_bits.TXIF
575 #define RCIF PIR1_bits.RCIF
576 #define ADIF PIR1_bits.ADIF
577 #define PSPIF PIR1_bits.PSPIF
579 // ----- PIR2 bits --------------------
582 unsigned char CCP2IF:1;
585 unsigned char BCLIF:1;
586 unsigned char EEIF:1;
592 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
594 #define CCP2IF PIR2_bits.CCP2IF
595 #define BCLIF PIR2_bits.BCLIF
596 #define EEIF PIR2_bits.EEIF
598 // ----- RCSTA bits --------------------
601 unsigned char RX9D:1;
602 unsigned char OERR:1;
603 unsigned char FERR:1;
604 unsigned char ADDEN:1;
605 unsigned char CREN:1;
606 unsigned char SREN:1;
608 unsigned char SPEN:1;
611 unsigned char RCD8:1;
627 unsigned char NOT_RC8:1;
637 unsigned char RC8_9:1;
641 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
643 #define RX9D RCSTA_bits.RX9D
644 #define RCD8 RCSTA_bits.RCD8
645 #define OERR RCSTA_bits.OERR
646 #define FERR RCSTA_bits.FERR
647 #define ADDEN RCSTA_bits.ADDEN
648 #define CREN RCSTA_bits.CREN
649 #define SREN RCSTA_bits.SREN
650 #define RX9 RCSTA_bits.RX9
651 #define RC9 RCSTA_bits.RC9
652 #define NOT_RC8 RCSTA_bits.NOT_RC8
653 #define RC8_9 RCSTA_bits.RC8_9
654 #define SPEN RCSTA_bits.SPEN
656 // ----- SSPCON bits --------------------
659 unsigned char SSPM0:1;
660 unsigned char SSPM1:1;
661 unsigned char SSPM2:1;
662 unsigned char SSPM3:1;
664 unsigned char SSPEN:1;
665 unsigned char SSPOV:1;
666 unsigned char WCOL:1;
669 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
671 #define SSPM0 SSPCON_bits.SSPM0
672 #define SSPM1 SSPCON_bits.SSPM1
673 #define SSPM2 SSPCON_bits.SSPM2
674 #define SSPM3 SSPCON_bits.SSPM3
675 #define CKP SSPCON_bits.CKP
676 #define SSPEN SSPCON_bits.SSPEN
677 #define SSPOV SSPCON_bits.SSPOV
678 #define WCOL SSPCON_bits.WCOL
680 // ----- SSPCON2 bits --------------------
684 unsigned char RSEN:1;
686 unsigned char RCEN:1;
687 unsigned char ACKEN:1;
688 unsigned char ACKDT:1;
689 unsigned char ACKSTAT:1;
690 unsigned char GCEN:1;
693 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
695 #define SEN SSPCON2_bits.SEN
696 #define RSEN SSPCON2_bits.RSEN
697 #define PEN SSPCON2_bits.PEN
698 #define RCEN SSPCON2_bits.RCEN
699 #define ACKEN SSPCON2_bits.ACKEN
700 #define ACKDT SSPCON2_bits.ACKDT
701 #define ACKSTAT SSPCON2_bits.ACKSTAT
702 #define GCEN SSPCON2_bits.GCEN
704 // ----- SSPSTAT bits --------------------
719 unsigned char I2C_READ:1;
720 unsigned char I2C_START:1;
721 unsigned char I2C_STOP:1;
722 unsigned char I2C_DATA:1;
729 unsigned char NOT_W:1;
732 unsigned char NOT_A:1;
739 unsigned char NOT_WRITE:1;
742 unsigned char NOT_ADDRESS:1;
759 unsigned char READ_WRITE:1;
762 unsigned char DATA_ADDRESS:1;
767 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
769 #define BF SSPSTAT_bits.BF
770 #define UA SSPSTAT_bits.UA
771 #define R SSPSTAT_bits.R
772 #define I2C_READ SSPSTAT_bits.I2C_READ
773 #define NOT_W SSPSTAT_bits.NOT_W
774 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
775 #define R_W SSPSTAT_bits.R_W
776 #define READ_WRITE SSPSTAT_bits.READ_WRITE
777 #define S SSPSTAT_bits.S
778 #define I2C_START SSPSTAT_bits.I2C_START
779 #define P SSPSTAT_bits.P
780 #define I2C_STOP SSPSTAT_bits.I2C_STOP
781 #define D SSPSTAT_bits.D
782 #define I2C_DATA SSPSTAT_bits.I2C_DATA
783 #define NOT_A SSPSTAT_bits.NOT_A
784 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
785 #define D_A SSPSTAT_bits.D_A
786 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
787 #define CKE SSPSTAT_bits.CKE
788 #define SMP SSPSTAT_bits.SMP
790 // ----- STATUS bits --------------------
796 unsigned char NOT_PD:1;
797 unsigned char NOT_TO:1;
803 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
805 #define C STATUS_bits.C
806 #define DC STATUS_bits.DC
807 #define Z STATUS_bits.Z
808 #define NOT_PD STATUS_bits.NOT_PD
809 #define NOT_TO STATUS_bits.NOT_TO
810 #define RP0 STATUS_bits.RP0
811 #define RP1 STATUS_bits.RP1
812 #define IRP STATUS_bits.IRP
814 // ----- T1CON bits --------------------
817 unsigned char TMR1ON:1;
818 unsigned char TMR1CS:1;
819 unsigned char NOT_T1SYNC:1;
820 unsigned char T1OSCEN:1;
821 unsigned char T1CKPS0:1;
822 unsigned char T1CKPS1:1;
829 unsigned char T1INSYNC:1;
839 unsigned char T1SYNC:1;
847 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
849 #define TMR1ON T1CON_bits.TMR1ON
850 #define TMR1CS T1CON_bits.TMR1CS
851 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
852 #define T1INSYNC T1CON_bits.T1INSYNC
853 #define T1SYNC T1CON_bits.T1SYNC
854 #define T1OSCEN T1CON_bits.T1OSCEN
855 #define T1CKPS0 T1CON_bits.T1CKPS0
856 #define T1CKPS1 T1CON_bits.T1CKPS1
858 // ----- T2CON bits --------------------
861 unsigned char T2CKPS0:1;
862 unsigned char T2CKPS1:1;
863 unsigned char TMR2ON:1;
864 unsigned char TOUTPS0:1;
865 unsigned char TOUTPS1:1;
866 unsigned char TOUTPS2:1;
867 unsigned char TOUTPS3:1;
871 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
873 #define T2CKPS0 T2CON_bits.T2CKPS0
874 #define T2CKPS1 T2CON_bits.T2CKPS1
875 #define TMR2ON T2CON_bits.TMR2ON
876 #define TOUTPS0 T2CON_bits.TOUTPS0
877 #define TOUTPS1 T2CON_bits.TOUTPS1
878 #define TOUTPS2 T2CON_bits.TOUTPS2
879 #define TOUTPS3 T2CON_bits.TOUTPS3
881 // ----- TRISE bits --------------------
884 unsigned char TRISE0:1;
885 unsigned char TRISE1:1;
886 unsigned char TRISE2:1;
888 unsigned char PSPMODE:1;
889 unsigned char IBOV:1;
894 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
896 #define TRISE0 TRISE_bits.TRISE0
897 #define TRISE1 TRISE_bits.TRISE1
898 #define TRISE2 TRISE_bits.TRISE2
899 #define PSPMODE TRISE_bits.PSPMODE
900 #define IBOV TRISE_bits.IBOV
901 #define OBF TRISE_bits.OBF
902 #define IBF TRISE_bits.IBF
904 // ----- TXSTA bits --------------------
907 unsigned char TX9D:1;
908 unsigned char TRMT:1;
909 unsigned char BRGH:1;
911 unsigned char SYNC:1;
912 unsigned char TXEN:1;
914 unsigned char CSRC:1;
917 unsigned char TXD8:1;
923 unsigned char NOT_TX8:1;
933 unsigned char TX8_9:1;
937 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
939 #define TX9D TXSTA_bits.TX9D
940 #define TXD8 TXSTA_bits.TXD8
941 #define TRMT TXSTA_bits.TRMT
942 #define BRGH TXSTA_bits.BRGH
943 #define SYNC TXSTA_bits.SYNC
944 #define TXEN TXSTA_bits.TXEN
945 #define TX9 TXSTA_bits.TX9
946 #define NOT_TX8 TXSTA_bits.NOT_TX8
947 #define TX8_9 TXSTA_bits.TX8_9
948 #define CSRC TXSTA_bits.CSRC