2 // Register Declarations for Microchip 16F877 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define ADRESL_ADDR 0x009E
76 #define ADCON1_ADDR 0x009F
77 #define EEDATA_ADDR 0x010C
78 #define EEADR_ADDR 0x010D
79 #define EEDATH_ADDR 0x010E
80 #define EEADRH_ADDR 0x010F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
85 // Memory organization.
91 // P16F877.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
94 // This header file defines configurations, registers, and other useful bits of
95 // information for the PIC16F877 microcontroller. These names are taken to match
96 // the data sheets as closely as possible.
98 // Note that the processor must be selected before this file is
99 // included. The processor may be selected the following ways:
101 // 1. Command line switch:
102 // C:\ MPASM MYFILE.ASM /PIC16F877
103 // 2. LIST directive in the source file
105 // 3. Processor Type entry in the MPASM full-screen interface
107 //==========================================================================
111 //==========================================================================
115 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
116 // to match datasheet (DS30292B)
117 //1.00 08/07/98 Initial Release
119 //==========================================================================
123 //==========================================================================
126 // MESSG "Processor-header file mismatch. Verify selected processor."
129 //==========================================================================
131 // Register Definitions
133 //==========================================================================
138 //----- Register Files------------------------------------------------------
140 extern __sfr __at (INDF_ADDR) INDF;
141 extern __sfr __at (TMR0_ADDR) TMR0;
142 extern __sfr __at (PCL_ADDR) PCL;
143 extern __sfr __at (STATUS_ADDR) STATUS;
144 extern __sfr __at (FSR_ADDR) FSR;
145 extern __sfr __at (PORTA_ADDR) PORTA;
146 extern __sfr __at (PORTB_ADDR) PORTB;
147 extern __sfr __at (PORTC_ADDR) PORTC;
148 extern __sfr __at (PORTD_ADDR) PORTD;
149 extern __sfr __at (PORTE_ADDR) PORTE;
150 extern __sfr __at (PCLATH_ADDR) PCLATH;
151 extern __sfr __at (INTCON_ADDR) INTCON;
152 extern __sfr __at (PIR1_ADDR) PIR1;
153 extern __sfr __at (PIR2_ADDR) PIR2;
154 extern __sfr __at (TMR1L_ADDR) TMR1L;
155 extern __sfr __at (TMR1H_ADDR) TMR1H;
156 extern __sfr __at (T1CON_ADDR) T1CON;
157 extern __sfr __at (TMR2_ADDR) TMR2;
158 extern __sfr __at (T2CON_ADDR) T2CON;
159 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
160 extern __sfr __at (SSPCON_ADDR) SSPCON;
161 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
162 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
163 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
164 extern __sfr __at (RCSTA_ADDR) RCSTA;
165 extern __sfr __at (TXREG_ADDR) TXREG;
166 extern __sfr __at (RCREG_ADDR) RCREG;
167 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
168 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
169 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
170 extern __sfr __at (ADRESH_ADDR) ADRESH;
171 extern __sfr __at (ADCON0_ADDR) ADCON0;
173 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
174 extern __sfr __at (TRISA_ADDR) TRISA;
175 extern __sfr __at (TRISB_ADDR) TRISB;
176 extern __sfr __at (TRISC_ADDR) TRISC;
177 extern __sfr __at (TRISD_ADDR) TRISD;
178 extern __sfr __at (TRISE_ADDR) TRISE;
179 extern __sfr __at (PIE1_ADDR) PIE1;
180 extern __sfr __at (PIE2_ADDR) PIE2;
181 extern __sfr __at (PCON_ADDR) PCON;
182 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
183 extern __sfr __at (PR2_ADDR) PR2;
184 extern __sfr __at (SSPADD_ADDR) SSPADD;
185 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
186 extern __sfr __at (TXSTA_ADDR) TXSTA;
187 extern __sfr __at (SPBRG_ADDR) SPBRG;
188 extern __sfr __at (ADRESL_ADDR) ADRESL;
189 extern __sfr __at (ADCON1_ADDR) ADCON1;
191 extern __sfr __at (EEDATA_ADDR) EEDATA;
192 extern __sfr __at (EEADR_ADDR) EEADR;
193 extern __sfr __at (EEDATH_ADDR) EEDATH;
194 extern __sfr __at (EEADRH_ADDR) EEADRH;
196 extern __sfr __at (EECON1_ADDR) EECON1;
197 extern __sfr __at (EECON2_ADDR) EECON2;
199 //----- STATUS Bits --------------------------------------------------------
202 //----- INTCON Bits --------------------------------------------------------
205 //----- PIR1 Bits ----------------------------------------------------------
208 //----- PIR2 Bits ----------------------------------------------------------
211 //----- T1CON Bits ---------------------------------------------------------
214 //----- T2CON Bits ---------------------------------------------------------
217 //----- SSPCON Bits --------------------------------------------------------
220 //----- CCP1CON Bits -------------------------------------------------------
223 //----- RCSTA Bits ---------------------------------------------------------
226 //----- CCP2CON Bits -------------------------------------------------------
229 //----- ADCON0 Bits --------------------------------------------------------
232 //----- OPTION_REG Bits -----------------------------------------------------
235 //----- TRISE Bits ---------------------------------------------------------
238 //----- PIE1 Bits ----------------------------------------------------------
241 //----- PIE2 Bits ----------------------------------------------------------
244 //----- PCON Bits ----------------------------------------------------------
247 //----- SSPCON2 Bits --------------------------------------------------------
250 //----- SSPSTAT Bits -------------------------------------------------------
253 //----- TXSTA Bits ---------------------------------------------------------
256 //----- ADCON1 Bits --------------------------------------------------------
259 //----- EECON1 Bits --------------------------------------------------------
262 //==========================================================================
266 //==========================================================================
269 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
270 // __BADRAM H'105', H'107'-H'109'
271 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
273 //==========================================================================
275 // Configuration Bits
277 //==========================================================================
279 #define _CP_ALL 0x0FCF
280 #define _CP_HALF 0x1FDF
281 #define _CP_UPPER_256 0x2FEF
282 #define _CP_OFF 0x3FFF
283 #define _DEBUG_ON 0x37FF
284 #define _DEBUG_OFF 0x3FFF
285 #define _WRT_ENABLE_ON 0x3FFF
286 #define _WRT_ENABLE_OFF 0x3DFF
287 #define _CPD_ON 0x3EFF
288 #define _CPD_OFF 0x3FFF
289 #define _LVP_ON 0x3FFF
290 #define _LVP_OFF 0x3F7F
291 #define _BODEN_ON 0x3FFF
292 #define _BODEN_OFF 0x3FBF
293 #define _PWRTE_OFF 0x3FFF
294 #define _PWRTE_ON 0x3FF7
295 #define _WDT_ON 0x3FFF
296 #define _WDT_OFF 0x3FFB
297 #define _LP_OSC 0x3FFC
298 #define _XT_OSC 0x3FFD
299 #define _HS_OSC 0x3FFE
300 #define _RC_OSC 0x3FFF
304 // ----- ADCON0 bits --------------------
307 unsigned char ADON:1;
310 unsigned char CHS0:1;
311 unsigned char CHS1:1;
312 unsigned char CHS2:1;
313 unsigned char ADCS0:1;
314 unsigned char ADCS1:1;
319 unsigned char NOT_DONE:1;
329 unsigned char GO_DONE:1;
337 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
339 #ifndef NO_BIT_DEFINES
340 #define ADON ADCON0_bits.ADON
341 #define GO ADCON0_bits.GO
342 #define NOT_DONE ADCON0_bits.NOT_DONE
343 #define GO_DONE ADCON0_bits.GO_DONE
344 #define CHS0 ADCON0_bits.CHS0
345 #define CHS1 ADCON0_bits.CHS1
346 #define CHS2 ADCON0_bits.CHS2
347 #define ADCS0 ADCON0_bits.ADCS0
348 #define ADCS1 ADCON0_bits.ADCS1
349 #endif /* NO_BIT_DEFINES */
351 // ----- ADCON1 bits --------------------
354 unsigned char PCFG0:1;
355 unsigned char PCFG1:1;
356 unsigned char PCFG2:1;
357 unsigned char PCFG3:1;
361 unsigned char ADFM:1;
364 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
366 #ifndef NO_BIT_DEFINES
367 #define PCFG0 ADCON1_bits.PCFG0
368 #define PCFG1 ADCON1_bits.PCFG1
369 #define PCFG2 ADCON1_bits.PCFG2
370 #define PCFG3 ADCON1_bits.PCFG3
371 #define ADFM ADCON1_bits.ADFM
372 #endif /* NO_BIT_DEFINES */
374 // ----- CCP1CON bits --------------------
377 unsigned char CCP1M0:1;
378 unsigned char CCP1M1:1;
379 unsigned char CCP1M2:1;
380 unsigned char CCP1M3:1;
381 unsigned char CCP1Y:1;
382 unsigned char CCP1X:1;
387 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
389 #ifndef NO_BIT_DEFINES
390 #define CCP1M0 CCP1CON_bits.CCP1M0
391 #define CCP1M1 CCP1CON_bits.CCP1M1
392 #define CCP1M2 CCP1CON_bits.CCP1M2
393 #define CCP1M3 CCP1CON_bits.CCP1M3
394 #define CCP1Y CCP1CON_bits.CCP1Y
395 #define CCP1X CCP1CON_bits.CCP1X
396 #endif /* NO_BIT_DEFINES */
398 // ----- CCP2CON bits --------------------
401 unsigned char CCP2M0:1;
402 unsigned char CCP2M1:1;
403 unsigned char CCP2M2:1;
404 unsigned char CCP2M3:1;
405 unsigned char CCP2Y:1;
406 unsigned char CCP2X:1;
411 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
413 #ifndef NO_BIT_DEFINES
414 #define CCP2M0 CCP2CON_bits.CCP2M0
415 #define CCP2M1 CCP2CON_bits.CCP2M1
416 #define CCP2M2 CCP2CON_bits.CCP2M2
417 #define CCP2M3 CCP2CON_bits.CCP2M3
418 #define CCP2Y CCP2CON_bits.CCP2Y
419 #define CCP2X CCP2CON_bits.CCP2X
420 #endif /* NO_BIT_DEFINES */
422 // ----- EECON1 bits --------------------
427 unsigned char WREN:1;
428 unsigned char WRERR:1;
432 unsigned char EEPGD:1;
435 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
437 #ifndef NO_BIT_DEFINES
438 #define RD EECON1_bits.RD
439 #define WR EECON1_bits.WR
440 #define WREN EECON1_bits.WREN
441 #define WRERR EECON1_bits.WRERR
442 #define EEPGD EECON1_bits.EEPGD
443 #endif /* NO_BIT_DEFINES */
445 // ----- INTCON bits --------------------
448 unsigned char RBIF:1;
449 unsigned char INTF:1;
450 unsigned char T0IF:1;
451 unsigned char RBIE:1;
452 unsigned char INTE:1;
453 unsigned char T0IE:1;
454 unsigned char PEIE:1;
458 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
460 #ifndef NO_BIT_DEFINES
461 #define RBIF INTCON_bits.RBIF
462 #define INTF INTCON_bits.INTF
463 #define T0IF INTCON_bits.T0IF
464 #define RBIE INTCON_bits.RBIE
465 #define INTE INTCON_bits.INTE
466 #define T0IE INTCON_bits.T0IE
467 #define PEIE INTCON_bits.PEIE
468 #define GIE INTCON_bits.GIE
469 #endif /* NO_BIT_DEFINES */
471 // ----- OPTION_REG bits --------------------
478 unsigned char T0SE:1;
479 unsigned char T0CS:1;
480 unsigned char INTEDG:1;
481 unsigned char NOT_RBPU:1;
483 } __OPTION_REG_bits_t;
484 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
486 #ifndef NO_BIT_DEFINES
487 #define PS0 OPTION_REG_bits.PS0
488 #define PS1 OPTION_REG_bits.PS1
489 #define PS2 OPTION_REG_bits.PS2
490 #define PSA OPTION_REG_bits.PSA
491 #define T0SE OPTION_REG_bits.T0SE
492 #define T0CS OPTION_REG_bits.T0CS
493 #define INTEDG OPTION_REG_bits.INTEDG
494 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
495 #endif /* NO_BIT_DEFINES */
497 // ----- PCON bits --------------------
500 unsigned char NOT_BO:1;
501 unsigned char NOT_POR:1;
510 unsigned char NOT_BOR:1;
520 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
522 #ifndef NO_BIT_DEFINES
523 #define NOT_BO PCON_bits.NOT_BO
524 #define NOT_BOR PCON_bits.NOT_BOR
525 #define NOT_POR PCON_bits.NOT_POR
526 #endif /* NO_BIT_DEFINES */
528 // ----- PIE1 bits --------------------
531 unsigned char TMR1IE:1;
532 unsigned char TMR2IE:1;
533 unsigned char CCP1IE:1;
534 unsigned char SSPIE:1;
535 unsigned char TXIE:1;
536 unsigned char RCIE:1;
537 unsigned char ADIE:1;
538 unsigned char PSPIE:1;
541 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
543 #ifndef NO_BIT_DEFINES
544 #define TMR1IE PIE1_bits.TMR1IE
545 #define TMR2IE PIE1_bits.TMR2IE
546 #define CCP1IE PIE1_bits.CCP1IE
547 #define SSPIE PIE1_bits.SSPIE
548 #define TXIE PIE1_bits.TXIE
549 #define RCIE PIE1_bits.RCIE
550 #define ADIE PIE1_bits.ADIE
551 #define PSPIE PIE1_bits.PSPIE
552 #endif /* NO_BIT_DEFINES */
554 // ----- PIE2 bits --------------------
557 unsigned char CCP2IE:1;
560 unsigned char BCLIE:1;
561 unsigned char EEIE:1;
567 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
569 #ifndef NO_BIT_DEFINES
570 #define CCP2IE PIE2_bits.CCP2IE
571 #define BCLIE PIE2_bits.BCLIE
572 #define EEIE PIE2_bits.EEIE
573 #endif /* NO_BIT_DEFINES */
575 // ----- PIR1 bits --------------------
578 unsigned char TMR1IF:1;
579 unsigned char TMR2IF:1;
580 unsigned char CCP1IF:1;
581 unsigned char SSPIF:1;
582 unsigned char TXIF:1;
583 unsigned char RCIF:1;
584 unsigned char ADIF:1;
585 unsigned char PSPIF:1;
588 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
590 #ifndef NO_BIT_DEFINES
591 #define TMR1IF PIR1_bits.TMR1IF
592 #define TMR2IF PIR1_bits.TMR2IF
593 #define CCP1IF PIR1_bits.CCP1IF
594 #define SSPIF PIR1_bits.SSPIF
595 #define TXIF PIR1_bits.TXIF
596 #define RCIF PIR1_bits.RCIF
597 #define ADIF PIR1_bits.ADIF
598 #define PSPIF PIR1_bits.PSPIF
599 #endif /* NO_BIT_DEFINES */
601 // ----- PIR2 bits --------------------
604 unsigned char CCP2IF:1;
607 unsigned char BCLIF:1;
608 unsigned char EEIF:1;
614 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
616 #ifndef NO_BIT_DEFINES
617 #define CCP2IF PIR2_bits.CCP2IF
618 #define BCLIF PIR2_bits.BCLIF
619 #define EEIF PIR2_bits.EEIF
620 #endif /* NO_BIT_DEFINES */
622 // ----- PORTA bits --------------------
635 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
637 #ifndef NO_BIT_DEFINES
638 #define RA0 PORTA_bits.RA0
639 #define RA1 PORTA_bits.RA1
640 #define RA2 PORTA_bits.RA2
641 #define RA3 PORTA_bits.RA3
642 #define RA4 PORTA_bits.RA4
643 #define RA5 PORTA_bits.RA5
644 #endif /* NO_BIT_DEFINES */
646 // ----- PORTB bits --------------------
659 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
661 #ifndef NO_BIT_DEFINES
662 #define RB0 PORTB_bits.RB0
663 #define RB1 PORTB_bits.RB1
664 #define RB2 PORTB_bits.RB2
665 #define RB3 PORTB_bits.RB3
666 #define RB4 PORTB_bits.RB4
667 #define RB5 PORTB_bits.RB5
668 #define RB6 PORTB_bits.RB6
669 #define RB7 PORTB_bits.RB7
670 #endif /* NO_BIT_DEFINES */
672 // ----- PORTC bits --------------------
685 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
687 #ifndef NO_BIT_DEFINES
688 #define RC0 PORTC_bits.RC0
689 #define RC1 PORTC_bits.RC1
690 #define RC2 PORTC_bits.RC2
691 #define RC3 PORTC_bits.RC3
692 #define RC4 PORTC_bits.RC4
693 #define RC5 PORTC_bits.RC5
694 #define RC6 PORTC_bits.RC6
695 #define RC7 PORTC_bits.RC7
696 #endif /* NO_BIT_DEFINES */
698 // ----- PORTD bits --------------------
711 extern volatile __PORTD_bits_t __at(PORTD_ADDR) PORTD_bits;
713 #ifndef NO_BIT_DEFINES
714 #define RD0 PORTD_bits.RD0
715 #define RD1 PORTD_bits.RD1
716 #define RD2 PORTD_bits.RD2
717 #define RD3 PORTD_bits.RD3
718 #define RD4 PORTD_bits.RD4
719 #define RD5 PORTD_bits.RD5
720 #define RD6 PORTD_bits.RD6
721 #define RD7 PORTD_bits.RD7
722 #endif /* NO_BIT_DEFINES */
724 // ----- PORTE bits --------------------
737 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
739 #ifndef NO_BIT_DEFINES
740 #define RE0 PORTE_bits.RE0
741 #define RE1 PORTE_bits.RE1
742 #define RE2 PORTE_bits.RE2
743 #endif /* NO_BIT_DEFINES */
745 // ----- RCSTA bits --------------------
748 unsigned char RX9D:1;
749 unsigned char OERR:1;
750 unsigned char FERR:1;
751 unsigned char ADDEN:1;
752 unsigned char CREN:1;
753 unsigned char SREN:1;
755 unsigned char SPEN:1;
758 unsigned char RCD8:1;
774 unsigned char NOT_RC8:1;
784 unsigned char RC8_9:1;
788 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
790 #ifndef NO_BIT_DEFINES
791 #define RX9D RCSTA_bits.RX9D
792 #define RCD8 RCSTA_bits.RCD8
793 #define OERR RCSTA_bits.OERR
794 #define FERR RCSTA_bits.FERR
795 #define ADDEN RCSTA_bits.ADDEN
796 #define CREN RCSTA_bits.CREN
797 #define SREN RCSTA_bits.SREN
798 #define RX9 RCSTA_bits.RX9
799 #define RC9 RCSTA_bits.RC9
800 #define NOT_RC8 RCSTA_bits.NOT_RC8
801 #define RC8_9 RCSTA_bits.RC8_9
802 #define SPEN RCSTA_bits.SPEN
803 #endif /* NO_BIT_DEFINES */
805 // ----- SSPCON bits --------------------
808 unsigned char SSPM0:1;
809 unsigned char SSPM1:1;
810 unsigned char SSPM2:1;
811 unsigned char SSPM3:1;
813 unsigned char SSPEN:1;
814 unsigned char SSPOV:1;
815 unsigned char WCOL:1;
818 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
820 #ifndef NO_BIT_DEFINES
821 #define SSPM0 SSPCON_bits.SSPM0
822 #define SSPM1 SSPCON_bits.SSPM1
823 #define SSPM2 SSPCON_bits.SSPM2
824 #define SSPM3 SSPCON_bits.SSPM3
825 #define CKP SSPCON_bits.CKP
826 #define SSPEN SSPCON_bits.SSPEN
827 #define SSPOV SSPCON_bits.SSPOV
828 #define WCOL SSPCON_bits.WCOL
829 #endif /* NO_BIT_DEFINES */
831 // ----- SSPCON2 bits --------------------
835 unsigned char RSEN:1;
837 unsigned char RCEN:1;
838 unsigned char ACKEN:1;
839 unsigned char ACKDT:1;
840 unsigned char ACKSTAT:1;
841 unsigned char GCEN:1;
844 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
846 #ifndef NO_BIT_DEFINES
847 #define SEN SSPCON2_bits.SEN
848 #define RSEN SSPCON2_bits.RSEN
849 #define PEN SSPCON2_bits.PEN
850 #define RCEN SSPCON2_bits.RCEN
851 #define ACKEN SSPCON2_bits.ACKEN
852 #define ACKDT SSPCON2_bits.ACKDT
853 #define ACKSTAT SSPCON2_bits.ACKSTAT
854 #define GCEN SSPCON2_bits.GCEN
855 #endif /* NO_BIT_DEFINES */
857 // ----- SSPSTAT bits --------------------
872 unsigned char I2C_READ:1;
873 unsigned char I2C_START:1;
874 unsigned char I2C_STOP:1;
875 unsigned char I2C_DATA:1;
882 unsigned char NOT_W:1;
885 unsigned char NOT_A:1;
892 unsigned char NOT_WRITE:1;
895 unsigned char NOT_ADDRESS:1;
912 unsigned char READ_WRITE:1;
915 unsigned char DATA_ADDRESS:1;
920 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
922 #ifndef NO_BIT_DEFINES
923 #define BF SSPSTAT_bits.BF
924 #define UA SSPSTAT_bits.UA
925 #define R SSPSTAT_bits.R
926 #define I2C_READ SSPSTAT_bits.I2C_READ
927 #define NOT_W SSPSTAT_bits.NOT_W
928 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
929 #define R_W SSPSTAT_bits.R_W
930 #define READ_WRITE SSPSTAT_bits.READ_WRITE
931 #define S SSPSTAT_bits.S
932 #define I2C_START SSPSTAT_bits.I2C_START
933 #define P SSPSTAT_bits.P
934 #define I2C_STOP SSPSTAT_bits.I2C_STOP
935 #define D SSPSTAT_bits.D
936 #define I2C_DATA SSPSTAT_bits.I2C_DATA
937 #define NOT_A SSPSTAT_bits.NOT_A
938 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
939 #define D_A SSPSTAT_bits.D_A
940 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
941 #define CKE SSPSTAT_bits.CKE
942 #define SMP SSPSTAT_bits.SMP
943 #endif /* NO_BIT_DEFINES */
945 // ----- STATUS bits --------------------
951 unsigned char NOT_PD:1;
952 unsigned char NOT_TO:1;
958 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
960 #ifndef NO_BIT_DEFINES
961 #define C STATUS_bits.C
962 #define DC STATUS_bits.DC
963 #define Z STATUS_bits.Z
964 #define NOT_PD STATUS_bits.NOT_PD
965 #define NOT_TO STATUS_bits.NOT_TO
966 #define RP0 STATUS_bits.RP0
967 #define RP1 STATUS_bits.RP1
968 #define IRP STATUS_bits.IRP
969 #endif /* NO_BIT_DEFINES */
971 // ----- T1CON bits --------------------
974 unsigned char TMR1ON:1;
975 unsigned char TMR1CS:1;
976 unsigned char NOT_T1SYNC:1;
977 unsigned char T1OSCEN:1;
978 unsigned char T1CKPS0:1;
979 unsigned char T1CKPS1:1;
986 unsigned char T1INSYNC:1;
996 unsigned char T1SYNC:1;
1004 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1006 #ifndef NO_BIT_DEFINES
1007 #define TMR1ON T1CON_bits.TMR1ON
1008 #define TMR1CS T1CON_bits.TMR1CS
1009 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1010 #define T1INSYNC T1CON_bits.T1INSYNC
1011 #define T1SYNC T1CON_bits.T1SYNC
1012 #define T1OSCEN T1CON_bits.T1OSCEN
1013 #define T1CKPS0 T1CON_bits.T1CKPS0
1014 #define T1CKPS1 T1CON_bits.T1CKPS1
1015 #endif /* NO_BIT_DEFINES */
1017 // ----- T2CON bits --------------------
1020 unsigned char T2CKPS0:1;
1021 unsigned char T2CKPS1:1;
1022 unsigned char TMR2ON:1;
1023 unsigned char TOUTPS0:1;
1024 unsigned char TOUTPS1:1;
1025 unsigned char TOUTPS2:1;
1026 unsigned char TOUTPS3:1;
1030 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1032 #ifndef NO_BIT_DEFINES
1033 #define T2CKPS0 T2CON_bits.T2CKPS0
1034 #define T2CKPS1 T2CON_bits.T2CKPS1
1035 #define TMR2ON T2CON_bits.TMR2ON
1036 #define TOUTPS0 T2CON_bits.TOUTPS0
1037 #define TOUTPS1 T2CON_bits.TOUTPS1
1038 #define TOUTPS2 T2CON_bits.TOUTPS2
1039 #define TOUTPS3 T2CON_bits.TOUTPS3
1040 #endif /* NO_BIT_DEFINES */
1042 // ----- TRISA bits --------------------
1045 unsigned char TRISA0:1;
1046 unsigned char TRISA1:1;
1047 unsigned char TRISA2:1;
1048 unsigned char TRISA3:1;
1049 unsigned char TRISA4:1;
1050 unsigned char TRISA5:1;
1055 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1057 #ifndef NO_BIT_DEFINES
1058 #define TRISA0 TRISA_bits.TRISA0
1059 #define TRISA1 TRISA_bits.TRISA1
1060 #define TRISA2 TRISA_bits.TRISA2
1061 #define TRISA3 TRISA_bits.TRISA3
1062 #define TRISA4 TRISA_bits.TRISA4
1063 #define TRISA5 TRISA_bits.TRISA5
1064 #endif /* NO_BIT_DEFINES */
1066 // ----- TRISB bits --------------------
1069 unsigned char TRISB0:1;
1070 unsigned char TRISB1:1;
1071 unsigned char TRISB2:1;
1072 unsigned char TRISB3:1;
1073 unsigned char TRISB4:1;
1074 unsigned char TRISB5:1;
1075 unsigned char TRISB6:1;
1076 unsigned char TRISB7:1;
1079 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1081 #ifndef NO_BIT_DEFINES
1082 #define TRISB0 TRISB_bits.TRISB0
1083 #define TRISB1 TRISB_bits.TRISB1
1084 #define TRISB2 TRISB_bits.TRISB2
1085 #define TRISB3 TRISB_bits.TRISB3
1086 #define TRISB4 TRISB_bits.TRISB4
1087 #define TRISB5 TRISB_bits.TRISB5
1088 #define TRISB6 TRISB_bits.TRISB6
1089 #define TRISB7 TRISB_bits.TRISB7
1090 #endif /* NO_BIT_DEFINES */
1092 // ----- TRISC bits --------------------
1095 unsigned char TRISC0:1;
1096 unsigned char TRISC1:1;
1097 unsigned char TRISC2:1;
1098 unsigned char TRISC3:1;
1099 unsigned char TRISC4:1;
1100 unsigned char TRISC5:1;
1101 unsigned char TRISC6:1;
1102 unsigned char TRISC7:1;
1105 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1107 #ifndef NO_BIT_DEFINES
1108 #define TRISC0 TRISC_bits.TRISC0
1109 #define TRISC1 TRISC_bits.TRISC1
1110 #define TRISC2 TRISC_bits.TRISC2
1111 #define TRISC3 TRISC_bits.TRISC3
1112 #define TRISC4 TRISC_bits.TRISC4
1113 #define TRISC5 TRISC_bits.TRISC5
1114 #define TRISC6 TRISC_bits.TRISC6
1115 #define TRISC7 TRISC_bits.TRISC7
1116 #endif /* NO_BIT_DEFINES */
1118 // ----- TRISD bits --------------------
1121 unsigned char TRISD0:1;
1122 unsigned char TRISD1:1;
1123 unsigned char TRISD2:1;
1124 unsigned char TRISD3:1;
1125 unsigned char TRISD4:1;
1126 unsigned char TRISD5:1;
1127 unsigned char TRISD6:1;
1128 unsigned char TRISD7:1;
1131 extern volatile __TRISD_bits_t __at(TRISD_ADDR) TRISD_bits;
1133 #ifndef NO_BIT_DEFINES
1134 #define TRISD0 TRISD_bits.TRISD0
1135 #define TRISD1 TRISD_bits.TRISD1
1136 #define TRISD2 TRISD_bits.TRISD2
1137 #define TRISD3 TRISD_bits.TRISD3
1138 #define TRISD4 TRISD_bits.TRISD4
1139 #define TRISD5 TRISD_bits.TRISD5
1140 #define TRISD6 TRISD_bits.TRISD6
1141 #define TRISD7 TRISD_bits.TRISD7
1142 #endif /* NO_BIT_DEFINES */
1144 // ----- TRISE bits --------------------
1147 unsigned char TRISE0:1;
1148 unsigned char TRISE1:1;
1149 unsigned char TRISE2:1;
1151 unsigned char PSPMODE:1;
1152 unsigned char IBOV:1;
1153 unsigned char OBF:1;
1154 unsigned char IBF:1;
1157 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1159 #ifndef NO_BIT_DEFINES
1160 #define TRISE0 TRISE_bits.TRISE0
1161 #define TRISE1 TRISE_bits.TRISE1
1162 #define TRISE2 TRISE_bits.TRISE2
1163 #define PSPMODE TRISE_bits.PSPMODE
1164 #define IBOV TRISE_bits.IBOV
1165 #define OBF TRISE_bits.OBF
1166 #define IBF TRISE_bits.IBF
1167 #endif /* NO_BIT_DEFINES */
1169 // ----- TXSTA bits --------------------
1172 unsigned char TX9D:1;
1173 unsigned char TRMT:1;
1174 unsigned char BRGH:1;
1176 unsigned char SYNC:1;
1177 unsigned char TXEN:1;
1178 unsigned char TX9:1;
1179 unsigned char CSRC:1;
1182 unsigned char TXD8:1;
1188 unsigned char NOT_TX8:1;
1198 unsigned char TX8_9:1;
1202 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1204 #ifndef NO_BIT_DEFINES
1205 #define TX9D TXSTA_bits.TX9D
1206 #define TXD8 TXSTA_bits.TXD8
1207 #define TRMT TXSTA_bits.TRMT
1208 #define BRGH TXSTA_bits.BRGH
1209 #define SYNC TXSTA_bits.SYNC
1210 #define TXEN TXSTA_bits.TXEN
1211 #define TX9 TXSTA_bits.TX9
1212 #define NOT_TX8 TXSTA_bits.NOT_TX8
1213 #define TX8_9 TXSTA_bits.TX8_9
1214 #define CSRC TXSTA_bits.CSRC
1215 #endif /* NO_BIT_DEFINES */