2 // Register Declarations for Microchip 16F876A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define CMCON_ADDR 0x009C
72 #define CVRCON_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define EEDATA_ADDR 0x010C
76 #define EEADR_ADDR 0x010D
77 #define EEDATH_ADDR 0x010E
78 #define EEADRH_ADDR 0x010F
79 #define EECON1_ADDR 0x018C
80 #define EECON2_ADDR 0x018D
83 // Memory organization.
89 // P16F876A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
92 // This header file defines configurations, registers, and other useful bits of
93 // information for the PIC16F877A microcontroller. These names are taken to match
94 // the data sheets as closely as possible.
96 // Note that the processor must be selected before this file is
97 // included. The processor may be selected the following ways:
99 // 1. Command line switch:
100 // C:\ MPASM MYFILE.ASM /PIC16F876A
101 // 2. LIST directive in the source file
103 // 3. Processor Type entry in the MPASM full-screen interface
105 //==========================================================================
109 //==========================================================================
112 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
113 //1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
114 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc)
116 //==========================================================================
120 //==========================================================================
123 // MESSG "Processor-header file mismatch. Verify selected processor."
126 //==========================================================================
128 // Register Definitions
130 //==========================================================================
135 //----- Register Files------------------------------------------------------
137 extern __data __at (INDF_ADDR) volatile char INDF;
138 extern __sfr __at (TMR0_ADDR) TMR0;
139 extern __data __at (PCL_ADDR) volatile char PCL;
140 extern __sfr __at (STATUS_ADDR) STATUS;
141 extern __sfr __at (FSR_ADDR) FSR;
142 extern __sfr __at (PORTA_ADDR) PORTA;
143 extern __sfr __at (PORTB_ADDR) PORTB;
144 extern __sfr __at (PORTC_ADDR) PORTC;
145 extern __sfr __at (PCLATH_ADDR) PCLATH;
146 extern __sfr __at (INTCON_ADDR) INTCON;
147 extern __sfr __at (PIR1_ADDR) PIR1;
148 extern __sfr __at (PIR2_ADDR) PIR2;
149 extern __sfr __at (TMR1L_ADDR) TMR1L;
150 extern __sfr __at (TMR1H_ADDR) TMR1H;
151 extern __sfr __at (T1CON_ADDR) T1CON;
152 extern __sfr __at (TMR2_ADDR) TMR2;
153 extern __sfr __at (T2CON_ADDR) T2CON;
154 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
155 extern __sfr __at (SSPCON_ADDR) SSPCON;
156 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
157 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
158 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
159 extern __sfr __at (RCSTA_ADDR) RCSTA;
160 extern __sfr __at (TXREG_ADDR) TXREG;
161 extern __sfr __at (RCREG_ADDR) RCREG;
162 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
163 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
164 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
168 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
169 extern __sfr __at (TRISA_ADDR) TRISA;
170 extern __sfr __at (TRISB_ADDR) TRISB;
171 extern __sfr __at (TRISC_ADDR) TRISC;
172 extern __sfr __at (PIE1_ADDR) PIE1;
173 extern __sfr __at (PIE2_ADDR) PIE2;
174 extern __sfr __at (PCON_ADDR) PCON;
175 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
176 extern __sfr __at (PR2_ADDR) PR2;
177 extern __sfr __at (SSPADD_ADDR) SSPADD;
178 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
179 extern __sfr __at (TXSTA_ADDR) TXSTA;
180 extern __sfr __at (SPBRG_ADDR) SPBRG;
181 extern __sfr __at (CMCON_ADDR) CMCON;
182 extern __sfr __at (CVRCON_ADDR) CVRCON;
183 extern __sfr __at (ADRESL_ADDR) ADRESL;
184 extern __sfr __at (ADCON1_ADDR) ADCON1;
186 extern __sfr __at (EEDATA_ADDR) EEDATA;
187 extern __sfr __at (EEADR_ADDR) EEADR;
188 extern __sfr __at (EEDATH_ADDR) EEDATH;
189 extern __sfr __at (EEADRH_ADDR) EEADRH;
191 extern __sfr __at (EECON1_ADDR) EECON1;
192 extern __sfr __at (EECON2_ADDR) EECON2;
194 //----- STATUS Bits --------------------------------------------------------
197 //----- INTCON Bits --------------------------------------------------------
200 //----- PIR1 Bits ----------------------------------------------------------
203 //----- PIR2 Bits ----------------------------------------------------------
206 //----- T1CON Bits ---------------------------------------------------------
209 //----- T2CON Bits ---------------------------------------------------------
212 //----- SSPCON Bits --------------------------------------------------------
215 //----- CCP1CON Bits -------------------------------------------------------
218 //----- RCSTA Bits ---------------------------------------------------------
221 //----- CCP2CON Bits -------------------------------------------------------
224 //----- ADCON0 Bits --------------------------------------------------------
227 //----- OPTION Bits -----------------------------------------------------
230 //----- PIE1 Bits ----------------------------------------------------------
233 //----- PIE2 Bits ----------------------------------------------------------
236 //----- PCON Bits ----------------------------------------------------------
239 //----- SSPCON2 Bits --------------------------------------------------------
242 //----- SSPSTAT Bits -------------------------------------------------------
245 //----- TXSTA Bits ---------------------------------------------------------
249 //----- CMCON Bits ---------------------------------------------------------
251 //----- CVRCON Bits --------------------------------------------------------
253 //----- ADCON1 Bits --------------------------------------------------------
256 //----- EECON1 Bits --------------------------------------------------------
259 //==========================================================================
263 //==========================================================================
266 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
267 // __BADRAM H'105', H'107'-H'109'
268 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
270 //==========================================================================
272 // Configuration Bits
274 //==========================================================================
276 #define _CP_ALL 0x1FFF
277 #define _CP_OFF 0x3FFF
278 #define _DEBUG_OFF 0x3FFF
279 #define _DEBUG_ON 0x37FF
280 #define _WRT_OFF 0x3FFF // No prog memmory write protection
281 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
282 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
283 #define _WRT_HALF 0x39FF // First half memmory write protected
284 #define _CPD_OFF 0x3FFF
285 #define _CPD_ON 0x3EFF
286 #define _LVP_ON 0x3FFF
287 #define _LVP_OFF 0x3F7F
288 #define _BODEN_ON 0x3FFF
289 #define _BODEN_OFF 0x3FBF
290 #define _PWRTE_OFF 0x3FFF
291 #define _PWRTE_ON 0x3FF7
292 #define _WDT_ON 0x3FFF
293 #define _WDT_OFF 0x3FFB
294 #define _RC_OSC 0x3FFF
295 #define _HS_OSC 0x3FFE
296 #define _XT_OSC 0x3FFD
297 #define _LP_OSC 0x3FFC
301 // ----- ADCON0 bits --------------------
304 unsigned char ADON:1;
307 unsigned char CHS0:1;
308 unsigned char CHS1:1;
309 unsigned char CHS2:1;
310 unsigned char ADCS0:1;
311 unsigned char ADCS1:1;
316 unsigned char NOT_DONE:1;
326 unsigned char GO_DONE:1;
334 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
336 #define ADON ADCON0_bits.ADON
337 #define GO ADCON0_bits.GO
338 #define NOT_DONE ADCON0_bits.NOT_DONE
339 #define GO_DONE ADCON0_bits.GO_DONE
340 #define CHS0 ADCON0_bits.CHS0
341 #define CHS1 ADCON0_bits.CHS1
342 #define CHS2 ADCON0_bits.CHS2
343 #define ADCS0 ADCON0_bits.ADCS0
344 #define ADCS1 ADCON0_bits.ADCS1
346 // ----- ADCON1 bits --------------------
349 unsigned char PCFG0:1;
350 unsigned char PCFG1:1;
351 unsigned char PCFG2:1;
352 unsigned char PCFG3:1;
356 unsigned char ADFM:1;
359 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
361 #define PCFG0 ADCON1_bits.PCFG0
362 #define PCFG1 ADCON1_bits.PCFG1
363 #define PCFG2 ADCON1_bits.PCFG2
364 #define PCFG3 ADCON1_bits.PCFG3
365 #define ADFM ADCON1_bits.ADFM
367 // ----- CCP1CON bits --------------------
370 unsigned char CCP1M0:1;
371 unsigned char CCP1M1:1;
372 unsigned char CCP1M2:1;
373 unsigned char CCP1M3:1;
374 unsigned char CCP1Y:1;
375 unsigned char CCP1X:1;
380 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
382 #define CCP1M0 CCP1CON_bits.CCP1M0
383 #define CCP1M1 CCP1CON_bits.CCP1M1
384 #define CCP1M2 CCP1CON_bits.CCP1M2
385 #define CCP1M3 CCP1CON_bits.CCP1M3
386 #define CCP1Y CCP1CON_bits.CCP1Y
387 #define CCP1X CCP1CON_bits.CCP1X
389 // ----- CCP2CON bits --------------------
392 unsigned char CCP2M0:1;
393 unsigned char CCP2M1:1;
394 unsigned char CCP2M2:1;
395 unsigned char CCP2M3:1;
396 unsigned char CCP2Y:1;
397 unsigned char CCP2X:1;
402 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
404 #define CCP2M0 CCP2CON_bits.CCP2M0
405 #define CCP2M1 CCP2CON_bits.CCP2M1
406 #define CCP2M2 CCP2CON_bits.CCP2M2
407 #define CCP2M3 CCP2CON_bits.CCP2M3
408 #define CCP2Y CCP2CON_bits.CCP2Y
409 #define CCP2X CCP2CON_bits.CCP2X
411 // ----- CMCON bits --------------------
418 unsigned char C1INV:1;
419 unsigned char C2INV:1;
420 unsigned char C1OUT:1;
421 unsigned char C2OUT:1;
424 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
426 #define CM0 CMCON_bits.CM0
427 #define CM1 CMCON_bits.CM1
428 #define CM2 CMCON_bits.CM2
429 #define CIS CMCON_bits.CIS
430 #define C1INV CMCON_bits.C1INV
431 #define C2INV CMCON_bits.C2INV
432 #define C1OUT CMCON_bits.C1OUT
433 #define C2OUT CMCON_bits.C2OUT
435 // ----- CVRCON bits --------------------
438 unsigned char CVR0:1;
439 unsigned char CVR1:1;
440 unsigned char CVR2:1;
441 unsigned char CVR3:1;
443 unsigned char CVRR:1;
444 unsigned char CVROE:1;
445 unsigned char CVREN:1;
448 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
450 #define CVR0 CVRCON_bits.CVR0
451 #define CVR1 CVRCON_bits.CVR1
452 #define CVR2 CVRCON_bits.CVR2
453 #define CVR3 CVRCON_bits.CVR3
454 #define CVRR CVRCON_bits.CVRR
455 #define CVROE CVRCON_bits.CVROE
456 #define CVREN CVRCON_bits.CVREN
458 // ----- EECON1 bits --------------------
463 unsigned char WREN:1;
464 unsigned char WRERR:1;
468 unsigned char EEPGD:1;
471 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
473 #define RD EECON1_bits.RD
474 #define WR EECON1_bits.WR
475 #define WREN EECON1_bits.WREN
476 #define WRERR EECON1_bits.WRERR
477 #define EEPGD EECON1_bits.EEPGD
479 // ----- INTCON bits --------------------
482 unsigned char RBIF:1;
483 unsigned char INTF:1;
484 unsigned char T0IF:1;
485 unsigned char RBIE:1;
486 unsigned char INTE:1;
487 unsigned char T0IE:1;
488 unsigned char PEIE:1;
492 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
494 #define RBIF INTCON_bits.RBIF
495 #define INTF INTCON_bits.INTF
496 #define T0IF INTCON_bits.T0IF
497 #define RBIE INTCON_bits.RBIE
498 #define INTE INTCON_bits.INTE
499 #define T0IE INTCON_bits.T0IE
500 #define PEIE INTCON_bits.PEIE
501 #define GIE INTCON_bits.GIE
503 // ----- OPTION_REG bits --------------------
510 unsigned char T0SE:1;
511 unsigned char T0CS:1;
512 unsigned char INTEDG:1;
513 unsigned char NOT_RBPU:1;
515 } __OPTION_REG_bits_t;
516 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
518 #define PS0 OPTION_REG_bits.PS0
519 #define PS1 OPTION_REG_bits.PS1
520 #define PS2 OPTION_REG_bits.PS2
521 #define PSA OPTION_REG_bits.PSA
522 #define T0SE OPTION_REG_bits.T0SE
523 #define T0CS OPTION_REG_bits.T0CS
524 #define INTEDG OPTION_REG_bits.INTEDG
525 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
527 // ----- PCON bits --------------------
530 unsigned char NOT_BO:1;
531 unsigned char NOT_POR:1;
540 unsigned char NOT_BOR:1;
550 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
552 #define NOT_BO PCON_bits.NOT_BO
553 #define NOT_BOR PCON_bits.NOT_BOR
554 #define NOT_POR PCON_bits.NOT_POR
556 // ----- PIE1 bits --------------------
559 unsigned char TMR1IE:1;
560 unsigned char TMR2IE:1;
561 unsigned char CCP1IE:1;
562 unsigned char SSPIE:1;
563 unsigned char TXIE:1;
564 unsigned char RCIE:1;
565 unsigned char ADIE:1;
569 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
571 #define TMR1IE PIE1_bits.TMR1IE
572 #define TMR2IE PIE1_bits.TMR2IE
573 #define CCP1IE PIE1_bits.CCP1IE
574 #define SSPIE PIE1_bits.SSPIE
575 #define TXIE PIE1_bits.TXIE
576 #define RCIE PIE1_bits.RCIE
577 #define ADIE PIE1_bits.ADIE
579 // ----- PIE2 bits --------------------
582 unsigned char CCP2IE:1;
585 unsigned char BCLIE:1;
586 unsigned char EEIE:1;
588 unsigned char CMIE:1;
592 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
594 #define CCP2IE PIE2_bits.CCP2IE
595 #define BCLIE PIE2_bits.BCLIE
596 #define EEIE PIE2_bits.EEIE
597 #define CMIE PIE2_bits.CMIE
599 // ----- PIR1 bits --------------------
602 unsigned char TMR1IF:1;
603 unsigned char TMR2IF:1;
604 unsigned char CCP1IF:1;
605 unsigned char SSPIF:1;
606 unsigned char TXIF:1;
607 unsigned char RCIF:1;
608 unsigned char ADIF:1;
612 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
614 #define TMR1IF PIR1_bits.TMR1IF
615 #define TMR2IF PIR1_bits.TMR2IF
616 #define CCP1IF PIR1_bits.CCP1IF
617 #define SSPIF PIR1_bits.SSPIF
618 #define TXIF PIR1_bits.TXIF
619 #define RCIF PIR1_bits.RCIF
620 #define ADIF PIR1_bits.ADIF
622 // ----- PIR2 bits --------------------
625 unsigned char CCP2IF:1;
628 unsigned char BCLIF:1;
629 unsigned char EEIF:1;
631 unsigned char CMIF:1;
635 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
637 #define CCP2IF PIR2_bits.CCP2IF
638 #define BCLIF PIR2_bits.BCLIF
639 #define EEIF PIR2_bits.EEIF
640 #define CMIF PIR2_bits.CMIF
642 // ----- RCSTA bits --------------------
645 unsigned char RX9D:1;
646 unsigned char OERR:1;
647 unsigned char FERR:1;
648 unsigned char ADDEN:1;
649 unsigned char CREN:1;
650 unsigned char SREN:1;
652 unsigned char SPEN:1;
655 unsigned char RCD8:1;
671 unsigned char NOT_RC8:1;
681 unsigned char RC8_9:1;
685 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
687 #define RX9D RCSTA_bits.RX9D
688 #define RCD8 RCSTA_bits.RCD8
689 #define OERR RCSTA_bits.OERR
690 #define FERR RCSTA_bits.FERR
691 #define ADDEN RCSTA_bits.ADDEN
692 #define CREN RCSTA_bits.CREN
693 #define SREN RCSTA_bits.SREN
694 #define RX9 RCSTA_bits.RX9
695 #define RC9 RCSTA_bits.RC9
696 #define NOT_RC8 RCSTA_bits.NOT_RC8
697 #define RC8_9 RCSTA_bits.RC8_9
698 #define SPEN RCSTA_bits.SPEN
700 // ----- SSPCON bits --------------------
703 unsigned char SSPM0:1;
704 unsigned char SSPM1:1;
705 unsigned char SSPM2:1;
706 unsigned char SSPM3:1;
708 unsigned char SSPEN:1;
709 unsigned char SSPOV:1;
710 unsigned char WCOL:1;
713 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
715 #define SSPM0 SSPCON_bits.SSPM0
716 #define SSPM1 SSPCON_bits.SSPM1
717 #define SSPM2 SSPCON_bits.SSPM2
718 #define SSPM3 SSPCON_bits.SSPM3
719 #define CKP SSPCON_bits.CKP
720 #define SSPEN SSPCON_bits.SSPEN
721 #define SSPOV SSPCON_bits.SSPOV
722 #define WCOL SSPCON_bits.WCOL
724 // ----- SSPCON2 bits --------------------
728 unsigned char RSEN:1;
730 unsigned char RCEN:1;
731 unsigned char ACKEN:1;
732 unsigned char ACKDT:1;
733 unsigned char ACKSTAT:1;
734 unsigned char GCEN:1;
737 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
739 #define SEN SSPCON2_bits.SEN
740 #define RSEN SSPCON2_bits.RSEN
741 #define PEN SSPCON2_bits.PEN
742 #define RCEN SSPCON2_bits.RCEN
743 #define ACKEN SSPCON2_bits.ACKEN
744 #define ACKDT SSPCON2_bits.ACKDT
745 #define ACKSTAT SSPCON2_bits.ACKSTAT
746 #define GCEN SSPCON2_bits.GCEN
748 // ----- SSPSTAT bits --------------------
763 unsigned char I2C_READ:1;
764 unsigned char I2C_START:1;
765 unsigned char I2C_STOP:1;
766 unsigned char I2C_DATA:1;
773 unsigned char NOT_W:1;
776 unsigned char NOT_A:1;
783 unsigned char NOT_WRITE:1;
786 unsigned char NOT_ADDRESS:1;
803 unsigned char READ_WRITE:1;
806 unsigned char DATA_ADDRESS:1;
811 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
813 #define BF SSPSTAT_bits.BF
814 #define UA SSPSTAT_bits.UA
815 #define R SSPSTAT_bits.R
816 #define I2C_READ SSPSTAT_bits.I2C_READ
817 #define NOT_W SSPSTAT_bits.NOT_W
818 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
819 #define R_W SSPSTAT_bits.R_W
820 #define READ_WRITE SSPSTAT_bits.READ_WRITE
821 #define S SSPSTAT_bits.S
822 #define I2C_START SSPSTAT_bits.I2C_START
823 #define P SSPSTAT_bits.P
824 #define I2C_STOP SSPSTAT_bits.I2C_STOP
825 #define D SSPSTAT_bits.D
826 #define I2C_DATA SSPSTAT_bits.I2C_DATA
827 #define NOT_A SSPSTAT_bits.NOT_A
828 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
829 #define D_A SSPSTAT_bits.D_A
830 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
831 #define CKE SSPSTAT_bits.CKE
832 #define SMP SSPSTAT_bits.SMP
834 // ----- STATUS bits --------------------
840 unsigned char NOT_PD:1;
841 unsigned char NOT_TO:1;
847 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
849 #define C STATUS_bits.C
850 #define DC STATUS_bits.DC
851 #define Z STATUS_bits.Z
852 #define NOT_PD STATUS_bits.NOT_PD
853 #define NOT_TO STATUS_bits.NOT_TO
854 #define RP0 STATUS_bits.RP0
855 #define RP1 STATUS_bits.RP1
856 #define IRP STATUS_bits.IRP
858 // ----- T1CON bits --------------------
861 unsigned char TMR1ON:1;
862 unsigned char TMR1CS:1;
863 unsigned char NOT_T1SYNC:1;
864 unsigned char T1OSCEN:1;
865 unsigned char T1CKPS0:1;
866 unsigned char T1CKPS1:1;
873 unsigned char T1INSYNC:1;
883 unsigned char T1SYNC:1;
891 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
893 #define TMR1ON T1CON_bits.TMR1ON
894 #define TMR1CS T1CON_bits.TMR1CS
895 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
896 #define T1INSYNC T1CON_bits.T1INSYNC
897 #define T1SYNC T1CON_bits.T1SYNC
898 #define T1OSCEN T1CON_bits.T1OSCEN
899 #define T1CKPS0 T1CON_bits.T1CKPS0
900 #define T1CKPS1 T1CON_bits.T1CKPS1
902 // ----- T2CON bits --------------------
905 unsigned char T2CKPS0:1;
906 unsigned char T2CKPS1:1;
907 unsigned char TMR2ON:1;
908 unsigned char TOUTPS0:1;
909 unsigned char TOUTPS1:1;
910 unsigned char TOUTPS2:1;
911 unsigned char TOUTPS3:1;
915 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
917 #define T2CKPS0 T2CON_bits.T2CKPS0
918 #define T2CKPS1 T2CON_bits.T2CKPS1
919 #define TMR2ON T2CON_bits.TMR2ON
920 #define TOUTPS0 T2CON_bits.TOUTPS0
921 #define TOUTPS1 T2CON_bits.TOUTPS1
922 #define TOUTPS2 T2CON_bits.TOUTPS2
923 #define TOUTPS3 T2CON_bits.TOUTPS3
925 // ----- TXSTA bits --------------------
928 unsigned char TX9D:1;
929 unsigned char TRMT:1;
930 unsigned char BRGH:1;
932 unsigned char SYNC:1;
933 unsigned char TXEN:1;
935 unsigned char CSRC:1;
938 unsigned char TXD8:1;
944 unsigned char NOT_TX8:1;
954 unsigned char TX8_9:1;
958 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
960 #define TX9D TXSTA_bits.TX9D
961 #define TXD8 TXSTA_bits.TXD8
962 #define TRMT TXSTA_bits.TRMT
963 #define BRGH TXSTA_bits.BRGH
964 #define SYNC TXSTA_bits.SYNC
965 #define TXEN TXSTA_bits.TXEN
966 #define TX9 TXSTA_bits.TX9
967 #define NOT_TX8 TXSTA_bits.NOT_TX8
968 #define TX8_9 TXSTA_bits.TX8_9
969 #define CSRC TXSTA_bits.CSRC