2 // Register Declarations for Microchip 16F876A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define CMCON_ADDR 0x009C
72 #define CVRCON_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define EEDATA_ADDR 0x010C
76 #define EEADR_ADDR 0x010D
77 #define EEDATH_ADDR 0x010E
78 #define EEADRH_ADDR 0x010F
79 #define EECON1_ADDR 0x018C
80 #define EECON2_ADDR 0x018D
83 // Memory organization.
86 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
87 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
88 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
89 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
90 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
91 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
92 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
93 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
94 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
95 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
96 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
97 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
98 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
99 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
100 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
101 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
102 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
103 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
104 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
105 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
106 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
107 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
108 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
109 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
110 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
111 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
112 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
113 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
114 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
115 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
116 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
117 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
118 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
119 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
120 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
121 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
122 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
123 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
124 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
125 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
126 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
127 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
128 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
129 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
130 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
131 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
132 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
133 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
134 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
135 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
136 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
137 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
138 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
142 // P16F876A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
145 // This header file defines configurations, registers, and other useful bits of
146 // information for the PIC16F877A microcontroller. These names are taken to match
147 // the data sheets as closely as possible.
149 // Note that the processor must be selected before this file is
150 // included. The processor may be selected the following ways:
152 // 1. Command line switch:
153 // C:\ MPASM MYFILE.ASM /PIC16F876A
154 // 2. LIST directive in the source file
156 // 3. Processor Type entry in the MPASM full-screen interface
158 //==========================================================================
162 //==========================================================================
165 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
166 //1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
167 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc)
169 //==========================================================================
173 //==========================================================================
176 // MESSG "Processor-header file mismatch. Verify selected processor."
179 //==========================================================================
181 // Register Definitions
183 //==========================================================================
188 //----- Register Files------------------------------------------------------
190 extern data __at (INDF_ADDR) volatile char INDF;
191 extern sfr __at (TMR0_ADDR) TMR0;
192 extern data __at (PCL_ADDR) volatile char PCL;
193 extern sfr __at (STATUS_ADDR) STATUS;
194 extern sfr __at (FSR_ADDR) FSR;
195 extern sfr __at (PORTA_ADDR) PORTA;
196 extern sfr __at (PORTB_ADDR) PORTB;
197 extern sfr __at (PORTC_ADDR) PORTC;
198 extern sfr __at (PCLATH_ADDR) PCLATH;
199 extern sfr __at (INTCON_ADDR) INTCON;
200 extern sfr __at (PIR1_ADDR) PIR1;
201 extern sfr __at (PIR2_ADDR) PIR2;
202 extern sfr __at (TMR1L_ADDR) TMR1L;
203 extern sfr __at (TMR1H_ADDR) TMR1H;
204 extern sfr __at (T1CON_ADDR) T1CON;
205 extern sfr __at (TMR2_ADDR) TMR2;
206 extern sfr __at (T2CON_ADDR) T2CON;
207 extern sfr __at (SSPBUF_ADDR) SSPBUF;
208 extern sfr __at (SSPCON_ADDR) SSPCON;
209 extern sfr __at (CCPR1L_ADDR) CCPR1L;
210 extern sfr __at (CCPR1H_ADDR) CCPR1H;
211 extern sfr __at (CCP1CON_ADDR) CCP1CON;
212 extern sfr __at (RCSTA_ADDR) RCSTA;
213 extern sfr __at (TXREG_ADDR) TXREG;
214 extern sfr __at (RCREG_ADDR) RCREG;
215 extern sfr __at (CCPR2L_ADDR) CCPR2L;
216 extern sfr __at (CCPR2H_ADDR) CCPR2H;
217 extern sfr __at (CCP2CON_ADDR) CCP2CON;
218 extern sfr __at (ADRESH_ADDR) ADRESH;
219 extern sfr __at (ADCON0_ADDR) ADCON0;
221 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
222 extern sfr __at (TRISA_ADDR) TRISA;
223 extern sfr __at (TRISB_ADDR) TRISB;
224 extern sfr __at (TRISC_ADDR) TRISC;
225 extern sfr __at (PIE1_ADDR) PIE1;
226 extern sfr __at (PIE2_ADDR) PIE2;
227 extern sfr __at (PCON_ADDR) PCON;
228 extern sfr __at (SSPCON2_ADDR) SSPCON2;
229 extern sfr __at (PR2_ADDR) PR2;
230 extern sfr __at (SSPADD_ADDR) SSPADD;
231 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
232 extern sfr __at (TXSTA_ADDR) TXSTA;
233 extern sfr __at (SPBRG_ADDR) SPBRG;
234 extern sfr __at (CMCON_ADDR) CMCON;
235 extern sfr __at (CVRCON_ADDR) CVRCON;
236 extern sfr __at (ADRESL_ADDR) ADRESL;
237 extern sfr __at (ADCON1_ADDR) ADCON1;
239 extern sfr __at (EEDATA_ADDR) EEDATA;
240 extern sfr __at (EEADR_ADDR) EEADR;
241 extern sfr __at (EEDATH_ADDR) EEDATH;
242 extern sfr __at (EEADRH_ADDR) EEADRH;
244 extern sfr __at (EECON1_ADDR) EECON1;
245 extern sfr __at (EECON2_ADDR) EECON2;
247 //----- STATUS Bits --------------------------------------------------------
250 //----- INTCON Bits --------------------------------------------------------
253 //----- PIR1 Bits ----------------------------------------------------------
256 //----- PIR2 Bits ----------------------------------------------------------
259 //----- T1CON Bits ---------------------------------------------------------
262 //----- T2CON Bits ---------------------------------------------------------
265 //----- SSPCON Bits --------------------------------------------------------
268 //----- CCP1CON Bits -------------------------------------------------------
271 //----- RCSTA Bits ---------------------------------------------------------
274 //----- CCP2CON Bits -------------------------------------------------------
277 //----- ADCON0 Bits --------------------------------------------------------
280 //----- OPTION Bits -----------------------------------------------------
283 //----- PIE1 Bits ----------------------------------------------------------
286 //----- PIE2 Bits ----------------------------------------------------------
289 //----- PCON Bits ----------------------------------------------------------
292 //----- SSPCON2 Bits --------------------------------------------------------
295 //----- SSPSTAT Bits -------------------------------------------------------
298 //----- TXSTA Bits ---------------------------------------------------------
302 //----- CMCON Bits ---------------------------------------------------------
304 //----- CVRCON Bits --------------------------------------------------------
306 //----- ADCON1 Bits --------------------------------------------------------
309 //----- EECON1 Bits --------------------------------------------------------
312 //==========================================================================
316 //==========================================================================
319 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
320 // __BADRAM H'105', H'107'-H'109'
321 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
323 //==========================================================================
325 // Configuration Bits
327 //==========================================================================
329 #define _CP_ALL 0x1FFF
330 #define _CP_OFF 0x3FFF
331 #define _DEBUG_OFF 0x3FFF
332 #define _DEBUG_ON 0x37FF
333 #define _WRT_OFF 0x3FFF // No prog memmory write protection
334 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
335 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
336 #define _WRT_HALF 0x39FF // First half memmory write protected
337 #define _CPD_OFF 0x3FFF
338 #define _CPD_ON 0x3EFF
339 #define _LVP_ON 0x3FFF
340 #define _LVP_OFF 0x3F7F
341 #define _BODEN_ON 0x3FFF
342 #define _BODEN_OFF 0x3FBF
343 #define _PWRTE_OFF 0x3FFF
344 #define _PWRTE_ON 0x3FF7
345 #define _WDT_ON 0x3FFF
346 #define _WDT_OFF 0x3FFB
347 #define _RC_OSC 0x3FFF
348 #define _HS_OSC 0x3FFE
349 #define _XT_OSC 0x3FFD
350 #define _LP_OSC 0x3FFC
354 // ----- ADCON0 bits --------------------
357 unsigned char ADON:1;
360 unsigned char CHS0:1;
361 unsigned char CHS1:1;
362 unsigned char CHS2:1;
363 unsigned char ADCS0:1;
364 unsigned char ADCS1:1;
369 unsigned char NOT_DONE:1;
379 unsigned char GO_DONE:1;
387 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
389 #define ADON ADCON0_bits.ADON
390 #define GO ADCON0_bits.GO
391 #define NOT_DONE ADCON0_bits.NOT_DONE
392 #define GO_DONE ADCON0_bits.GO_DONE
393 #define CHS0 ADCON0_bits.CHS0
394 #define CHS1 ADCON0_bits.CHS1
395 #define CHS2 ADCON0_bits.CHS2
396 #define ADCS0 ADCON0_bits.ADCS0
397 #define ADCS1 ADCON0_bits.ADCS1
399 // ----- ADCON1 bits --------------------
402 unsigned char PCFG0:1;
403 unsigned char PCFG1:1;
404 unsigned char PCFG2:1;
405 unsigned char PCFG3:1;
409 unsigned char ADFM:1;
412 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
414 #define PCFG0 ADCON1_bits.PCFG0
415 #define PCFG1 ADCON1_bits.PCFG1
416 #define PCFG2 ADCON1_bits.PCFG2
417 #define PCFG3 ADCON1_bits.PCFG3
418 #define ADFM ADCON1_bits.ADFM
420 // ----- CCP1CON bits --------------------
423 unsigned char CCP1M0:1;
424 unsigned char CCP1M1:1;
425 unsigned char CCP1M2:1;
426 unsigned char CCP1M3:1;
427 unsigned char CCP1Y:1;
428 unsigned char CCP1X:1;
433 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
435 #define CCP1M0 CCP1CON_bits.CCP1M0
436 #define CCP1M1 CCP1CON_bits.CCP1M1
437 #define CCP1M2 CCP1CON_bits.CCP1M2
438 #define CCP1M3 CCP1CON_bits.CCP1M3
439 #define CCP1Y CCP1CON_bits.CCP1Y
440 #define CCP1X CCP1CON_bits.CCP1X
442 // ----- CCP2CON bits --------------------
445 unsigned char CCP2M0:1;
446 unsigned char CCP2M1:1;
447 unsigned char CCP2M2:1;
448 unsigned char CCP2M3:1;
449 unsigned char CCP2Y:1;
450 unsigned char CCP2X:1;
455 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
457 #define CCP2M0 CCP2CON_bits.CCP2M0
458 #define CCP2M1 CCP2CON_bits.CCP2M1
459 #define CCP2M2 CCP2CON_bits.CCP2M2
460 #define CCP2M3 CCP2CON_bits.CCP2M3
461 #define CCP2Y CCP2CON_bits.CCP2Y
462 #define CCP2X CCP2CON_bits.CCP2X
464 // ----- CMCON bits --------------------
471 unsigned char C1INV:1;
472 unsigned char C2INV:1;
473 unsigned char C1OUT:1;
474 unsigned char C2OUT:1;
477 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
479 #define CM0 CMCON_bits.CM0
480 #define CM1 CMCON_bits.CM1
481 #define CM2 CMCON_bits.CM2
482 #define CIS CMCON_bits.CIS
483 #define C1INV CMCON_bits.C1INV
484 #define C2INV CMCON_bits.C2INV
485 #define C1OUT CMCON_bits.C1OUT
486 #define C2OUT CMCON_bits.C2OUT
488 // ----- CVRCON bits --------------------
491 unsigned char CVR0:1;
492 unsigned char CVR1:1;
493 unsigned char CVR2:1;
494 unsigned char CVR3:1;
496 unsigned char CVRR:1;
497 unsigned char CVROE:1;
498 unsigned char CVREN:1;
501 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
503 #define CVR0 CVRCON_bits.CVR0
504 #define CVR1 CVRCON_bits.CVR1
505 #define CVR2 CVRCON_bits.CVR2
506 #define CVR3 CVRCON_bits.CVR3
507 #define CVRR CVRCON_bits.CVRR
508 #define CVROE CVRCON_bits.CVROE
509 #define CVREN CVRCON_bits.CVREN
511 // ----- EECON1 bits --------------------
516 unsigned char WREN:1;
517 unsigned char WRERR:1;
521 unsigned char EEPGD:1;
524 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
526 #define RD EECON1_bits.RD
527 #define WR EECON1_bits.WR
528 #define WREN EECON1_bits.WREN
529 #define WRERR EECON1_bits.WRERR
530 #define EEPGD EECON1_bits.EEPGD
532 // ----- INTCON bits --------------------
535 unsigned char RBIF:1;
536 unsigned char INTF:1;
537 unsigned char T0IF:1;
538 unsigned char RBIE:1;
539 unsigned char INTE:1;
540 unsigned char T0IE:1;
541 unsigned char PEIE:1;
545 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
547 #define RBIF INTCON_bits.RBIF
548 #define INTF INTCON_bits.INTF
549 #define T0IF INTCON_bits.T0IF
550 #define RBIE INTCON_bits.RBIE
551 #define INTE INTCON_bits.INTE
552 #define T0IE INTCON_bits.T0IE
553 #define PEIE INTCON_bits.PEIE
554 #define GIE INTCON_bits.GIE
556 // ----- OPTION_REG bits --------------------
563 unsigned char T0SE:1;
564 unsigned char T0CS:1;
565 unsigned char INTEDG:1;
566 unsigned char NOT_RBPU:1;
568 } __OPTION_REG_bits_t;
569 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
571 #define PS0 OPTION_REG_bits.PS0
572 #define PS1 OPTION_REG_bits.PS1
573 #define PS2 OPTION_REG_bits.PS2
574 #define PSA OPTION_REG_bits.PSA
575 #define T0SE OPTION_REG_bits.T0SE
576 #define T0CS OPTION_REG_bits.T0CS
577 #define INTEDG OPTION_REG_bits.INTEDG
578 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
580 // ----- PCON bits --------------------
583 unsigned char NOT_BO:1;
584 unsigned char NOT_POR:1;
593 unsigned char NOT_BOR:1;
603 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
605 #define NOT_BO PCON_bits.NOT_BO
606 #define NOT_BOR PCON_bits.NOT_BOR
607 #define NOT_POR PCON_bits.NOT_POR
609 // ----- PIE1 bits --------------------
612 unsigned char TMR1IE:1;
613 unsigned char TMR2IE:1;
614 unsigned char CCP1IE:1;
615 unsigned char SSPIE:1;
616 unsigned char TXIE:1;
617 unsigned char RCIE:1;
618 unsigned char ADIE:1;
622 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
624 #define TMR1IE PIE1_bits.TMR1IE
625 #define TMR2IE PIE1_bits.TMR2IE
626 #define CCP1IE PIE1_bits.CCP1IE
627 #define SSPIE PIE1_bits.SSPIE
628 #define TXIE PIE1_bits.TXIE
629 #define RCIE PIE1_bits.RCIE
630 #define ADIE PIE1_bits.ADIE
632 // ----- PIE2 bits --------------------
635 unsigned char CCP2IE:1;
638 unsigned char BCLIE:1;
639 unsigned char EEIE:1;
641 unsigned char CMIE:1;
645 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
647 #define CCP2IE PIE2_bits.CCP2IE
648 #define BCLIE PIE2_bits.BCLIE
649 #define EEIE PIE2_bits.EEIE
650 #define CMIE PIE2_bits.CMIE
652 // ----- PIR1 bits --------------------
655 unsigned char TMR1IF:1;
656 unsigned char TMR2IF:1;
657 unsigned char CCP1IF:1;
658 unsigned char SSPIF:1;
659 unsigned char TXIF:1;
660 unsigned char RCIF:1;
661 unsigned char ADIF:1;
665 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
667 #define TMR1IF PIR1_bits.TMR1IF
668 #define TMR2IF PIR1_bits.TMR2IF
669 #define CCP1IF PIR1_bits.CCP1IF
670 #define SSPIF PIR1_bits.SSPIF
671 #define TXIF PIR1_bits.TXIF
672 #define RCIF PIR1_bits.RCIF
673 #define ADIF PIR1_bits.ADIF
675 // ----- PIR2 bits --------------------
678 unsigned char CCP2IF:1;
681 unsigned char BCLIF:1;
682 unsigned char EEIF:1;
684 unsigned char CMIF:1;
688 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
690 #define CCP2IF PIR2_bits.CCP2IF
691 #define BCLIF PIR2_bits.BCLIF
692 #define EEIF PIR2_bits.EEIF
693 #define CMIF PIR2_bits.CMIF
695 // ----- RCSTA bits --------------------
698 unsigned char RX9D:1;
699 unsigned char OERR:1;
700 unsigned char FERR:1;
701 unsigned char ADDEN:1;
702 unsigned char CREN:1;
703 unsigned char SREN:1;
705 unsigned char SPEN:1;
708 unsigned char RCD8:1;
724 unsigned char NOT_RC8:1;
734 unsigned char RC8_9:1;
738 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
740 #define RX9D RCSTA_bits.RX9D
741 #define RCD8 RCSTA_bits.RCD8
742 #define OERR RCSTA_bits.OERR
743 #define FERR RCSTA_bits.FERR
744 #define ADDEN RCSTA_bits.ADDEN
745 #define CREN RCSTA_bits.CREN
746 #define SREN RCSTA_bits.SREN
747 #define RX9 RCSTA_bits.RX9
748 #define RC9 RCSTA_bits.RC9
749 #define NOT_RC8 RCSTA_bits.NOT_RC8
750 #define RC8_9 RCSTA_bits.RC8_9
751 #define SPEN RCSTA_bits.SPEN
753 // ----- SSPCON bits --------------------
756 unsigned char SSPM0:1;
757 unsigned char SSPM1:1;
758 unsigned char SSPM2:1;
759 unsigned char SSPM3:1;
761 unsigned char SSPEN:1;
762 unsigned char SSPOV:1;
763 unsigned char WCOL:1;
766 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
768 #define SSPM0 SSPCON_bits.SSPM0
769 #define SSPM1 SSPCON_bits.SSPM1
770 #define SSPM2 SSPCON_bits.SSPM2
771 #define SSPM3 SSPCON_bits.SSPM3
772 #define CKP SSPCON_bits.CKP
773 #define SSPEN SSPCON_bits.SSPEN
774 #define SSPOV SSPCON_bits.SSPOV
775 #define WCOL SSPCON_bits.WCOL
777 // ----- SSPCON2 bits --------------------
781 unsigned char RSEN:1;
783 unsigned char RCEN:1;
784 unsigned char ACKEN:1;
785 unsigned char ACKDT:1;
786 unsigned char ACKSTAT:1;
787 unsigned char GCEN:1;
790 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
792 #define SEN SSPCON2_bits.SEN
793 #define RSEN SSPCON2_bits.RSEN
794 #define PEN SSPCON2_bits.PEN
795 #define RCEN SSPCON2_bits.RCEN
796 #define ACKEN SSPCON2_bits.ACKEN
797 #define ACKDT SSPCON2_bits.ACKDT
798 #define ACKSTAT SSPCON2_bits.ACKSTAT
799 #define GCEN SSPCON2_bits.GCEN
801 // ----- SSPSTAT bits --------------------
816 unsigned char I2C_READ:1;
817 unsigned char I2C_START:1;
818 unsigned char I2C_STOP:1;
819 unsigned char I2C_DATA:1;
826 unsigned char NOT_W:1;
829 unsigned char NOT_A:1;
836 unsigned char NOT_WRITE:1;
839 unsigned char NOT_ADDRESS:1;
856 unsigned char READ_WRITE:1;
859 unsigned char DATA_ADDRESS:1;
864 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
866 #define BF SSPSTAT_bits.BF
867 #define UA SSPSTAT_bits.UA
868 #define R SSPSTAT_bits.R
869 #define I2C_READ SSPSTAT_bits.I2C_READ
870 #define NOT_W SSPSTAT_bits.NOT_W
871 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
872 #define R_W SSPSTAT_bits.R_W
873 #define READ_WRITE SSPSTAT_bits.READ_WRITE
874 #define S SSPSTAT_bits.S
875 #define I2C_START SSPSTAT_bits.I2C_START
876 #define P SSPSTAT_bits.P
877 #define I2C_STOP SSPSTAT_bits.I2C_STOP
878 #define D SSPSTAT_bits.D
879 #define I2C_DATA SSPSTAT_bits.I2C_DATA
880 #define NOT_A SSPSTAT_bits.NOT_A
881 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
882 #define D_A SSPSTAT_bits.D_A
883 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
884 #define CKE SSPSTAT_bits.CKE
885 #define SMP SSPSTAT_bits.SMP
887 // ----- STATUS bits --------------------
893 unsigned char NOT_PD:1;
894 unsigned char NOT_TO:1;
900 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
902 #define C STATUS_bits.C
903 #define DC STATUS_bits.DC
904 #define Z STATUS_bits.Z
905 #define NOT_PD STATUS_bits.NOT_PD
906 #define NOT_TO STATUS_bits.NOT_TO
907 #define RP0 STATUS_bits.RP0
908 #define RP1 STATUS_bits.RP1
909 #define IRP STATUS_bits.IRP
911 // ----- T1CON bits --------------------
914 unsigned char TMR1ON:1;
915 unsigned char TMR1CS:1;
916 unsigned char NOT_T1SYNC:1;
917 unsigned char T1OSCEN:1;
918 unsigned char T1CKPS0:1;
919 unsigned char T1CKPS1:1;
926 unsigned char T1INSYNC:1;
936 unsigned char T1SYNC:1;
944 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
946 #define TMR1ON T1CON_bits.TMR1ON
947 #define TMR1CS T1CON_bits.TMR1CS
948 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
949 #define T1INSYNC T1CON_bits.T1INSYNC
950 #define T1SYNC T1CON_bits.T1SYNC
951 #define T1OSCEN T1CON_bits.T1OSCEN
952 #define T1CKPS0 T1CON_bits.T1CKPS0
953 #define T1CKPS1 T1CON_bits.T1CKPS1
955 // ----- T2CON bits --------------------
958 unsigned char T2CKPS0:1;
959 unsigned char T2CKPS1:1;
960 unsigned char TMR2ON:1;
961 unsigned char TOUTPS0:1;
962 unsigned char TOUTPS1:1;
963 unsigned char TOUTPS2:1;
964 unsigned char TOUTPS3:1;
968 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
970 #define T2CKPS0 T2CON_bits.T2CKPS0
971 #define T2CKPS1 T2CON_bits.T2CKPS1
972 #define TMR2ON T2CON_bits.TMR2ON
973 #define TOUTPS0 T2CON_bits.TOUTPS0
974 #define TOUTPS1 T2CON_bits.TOUTPS1
975 #define TOUTPS2 T2CON_bits.TOUTPS2
976 #define TOUTPS3 T2CON_bits.TOUTPS3
978 // ----- TXSTA bits --------------------
981 unsigned char TX9D:1;
982 unsigned char TRMT:1;
983 unsigned char BRGH:1;
985 unsigned char SYNC:1;
986 unsigned char TXEN:1;
988 unsigned char CSRC:1;
991 unsigned char TXD8:1;
997 unsigned char NOT_TX8:1;
1007 unsigned char TX8_9:1;
1011 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1013 #define TX9D TXSTA_bits.TX9D
1014 #define TXD8 TXSTA_bits.TXD8
1015 #define TRMT TXSTA_bits.TRMT
1016 #define BRGH TXSTA_bits.BRGH
1017 #define SYNC TXSTA_bits.SYNC
1018 #define TXEN TXSTA_bits.TXEN
1019 #define TX9 TXSTA_bits.TX9
1020 #define NOT_TX8 TXSTA_bits.NOT_TX8
1021 #define TX8_9 TXSTA_bits.TX8_9
1022 #define CSRC TXSTA_bits.CSRC