2 // Register Declarations for Microchip 16F876 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define ADRESL_ADDR 0x009E
72 #define ADCON1_ADDR 0x009F
73 #define EEDATA_ADDR 0x010C
74 #define EEADR_ADDR 0x010D
75 #define EEDATH_ADDR 0x010E
76 #define EEADRH_ADDR 0x010F
77 #define EECON1_ADDR 0x018C
78 #define EECON2_ADDR 0x018D
81 // Memory organization.
84 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
85 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
86 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
87 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
88 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
89 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
90 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
91 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
92 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
93 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
94 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
95 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
96 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
97 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
98 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
99 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
100 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
101 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
102 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
103 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
104 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
105 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
106 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
107 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
108 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
109 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
110 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
111 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
112 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
113 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
114 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
115 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
116 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
117 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
118 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
119 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
120 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
121 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
122 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
123 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
124 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
125 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
126 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
127 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
128 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
129 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
130 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
131 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
132 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
133 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
134 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
138 // P16F876.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
141 // This header file defines configurations, registers, and other useful bits of
142 // information for the PIC16F876 microcontroller. These names are taken to match
143 // the data sheets as closely as possible.
145 // Note that the processor must be selected before this file is
146 // included. The processor may be selected the following ways:
148 // 1. Command line switch:
149 // C:\ MPASM MYFILE.ASM /PIC16F876
150 // 2. LIST directive in the source file
152 // 3. Processor Type entry in the MPASM full-screen interface
154 //==========================================================================
158 //==========================================================================
162 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
163 // to match datasheet (DS30292B)
164 //1.00 08/07/98 Initial Release
166 //==========================================================================
170 //==========================================================================
173 // MESSG "Processor-header file mismatch. Verify selected processor."
176 //==========================================================================
178 // Register Definitions
180 //==========================================================================
185 //----- Register Files------------------------------------------------------
187 extern __data __at (INDF_ADDR) volatile char INDF;
188 extern __sfr __at (TMR0_ADDR) TMR0;
189 extern __data __at (PCL_ADDR) volatile char PCL;
190 extern __sfr __at (STATUS_ADDR) STATUS;
191 extern __sfr __at (FSR_ADDR) FSR;
192 extern __sfr __at (PORTA_ADDR) PORTA;
193 extern __sfr __at (PORTB_ADDR) PORTB;
194 extern __sfr __at (PORTC_ADDR) PORTC;
196 extern __sfr __at (PCLATH_ADDR) PCLATH;
197 extern __sfr __at (INTCON_ADDR) INTCON;
198 extern __sfr __at (PIR1_ADDR) PIR1;
199 extern __sfr __at (PIR2_ADDR) PIR2;
200 extern __sfr __at (TMR1L_ADDR) TMR1L;
201 extern __sfr __at (TMR1H_ADDR) TMR1H;
202 extern __sfr __at (T1CON_ADDR) T1CON;
203 extern __sfr __at (TMR2_ADDR) TMR2;
204 extern __sfr __at (T2CON_ADDR) T2CON;
205 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
206 extern __sfr __at (SSPCON_ADDR) SSPCON;
207 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
208 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
209 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
210 extern __sfr __at (RCSTA_ADDR) RCSTA;
211 extern __sfr __at (TXREG_ADDR) TXREG;
212 extern __sfr __at (RCREG_ADDR) RCREG;
213 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
214 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
215 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
216 extern __sfr __at (ADRESH_ADDR) ADRESH;
217 extern __sfr __at (ADCON0_ADDR) ADCON0;
219 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
220 extern __sfr __at (TRISA_ADDR) TRISA;
221 extern __sfr __at (TRISB_ADDR) TRISB;
222 extern __sfr __at (TRISC_ADDR) TRISC;
223 extern __sfr __at (PIE1_ADDR) PIE1;
224 extern __sfr __at (PIE2_ADDR) PIE2;
225 extern __sfr __at (PCON_ADDR) PCON;
226 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
227 extern __sfr __at (PR2_ADDR) PR2;
228 extern __sfr __at (SSPADD_ADDR) SSPADD;
229 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
230 extern __sfr __at (TXSTA_ADDR) TXSTA;
231 extern __sfr __at (SPBRG_ADDR) SPBRG;
232 extern __sfr __at (ADRESL_ADDR) ADRESL;
233 extern __sfr __at (ADCON1_ADDR) ADCON1;
235 extern __sfr __at (EEDATA_ADDR) EEDATA;
236 extern __sfr __at (EEADR_ADDR) EEADR;
237 extern __sfr __at (EEDATH_ADDR) EEDATH;
238 extern __sfr __at (EEADRH_ADDR) EEADRH;
240 extern __sfr __at (EECON1_ADDR) EECON1;
241 extern __sfr __at (EECON2_ADDR) EECON2;
243 //----- STATUS Bits --------------------------------------------------------
246 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
252 //----- PIR2 Bits ----------------------------------------------------------
255 //----- T1CON Bits ---------------------------------------------------------
258 //----- T2CON Bits ---------------------------------------------------------
261 //----- SSPCON Bits --------------------------------------------------------
264 //----- CCP1CON Bits -------------------------------------------------------
267 //----- RCSTA Bits ---------------------------------------------------------
270 //----- CCP2CON Bits -------------------------------------------------------
273 //----- ADCON0 Bits --------------------------------------------------------
276 //----- OPTION Bits ----------------------------------------------------
279 //----- PIE1 Bits ----------------------------------------------------------
282 //----- PIE2 Bits ----------------------------------------------------------
285 //----- PCON Bits ----------------------------------------------------------
288 //----- SSPCON2 Bits --------------------------------------------------------
291 //----- SSPSTAT Bits -------------------------------------------------------
294 //----- TXSTA Bits ---------------------------------------------------------
297 //----- ADCON1 Bits --------------------------------------------------------
300 //----- EECON1 Bits --------------------------------------------------------
303 //==========================================================================
307 //==========================================================================
310 // __BADRAM H'08'-H'09'
311 // __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
312 // __BADRAM H'105', H'107'-H'109'
313 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
315 //==========================================================================
317 // Configuration Bits
319 //==========================================================================
321 #define _CP_ALL 0x0FCF
322 #define _CP_HALF 0x1FDF
323 #define _CP_UPPER_256 0x2FEF
324 #define _CP_OFF 0x3FFF
325 #define _DEBUG_ON 0x37FF
326 #define _DEBUG_OFF 0x3FFF
327 #define _WRT_ENABLE_ON 0x3FFF
328 #define _WRT_ENABLE_OFF 0x3DFF
329 #define _CPD_ON 0x3EFF
330 #define _CPD_OFF 0x3FFF
331 #define _LVP_ON 0x3FFF
332 #define _LVP_OFF 0x3F7F
333 #define _BODEN_ON 0x3FFF
334 #define _BODEN_OFF 0x3FBF
335 #define _PWRTE_OFF 0x3FFF
336 #define _PWRTE_ON 0x3FF7
337 #define _WDT_ON 0x3FFF
338 #define _WDT_OFF 0x3FFB
339 #define _LP_OSC 0x3FFC
340 #define _XT_OSC 0x3FFD
341 #define _HS_OSC 0x3FFE
342 #define _RC_OSC 0x3FFF
346 // ----- ADCON0 bits --------------------
349 unsigned char ADON:1;
352 unsigned char CHS0:1;
353 unsigned char CHS1:1;
354 unsigned char CHS2:1;
355 unsigned char ADCS0:1;
356 unsigned char ADCS1:1;
361 unsigned char NOT_DONE:1;
371 unsigned char GO_DONE:1;
379 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
381 #define ADON ADCON0_bits.ADON
382 #define GO ADCON0_bits.GO
383 #define NOT_DONE ADCON0_bits.NOT_DONE
384 #define GO_DONE ADCON0_bits.GO_DONE
385 #define CHS0 ADCON0_bits.CHS0
386 #define CHS1 ADCON0_bits.CHS1
387 #define CHS2 ADCON0_bits.CHS2
388 #define ADCS0 ADCON0_bits.ADCS0
389 #define ADCS1 ADCON0_bits.ADCS1
391 // ----- ADCON1 bits --------------------
394 unsigned char PCFG0:1;
395 unsigned char PCFG1:1;
396 unsigned char PCFG2:1;
397 unsigned char PCFG3:1;
401 unsigned char ADFM:1;
404 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
406 #define PCFG0 ADCON1_bits.PCFG0
407 #define PCFG1 ADCON1_bits.PCFG1
408 #define PCFG2 ADCON1_bits.PCFG2
409 #define PCFG3 ADCON1_bits.PCFG3
410 #define ADFM ADCON1_bits.ADFM
412 // ----- CCP1CON bits --------------------
415 unsigned char CCP1M0:1;
416 unsigned char CCP1M1:1;
417 unsigned char CCP1M2:1;
418 unsigned char CCP1M3:1;
419 unsigned char CCP1Y:1;
420 unsigned char CCP1X:1;
425 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
427 #define CCP1M0 CCP1CON_bits.CCP1M0
428 #define CCP1M1 CCP1CON_bits.CCP1M1
429 #define CCP1M2 CCP1CON_bits.CCP1M2
430 #define CCP1M3 CCP1CON_bits.CCP1M3
431 #define CCP1Y CCP1CON_bits.CCP1Y
432 #define CCP1X CCP1CON_bits.CCP1X
434 // ----- CCP2CON bits --------------------
437 unsigned char CCP2M0:1;
438 unsigned char CCP2M1:1;
439 unsigned char CCP2M2:1;
440 unsigned char CCP2M3:1;
441 unsigned char CCP2Y:1;
442 unsigned char CCP2X:1;
447 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
449 #define CCP2M0 CCP2CON_bits.CCP2M0
450 #define CCP2M1 CCP2CON_bits.CCP2M1
451 #define CCP2M2 CCP2CON_bits.CCP2M2
452 #define CCP2M3 CCP2CON_bits.CCP2M3
453 #define CCP2Y CCP2CON_bits.CCP2Y
454 #define CCP2X CCP2CON_bits.CCP2X
456 // ----- EECON1 bits --------------------
461 unsigned char WREN:1;
462 unsigned char WRERR:1;
466 unsigned char EEPGD:1;
469 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
471 #define RD EECON1_bits.RD
472 #define WR EECON1_bits.WR
473 #define WREN EECON1_bits.WREN
474 #define WRERR EECON1_bits.WRERR
475 #define EEPGD EECON1_bits.EEPGD
477 // ----- INTCON bits --------------------
480 unsigned char RBIF:1;
481 unsigned char INTF:1;
482 unsigned char T0IF:1;
483 unsigned char RBIE:1;
484 unsigned char INTE:1;
485 unsigned char T0IE:1;
486 unsigned char PEIE:1;
490 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
492 #define RBIF INTCON_bits.RBIF
493 #define INTF INTCON_bits.INTF
494 #define T0IF INTCON_bits.T0IF
495 #define RBIE INTCON_bits.RBIE
496 #define INTE INTCON_bits.INTE
497 #define T0IE INTCON_bits.T0IE
498 #define PEIE INTCON_bits.PEIE
499 #define GIE INTCON_bits.GIE
501 // ----- OPTION_REG bits --------------------
508 unsigned char T0SE:1;
509 unsigned char T0CS:1;
510 unsigned char INTEDG:1;
511 unsigned char NOT_RBPU:1;
513 } __OPTION_REG_bits_t;
514 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
516 #define PS0 OPTION_REG_bits.PS0
517 #define PS1 OPTION_REG_bits.PS1
518 #define PS2 OPTION_REG_bits.PS2
519 #define PSA OPTION_REG_bits.PSA
520 #define T0SE OPTION_REG_bits.T0SE
521 #define T0CS OPTION_REG_bits.T0CS
522 #define INTEDG OPTION_REG_bits.INTEDG
523 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
525 // ----- PCON bits --------------------
528 unsigned char NOT_BO:1;
529 unsigned char NOT_POR:1;
538 unsigned char NOT_BOR:1;
548 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
550 #define NOT_BO PCON_bits.NOT_BO
551 #define NOT_BOR PCON_bits.NOT_BOR
552 #define NOT_POR PCON_bits.NOT_POR
554 // ----- PIE1 bits --------------------
557 unsigned char TMR1IE:1;
558 unsigned char TMR2IE:1;
559 unsigned char CCP1IE:1;
560 unsigned char SSPIE:1;
561 unsigned char TXIE:1;
562 unsigned char RCIE:1;
563 unsigned char ADIE:1;
567 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
569 #define TMR1IE PIE1_bits.TMR1IE
570 #define TMR2IE PIE1_bits.TMR2IE
571 #define CCP1IE PIE1_bits.CCP1IE
572 #define SSPIE PIE1_bits.SSPIE
573 #define TXIE PIE1_bits.TXIE
574 #define RCIE PIE1_bits.RCIE
575 #define ADIE PIE1_bits.ADIE
577 // ----- PIE2 bits --------------------
580 unsigned char CCP2IE:1;
583 unsigned char BCLIE:1;
584 unsigned char EEIE:1;
590 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
592 #define CCP2IE PIE2_bits.CCP2IE
593 #define BCLIE PIE2_bits.BCLIE
594 #define EEIE PIE2_bits.EEIE
596 // ----- PIR1 bits --------------------
599 unsigned char TMR1IF:1;
600 unsigned char TMR2IF:1;
601 unsigned char CCP1IF:1;
602 unsigned char SSPIF:1;
603 unsigned char TXIF:1;
604 unsigned char RCIF:1;
605 unsigned char ADIF:1;
609 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
611 #define TMR1IF PIR1_bits.TMR1IF
612 #define TMR2IF PIR1_bits.TMR2IF
613 #define CCP1IF PIR1_bits.CCP1IF
614 #define SSPIF PIR1_bits.SSPIF
615 #define TXIF PIR1_bits.TXIF
616 #define RCIF PIR1_bits.RCIF
617 #define ADIF PIR1_bits.ADIF
619 // ----- PIR2 bits --------------------
622 unsigned char CCP2IF:1;
625 unsigned char BCLIF:1;
626 unsigned char EEIF:1;
632 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
634 #define CCP2IF PIR2_bits.CCP2IF
635 #define BCLIF PIR2_bits.BCLIF
636 #define EEIF PIR2_bits.EEIF
638 // ----- RCSTA bits --------------------
641 unsigned char RX9D:1;
642 unsigned char OERR:1;
643 unsigned char FERR:1;
644 unsigned char ADDEN:1;
645 unsigned char CREN:1;
646 unsigned char SREN:1;
648 unsigned char SPEN:1;
651 unsigned char RCD8:1;
667 unsigned char NOT_RC8:1;
677 unsigned char RC8_9:1;
681 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
683 #define RX9D RCSTA_bits.RX9D
684 #define RCD8 RCSTA_bits.RCD8
685 #define OERR RCSTA_bits.OERR
686 #define FERR RCSTA_bits.FERR
687 #define ADDEN RCSTA_bits.ADDEN
688 #define CREN RCSTA_bits.CREN
689 #define SREN RCSTA_bits.SREN
690 #define RX9 RCSTA_bits.RX9
691 #define RC9 RCSTA_bits.RC9
692 #define NOT_RC8 RCSTA_bits.NOT_RC8
693 #define RC8_9 RCSTA_bits.RC8_9
694 #define SPEN RCSTA_bits.SPEN
696 // ----- SSPCON bits --------------------
699 unsigned char SSPM0:1;
700 unsigned char SSPM1:1;
701 unsigned char SSPM2:1;
702 unsigned char SSPM3:1;
704 unsigned char SSPEN:1;
705 unsigned char SSPOV:1;
706 unsigned char WCOL:1;
709 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
711 #define SSPM0 SSPCON_bits.SSPM0
712 #define SSPM1 SSPCON_bits.SSPM1
713 #define SSPM2 SSPCON_bits.SSPM2
714 #define SSPM3 SSPCON_bits.SSPM3
715 #define CKP SSPCON_bits.CKP
716 #define SSPEN SSPCON_bits.SSPEN
717 #define SSPOV SSPCON_bits.SSPOV
718 #define WCOL SSPCON_bits.WCOL
720 // ----- SSPCON2 bits --------------------
724 unsigned char RSEN:1;
726 unsigned char RCEN:1;
727 unsigned char ACKEN:1;
728 unsigned char ACKDT:1;
729 unsigned char ACKSTAT:1;
730 unsigned char GCEN:1;
733 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
735 #define SEN SSPCON2_bits.SEN
736 #define RSEN SSPCON2_bits.RSEN
737 #define PEN SSPCON2_bits.PEN
738 #define RCEN SSPCON2_bits.RCEN
739 #define ACKEN SSPCON2_bits.ACKEN
740 #define ACKDT SSPCON2_bits.ACKDT
741 #define ACKSTAT SSPCON2_bits.ACKSTAT
742 #define GCEN SSPCON2_bits.GCEN
744 // ----- SSPSTAT bits --------------------
759 unsigned char I2C_READ:1;
760 unsigned char I2C_START:1;
761 unsigned char I2C_STOP:1;
762 unsigned char I2C_DATA:1;
769 unsigned char NOT_W:1;
772 unsigned char NOT_A:1;
779 unsigned char NOT_WRITE:1;
782 unsigned char NOT_ADDRESS:1;
799 unsigned char READ_WRITE:1;
802 unsigned char DATA_ADDRESS:1;
807 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
809 #define BF SSPSTAT_bits.BF
810 #define UA SSPSTAT_bits.UA
811 #define R SSPSTAT_bits.R
812 #define I2C_READ SSPSTAT_bits.I2C_READ
813 #define NOT_W SSPSTAT_bits.NOT_W
814 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
815 #define R_W SSPSTAT_bits.R_W
816 #define READ_WRITE SSPSTAT_bits.READ_WRITE
817 #define S SSPSTAT_bits.S
818 #define I2C_START SSPSTAT_bits.I2C_START
819 #define P SSPSTAT_bits.P
820 #define I2C_STOP SSPSTAT_bits.I2C_STOP
821 #define D SSPSTAT_bits.D
822 #define I2C_DATA SSPSTAT_bits.I2C_DATA
823 #define NOT_A SSPSTAT_bits.NOT_A
824 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
825 #define D_A SSPSTAT_bits.D_A
826 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
827 #define CKE SSPSTAT_bits.CKE
828 #define SMP SSPSTAT_bits.SMP
830 // ----- STATUS bits --------------------
836 unsigned char NOT_PD:1;
837 unsigned char NOT_TO:1;
843 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
845 #define C STATUS_bits.C
846 #define DC STATUS_bits.DC
847 #define Z STATUS_bits.Z
848 #define NOT_PD STATUS_bits.NOT_PD
849 #define NOT_TO STATUS_bits.NOT_TO
850 #define RP0 STATUS_bits.RP0
851 #define RP1 STATUS_bits.RP1
852 #define IRP STATUS_bits.IRP
854 // ----- T1CON bits --------------------
857 unsigned char TMR1ON:1;
858 unsigned char TMR1CS:1;
859 unsigned char NOT_T1SYNC:1;
860 unsigned char T1OSCEN:1;
861 unsigned char T1CKPS0:1;
862 unsigned char T1CKPS1:1;
869 unsigned char T1INSYNC:1;
879 unsigned char T1SYNC:1;
887 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
889 #define TMR1ON T1CON_bits.TMR1ON
890 #define TMR1CS T1CON_bits.TMR1CS
891 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
892 #define T1INSYNC T1CON_bits.T1INSYNC
893 #define T1SYNC T1CON_bits.T1SYNC
894 #define T1OSCEN T1CON_bits.T1OSCEN
895 #define T1CKPS0 T1CON_bits.T1CKPS0
896 #define T1CKPS1 T1CON_bits.T1CKPS1
898 // ----- T2CON bits --------------------
901 unsigned char T2CKPS0:1;
902 unsigned char T2CKPS1:1;
903 unsigned char TMR2ON:1;
904 unsigned char TOUTPS0:1;
905 unsigned char TOUTPS1:1;
906 unsigned char TOUTPS2:1;
907 unsigned char TOUTPS3:1;
911 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
913 #define T2CKPS0 T2CON_bits.T2CKPS0
914 #define T2CKPS1 T2CON_bits.T2CKPS1
915 #define TMR2ON T2CON_bits.TMR2ON
916 #define TOUTPS0 T2CON_bits.TOUTPS0
917 #define TOUTPS1 T2CON_bits.TOUTPS1
918 #define TOUTPS2 T2CON_bits.TOUTPS2
919 #define TOUTPS3 T2CON_bits.TOUTPS3
921 // ----- TXSTA bits --------------------
924 unsigned char TX9D:1;
925 unsigned char TRMT:1;
926 unsigned char BRGH:1;
928 unsigned char SYNC:1;
929 unsigned char TXEN:1;
931 unsigned char CSRC:1;
934 unsigned char TXD8:1;
940 unsigned char NOT_TX8:1;
950 unsigned char TX8_9:1;
954 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
956 #define TX9D TXSTA_bits.TX9D
957 #define TXD8 TXSTA_bits.TXD8
958 #define TRMT TXSTA_bits.TRMT
959 #define BRGH TXSTA_bits.BRGH
960 #define SYNC TXSTA_bits.SYNC
961 #define TXEN TXSTA_bits.TXEN
962 #define TX9 TXSTA_bits.TX9
963 #define NOT_TX8 TXSTA_bits.NOT_TX8
964 #define TX8_9 TXSTA_bits.TX8_9
965 #define CSRC TXSTA_bits.CSRC