2 // Register Declarations for Microchip 16F874 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define ADRESL_ADDR 0x009E
76 #define ADCON1_ADDR 0x009F
77 #define EEDATA_ADDR 0x010C
78 #define EEADR_ADDR 0x010D
79 #define EEDATH_ADDR 0x010E
80 #define EEADRH_ADDR 0x010F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
85 // Memory organization.
88 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
89 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
90 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
91 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
92 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
93 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
94 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
95 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
96 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
97 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
98 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
99 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
100 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
101 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
102 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
103 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
104 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
105 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
106 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
107 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
108 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
109 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
110 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
111 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
112 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
113 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
114 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
115 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
116 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
117 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
118 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
119 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
120 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
121 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
122 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
123 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
124 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
125 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
126 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
127 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
128 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
129 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
130 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
131 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
132 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
133 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
134 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
135 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
136 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
137 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
138 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
139 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
140 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
141 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
142 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
146 // P16F874.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
149 // This header file defines configurations, registers, and other useful bits of
150 // information for the PIC16F874 microcontroller. These names are taken to match
151 // the data sheets as closely as possible.
153 // Note that the processor must be selected before this file is
154 // included. The processor may be selected the following ways:
156 // 1. Command line switch:
157 // C:\ MPASM MYFILE.ASM /PIC16F874
158 // 2. LIST directive in the source file
160 // 3. Processor Type entry in the MPASM full-screen interface
162 //==========================================================================
166 //==========================================================================
170 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
171 // to match datasheet (DS30292B)
172 //1.11 10/18/98 Changes to file registers to match updated DOS
173 //1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1
174 //1.00 08/07/98 Initial Release
176 //==========================================================================
180 //==========================================================================
183 // MESSG "Processor-header file mismatch. Verify selected processor."
186 //==========================================================================
188 // Register Definitions
190 //==========================================================================
195 //----- Register Files------------------------------------------------------
197 extern data __at (INDF_ADDR) volatile char INDF;
198 extern sfr __at (TMR0_ADDR) TMR0;
199 extern data __at (PCL_ADDR) volatile char PCL;
200 extern sfr __at (STATUS_ADDR) STATUS;
201 extern sfr __at (FSR_ADDR) FSR;
202 extern sfr __at (PORTA_ADDR) PORTA;
203 extern sfr __at (PORTB_ADDR) PORTB;
204 extern sfr __at (PORTC_ADDR) PORTC;
205 extern sfr __at (PORTD_ADDR) PORTD;
206 extern sfr __at (PORTE_ADDR) PORTE;
207 extern sfr __at (PCLATH_ADDR) PCLATH;
208 extern sfr __at (INTCON_ADDR) INTCON;
209 extern sfr __at (PIR1_ADDR) PIR1;
210 extern sfr __at (PIR2_ADDR) PIR2;
211 extern sfr __at (TMR1L_ADDR) TMR1L;
212 extern sfr __at (TMR1H_ADDR) TMR1H;
213 extern sfr __at (T1CON_ADDR) T1CON;
214 extern sfr __at (TMR2_ADDR) TMR2;
215 extern sfr __at (T2CON_ADDR) T2CON;
216 extern sfr __at (SSPBUF_ADDR) SSPBUF;
217 extern sfr __at (SSPCON_ADDR) SSPCON;
218 extern sfr __at (CCPR1L_ADDR) CCPR1L;
219 extern sfr __at (CCPR1H_ADDR) CCPR1H;
220 extern sfr __at (CCP1CON_ADDR) CCP1CON;
221 extern sfr __at (RCSTA_ADDR) RCSTA;
222 extern sfr __at (TXREG_ADDR) TXREG;
223 extern sfr __at (RCREG_ADDR) RCREG;
224 extern sfr __at (CCPR2L_ADDR) CCPR2L;
225 extern sfr __at (CCPR2H_ADDR) CCPR2H;
226 extern sfr __at (CCP2CON_ADDR) CCP2CON;
227 extern sfr __at (ADRESH_ADDR) ADRESH;
228 extern sfr __at (ADCON0_ADDR) ADCON0;
230 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
231 extern sfr __at (TRISA_ADDR) TRISA;
232 extern sfr __at (TRISB_ADDR) TRISB;
233 extern sfr __at (TRISC_ADDR) TRISC;
234 extern sfr __at (TRISD_ADDR) TRISD;
235 extern sfr __at (TRISE_ADDR) TRISE;
236 extern sfr __at (PIE1_ADDR) PIE1;
237 extern sfr __at (PIE2_ADDR) PIE2;
238 extern sfr __at (PCON_ADDR) PCON;
239 extern sfr __at (SSPCON2_ADDR) SSPCON2;
240 extern sfr __at (PR2_ADDR) PR2;
241 extern sfr __at (SSPADD_ADDR) SSPADD;
242 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
243 extern sfr __at (TXSTA_ADDR) TXSTA;
244 extern sfr __at (SPBRG_ADDR) SPBRG;
245 extern sfr __at (ADRESL_ADDR) ADRESL;
246 extern sfr __at (ADCON1_ADDR) ADCON1;
248 extern sfr __at (EEDATA_ADDR) EEDATA;
249 extern sfr __at (EEADR_ADDR) EEADR;
250 extern sfr __at (EEDATH_ADDR) EEDATH;
251 extern sfr __at (EEADRH_ADDR) EEADRH;
253 extern sfr __at (EECON1_ADDR) EECON1;
254 extern sfr __at (EECON2_ADDR) EECON2;
255 //----- STATUS Bits --------------------------------------------------------
258 //----- INTCON Bits --------------------------------------------------------
261 //----- PIR1 Bits ----------------------------------------------------------
264 //----- PIR2 Bits ----------------------------------------------------------
267 //----- T1CON Bits ---------------------------------------------------------
270 //----- T2CON Bits ---------------------------------------------------------
273 //----- SSPCON Bits --------------------------------------------------------
276 //----- CCP1CON Bits -------------------------------------------------------
279 //----- RCSTA Bits ---------------------------------------------------------
282 //----- CCP2CON Bits -------------------------------------------------------
285 //----- ADCON0 Bits --------------------------------------------------------
288 //----- OPTION Bits --------------------------------------------------------
291 //----- TRISE Bits ---------------------------------------------------------
294 //----- PIE1 Bits ----------------------------------------------------------
297 //----- PIE2 Bits ----------------------------------------------------------
300 //----- PCON Bits ----------------------------------------------------------
303 //----- SSPCON2 Bits --------------------------------------------------------
306 //----- SSPSTAT Bits -------------------------------------------------------
309 //----- TXSTA Bits ---------------------------------------------------------
312 //----- ADCON1 Bits --------------------------------------------------------
315 //----- EECON1 Bits --------------------------------------------------------
318 //==========================================================================
322 //==========================================================================
325 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
326 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
327 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
329 //==========================================================================
331 // Configuration Bits
333 //==========================================================================
335 #define _CP_ALL 0x0FCF
336 #define _CP_HALF 0x1FDF
337 #define _CP_UPPER_256 0x2FEF
338 #define _CP_OFF 0x3FFF
339 #define _DEBUG_ON 0x37FF
340 #define _DEBUG_OFF 0x3FFF
341 #define _WRT_ENABLE_ON 0x3FFF
342 #define _WRT_ENABLE_OFF 0x3DFF
343 #define _CPD_ON 0x3EFF
344 #define _CPD_OFF 0x3FFF
345 #define _LVP_ON 0x3FFF
346 #define _LVP_OFF 0x3F7F
347 #define _BODEN_ON 0x3FFF
348 #define _BODEN_OFF 0x3FBF
349 #define _PWRTE_OFF 0x3FFF
350 #define _PWRTE_ON 0x3FF7
351 #define _WDT_ON 0x3FFF
352 #define _WDT_OFF 0x3FFB
353 #define _LP_OSC 0x3FFC
354 #define _XT_OSC 0x3FFD
355 #define _HS_OSC 0x3FFE
356 #define _RC_OSC 0x3FFF
360 // ----- ADCON0 bits --------------------
363 unsigned char ADON:1;
366 unsigned char CHS0:1;
367 unsigned char CHS1:1;
368 unsigned char CHS2:1;
369 unsigned char ADCS0:1;
370 unsigned char ADCS1:1;
375 unsigned char NOT_DONE:1;
385 unsigned char GO_DONE:1;
393 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
395 #define ADON ADCON0_bits.ADON
396 #define GO ADCON0_bits.GO
397 #define NOT_DONE ADCON0_bits.NOT_DONE
398 #define GO_DONE ADCON0_bits.GO_DONE
399 #define CHS0 ADCON0_bits.CHS0
400 #define CHS1 ADCON0_bits.CHS1
401 #define CHS2 ADCON0_bits.CHS2
402 #define ADCS0 ADCON0_bits.ADCS0
403 #define ADCS1 ADCON0_bits.ADCS1
405 // ----- ADCON1 bits --------------------
408 unsigned char PCFG0:1;
409 unsigned char PCFG1:1;
410 unsigned char PCFG2:1;
411 unsigned char PCFG3:1;
415 unsigned char ADFM:1;
418 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
420 #define PCFG0 ADCON1_bits.PCFG0
421 #define PCFG1 ADCON1_bits.PCFG1
422 #define PCFG2 ADCON1_bits.PCFG2
423 #define PCFG3 ADCON1_bits.PCFG3
424 #define ADFM ADCON1_bits.ADFM
426 // ----- CCP1CON bits --------------------
429 unsigned char CCP1M0:1;
430 unsigned char CCP1M1:1;
431 unsigned char CCP1M2:1;
432 unsigned char CCP1M3:1;
433 unsigned char CCP1Y:1;
434 unsigned char CCP1X:1;
439 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
441 #define CCP1M0 CCP1CON_bits.CCP1M0
442 #define CCP1M1 CCP1CON_bits.CCP1M1
443 #define CCP1M2 CCP1CON_bits.CCP1M2
444 #define CCP1M3 CCP1CON_bits.CCP1M3
445 #define CCP1Y CCP1CON_bits.CCP1Y
446 #define CCP1X CCP1CON_bits.CCP1X
448 // ----- CCP2CON bits --------------------
451 unsigned char CCP2M0:1;
452 unsigned char CCP2M1:1;
453 unsigned char CCP2M2:1;
454 unsigned char CCP2M3:1;
455 unsigned char CCP2Y:1;
456 unsigned char CCP2X:1;
461 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
463 #define CCP2M0 CCP2CON_bits.CCP2M0
464 #define CCP2M1 CCP2CON_bits.CCP2M1
465 #define CCP2M2 CCP2CON_bits.CCP2M2
466 #define CCP2M3 CCP2CON_bits.CCP2M3
467 #define CCP2Y CCP2CON_bits.CCP2Y
468 #define CCP2X CCP2CON_bits.CCP2X
470 // ----- EECON1 bits --------------------
475 unsigned char WREN:1;
476 unsigned char WRERR:1;
480 unsigned char EEPGD:1;
483 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
485 #define RD EECON1_bits.RD
486 #define WR EECON1_bits.WR
487 #define WREN EECON1_bits.WREN
488 #define WRERR EECON1_bits.WRERR
489 #define EEPGD EECON1_bits.EEPGD
491 // ----- INTCON bits --------------------
494 unsigned char RBIF:1;
495 unsigned char INTF:1;
496 unsigned char T0IF:1;
497 unsigned char RBIE:1;
498 unsigned char INTE:1;
499 unsigned char T0IE:1;
500 unsigned char PEIE:1;
504 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
506 #define RBIF INTCON_bits.RBIF
507 #define INTF INTCON_bits.INTF
508 #define T0IF INTCON_bits.T0IF
509 #define RBIE INTCON_bits.RBIE
510 #define INTE INTCON_bits.INTE
511 #define T0IE INTCON_bits.T0IE
512 #define PEIE INTCON_bits.PEIE
513 #define GIE INTCON_bits.GIE
515 // ----- OPTION_REG bits --------------------
522 unsigned char T0SE:1;
523 unsigned char T0CS:1;
524 unsigned char INTEDG:1;
525 unsigned char NOT_RBPU:1;
527 } __OPTION_REG_bits_t;
528 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
530 #define PS0 OPTION_REG_bits.PS0
531 #define PS1 OPTION_REG_bits.PS1
532 #define PS2 OPTION_REG_bits.PS2
533 #define PSA OPTION_REG_bits.PSA
534 #define T0SE OPTION_REG_bits.T0SE
535 #define T0CS OPTION_REG_bits.T0CS
536 #define INTEDG OPTION_REG_bits.INTEDG
537 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
539 // ----- PCON bits --------------------
542 unsigned char NOT_BO:1;
543 unsigned char NOT_POR:1;
552 unsigned char NOT_BOR:1;
562 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
564 #define NOT_BO PCON_bits.NOT_BO
565 #define NOT_BOR PCON_bits.NOT_BOR
566 #define NOT_POR PCON_bits.NOT_POR
568 // ----- PIE1 bits --------------------
571 unsigned char TMR1IE:1;
572 unsigned char TMR2IE:1;
573 unsigned char CCP1IE:1;
574 unsigned char SSPIE:1;
575 unsigned char TXIE:1;
576 unsigned char RCIE:1;
577 unsigned char ADIE:1;
578 unsigned char PSPIE:1;
581 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
583 #define TMR1IE PIE1_bits.TMR1IE
584 #define TMR2IE PIE1_bits.TMR2IE
585 #define CCP1IE PIE1_bits.CCP1IE
586 #define SSPIE PIE1_bits.SSPIE
587 #define TXIE PIE1_bits.TXIE
588 #define RCIE PIE1_bits.RCIE
589 #define ADIE PIE1_bits.ADIE
590 #define PSPIE PIE1_bits.PSPIE
592 // ----- PIE2 bits --------------------
595 unsigned char CCP2IE:1;
598 unsigned char BCLIE:1;
599 unsigned char EEIE:1;
605 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
607 #define CCP2IE PIE2_bits.CCP2IE
608 #define BCLIE PIE2_bits.BCLIE
609 #define EEIE PIE2_bits.EEIE
611 // ----- PIR1 bits --------------------
614 unsigned char TMR1IF:1;
615 unsigned char TMR2IF:1;
616 unsigned char CCP1IF:1;
617 unsigned char SSPIF:1;
618 unsigned char TXIF:1;
619 unsigned char RCIF:1;
620 unsigned char ADIF:1;
621 unsigned char PSPIF:1;
624 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
626 #define TMR1IF PIR1_bits.TMR1IF
627 #define TMR2IF PIR1_bits.TMR2IF
628 #define CCP1IF PIR1_bits.CCP1IF
629 #define SSPIF PIR1_bits.SSPIF
630 #define TXIF PIR1_bits.TXIF
631 #define RCIF PIR1_bits.RCIF
632 #define ADIF PIR1_bits.ADIF
633 #define PSPIF PIR1_bits.PSPIF
635 // ----- PIR2 bits --------------------
638 unsigned char CCP2IF:1;
641 unsigned char BCLIF:1;
642 unsigned char EEIF:1;
648 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
650 #define CCP2IF PIR2_bits.CCP2IF
651 #define BCLIF PIR2_bits.BCLIF
652 #define EEIF PIR2_bits.EEIF
654 // ----- RCSTA bits --------------------
657 unsigned char RX9D:1;
658 unsigned char OERR:1;
659 unsigned char FERR:1;
660 unsigned char ADDEN:1;
661 unsigned char CREN:1;
662 unsigned char SREN:1;
664 unsigned char SPEN:1;
667 unsigned char RCD8:1;
683 unsigned char NOT_RC8:1;
693 unsigned char RC8_9:1;
697 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
699 #define RX9D RCSTA_bits.RX9D
700 #define RCD8 RCSTA_bits.RCD8
701 #define OERR RCSTA_bits.OERR
702 #define FERR RCSTA_bits.FERR
703 #define ADDEN RCSTA_bits.ADDEN
704 #define CREN RCSTA_bits.CREN
705 #define SREN RCSTA_bits.SREN
706 #define RX9 RCSTA_bits.RX9
707 #define RC9 RCSTA_bits.RC9
708 #define NOT_RC8 RCSTA_bits.NOT_RC8
709 #define RC8_9 RCSTA_bits.RC8_9
710 #define SPEN RCSTA_bits.SPEN
712 // ----- SSPCON bits --------------------
715 unsigned char SSPM0:1;
716 unsigned char SSPM1:1;
717 unsigned char SSPM2:1;
718 unsigned char SSPM3:1;
720 unsigned char SSPEN:1;
721 unsigned char SSPOV:1;
722 unsigned char WCOL:1;
725 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
727 #define SSPM0 SSPCON_bits.SSPM0
728 #define SSPM1 SSPCON_bits.SSPM1
729 #define SSPM2 SSPCON_bits.SSPM2
730 #define SSPM3 SSPCON_bits.SSPM3
731 #define CKP SSPCON_bits.CKP
732 #define SSPEN SSPCON_bits.SSPEN
733 #define SSPOV SSPCON_bits.SSPOV
734 #define WCOL SSPCON_bits.WCOL
736 // ----- SSPCON2 bits --------------------
740 unsigned char RSEN:1;
742 unsigned char RCEN:1;
743 unsigned char ACKEN:1;
744 unsigned char ACKDT:1;
745 unsigned char ACKSTAT:1;
746 unsigned char GCEN:1;
749 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
751 #define SEN SSPCON2_bits.SEN
752 #define RSEN SSPCON2_bits.RSEN
753 #define PEN SSPCON2_bits.PEN
754 #define RCEN SSPCON2_bits.RCEN
755 #define ACKEN SSPCON2_bits.ACKEN
756 #define ACKDT SSPCON2_bits.ACKDT
757 #define ACKSTAT SSPCON2_bits.ACKSTAT
758 #define GCEN SSPCON2_bits.GCEN
760 // ----- SSPSTAT bits --------------------
775 unsigned char I2C_READ:1;
776 unsigned char I2C_START:1;
777 unsigned char I2C_STOP:1;
778 unsigned char I2C_DATA:1;
785 unsigned char NOT_W:1;
788 unsigned char NOT_A:1;
795 unsigned char NOT_WRITE:1;
798 unsigned char NOT_ADDRESS:1;
815 unsigned char READ_WRITE:1;
818 unsigned char DATA_ADDRESS:1;
823 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
825 #define BF SSPSTAT_bits.BF
826 #define UA SSPSTAT_bits.UA
827 #define R SSPSTAT_bits.R
828 #define I2C_READ SSPSTAT_bits.I2C_READ
829 #define NOT_W SSPSTAT_bits.NOT_W
830 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
831 #define R_W SSPSTAT_bits.R_W
832 #define READ_WRITE SSPSTAT_bits.READ_WRITE
833 #define S SSPSTAT_bits.S
834 #define I2C_START SSPSTAT_bits.I2C_START
835 #define P SSPSTAT_bits.P
836 #define I2C_STOP SSPSTAT_bits.I2C_STOP
837 #define D SSPSTAT_bits.D
838 #define I2C_DATA SSPSTAT_bits.I2C_DATA
839 #define NOT_A SSPSTAT_bits.NOT_A
840 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
841 #define D_A SSPSTAT_bits.D_A
842 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
843 #define CKE SSPSTAT_bits.CKE
844 #define SMP SSPSTAT_bits.SMP
846 // ----- STATUS bits --------------------
852 unsigned char NOT_PD:1;
853 unsigned char NOT_TO:1;
859 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
861 #define C STATUS_bits.C
862 #define DC STATUS_bits.DC
863 #define Z STATUS_bits.Z
864 #define NOT_PD STATUS_bits.NOT_PD
865 #define NOT_TO STATUS_bits.NOT_TO
866 #define RP0 STATUS_bits.RP0
867 #define RP1 STATUS_bits.RP1
868 #define IRP STATUS_bits.IRP
870 // ----- T1CON bits --------------------
873 unsigned char TMR1ON:1;
874 unsigned char TMR1CS:1;
875 unsigned char NOT_T1SYNC:1;
876 unsigned char T1OSCEN:1;
877 unsigned char T1CKPS0:1;
878 unsigned char T1CKPS1:1;
885 unsigned char T1INSYNC:1;
895 unsigned char T1SYNC:1;
903 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
905 #define TMR1ON T1CON_bits.TMR1ON
906 #define TMR1CS T1CON_bits.TMR1CS
907 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
908 #define T1INSYNC T1CON_bits.T1INSYNC
909 #define T1SYNC T1CON_bits.T1SYNC
910 #define T1OSCEN T1CON_bits.T1OSCEN
911 #define T1CKPS0 T1CON_bits.T1CKPS0
912 #define T1CKPS1 T1CON_bits.T1CKPS1
914 // ----- T2CON bits --------------------
917 unsigned char T2CKPS0:1;
918 unsigned char T2CKPS1:1;
919 unsigned char TMR2ON:1;
920 unsigned char TOUTPS0:1;
921 unsigned char TOUTPS1:1;
922 unsigned char TOUTPS2:1;
923 unsigned char TOUTPS3:1;
927 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
929 #define T2CKPS0 T2CON_bits.T2CKPS0
930 #define T2CKPS1 T2CON_bits.T2CKPS1
931 #define TMR2ON T2CON_bits.TMR2ON
932 #define TOUTPS0 T2CON_bits.TOUTPS0
933 #define TOUTPS1 T2CON_bits.TOUTPS1
934 #define TOUTPS2 T2CON_bits.TOUTPS2
935 #define TOUTPS3 T2CON_bits.TOUTPS3
937 // ----- TRISE bits --------------------
940 unsigned char TRISE0:1;
941 unsigned char TRISE1:1;
942 unsigned char TRISE2:1;
944 unsigned char PSPMODE:1;
945 unsigned char IBOV:1;
950 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
952 #define TRISE0 TRISE_bits.TRISE0
953 #define TRISE1 TRISE_bits.TRISE1
954 #define TRISE2 TRISE_bits.TRISE2
955 #define PSPMODE TRISE_bits.PSPMODE
956 #define IBOV TRISE_bits.IBOV
957 #define OBF TRISE_bits.OBF
958 #define IBF TRISE_bits.IBF
960 // ----- TXSTA bits --------------------
963 unsigned char TX9D:1;
964 unsigned char TRMT:1;
965 unsigned char BRGH:1;
967 unsigned char SYNC:1;
968 unsigned char TXEN:1;
970 unsigned char CSRC:1;
973 unsigned char TXD8:1;
979 unsigned char NOT_TX8:1;
989 unsigned char TX8_9:1;
993 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
995 #define TX9D TXSTA_bits.TX9D
996 #define TXD8 TXSTA_bits.TXD8
997 #define TRMT TXSTA_bits.TRMT
998 #define BRGH TXSTA_bits.BRGH
999 #define SYNC TXSTA_bits.SYNC
1000 #define TXEN TXSTA_bits.TXEN
1001 #define TX9 TXSTA_bits.TX9
1002 #define NOT_TX8 TXSTA_bits.NOT_TX8
1003 #define TX8_9 TXSTA_bits.TX8_9
1004 #define CSRC TXSTA_bits.CSRC