2 // Register Declarations for Microchip 16F874 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define ADRESL_ADDR 0x009E
76 #define ADCON1_ADDR 0x009F
77 #define EEDATA_ADDR 0x010C
78 #define EEADR_ADDR 0x010D
79 #define EEDATH_ADDR 0x010E
80 #define EEADRH_ADDR 0x010F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
85 // Memory organization.
91 // P16F874.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
94 // This header file defines configurations, registers, and other useful bits of
95 // information for the PIC16F874 microcontroller. These names are taken to match
96 // the data sheets as closely as possible.
98 // Note that the processor must be selected before this file is
99 // included. The processor may be selected the following ways:
101 // 1. Command line switch:
102 // C:\ MPASM MYFILE.ASM /PIC16F874
103 // 2. LIST directive in the source file
105 // 3. Processor Type entry in the MPASM full-screen interface
107 //==========================================================================
111 //==========================================================================
115 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
116 // to match datasheet (DS30292B)
117 //1.11 10/18/98 Changes to file registers to match updated DOS
118 //1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1
119 //1.00 08/07/98 Initial Release
121 //==========================================================================
125 //==========================================================================
128 // MESSG "Processor-header file mismatch. Verify selected processor."
131 //==========================================================================
133 // Register Definitions
135 //==========================================================================
140 //----- Register Files------------------------------------------------------
142 extern __data __at (INDF_ADDR) volatile char INDF;
143 extern __sfr __at (TMR0_ADDR) TMR0;
144 extern __data __at (PCL_ADDR) volatile char PCL;
145 extern __sfr __at (STATUS_ADDR) STATUS;
146 extern __sfr __at (FSR_ADDR) FSR;
147 extern __sfr __at (PORTA_ADDR) PORTA;
148 extern __sfr __at (PORTB_ADDR) PORTB;
149 extern __sfr __at (PORTC_ADDR) PORTC;
150 extern __sfr __at (PORTD_ADDR) PORTD;
151 extern __sfr __at (PORTE_ADDR) PORTE;
152 extern __sfr __at (PCLATH_ADDR) PCLATH;
153 extern __sfr __at (INTCON_ADDR) INTCON;
154 extern __sfr __at (PIR1_ADDR) PIR1;
155 extern __sfr __at (PIR2_ADDR) PIR2;
156 extern __sfr __at (TMR1L_ADDR) TMR1L;
157 extern __sfr __at (TMR1H_ADDR) TMR1H;
158 extern __sfr __at (T1CON_ADDR) T1CON;
159 extern __sfr __at (TMR2_ADDR) TMR2;
160 extern __sfr __at (T2CON_ADDR) T2CON;
161 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
162 extern __sfr __at (SSPCON_ADDR) SSPCON;
163 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
164 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
165 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
166 extern __sfr __at (RCSTA_ADDR) RCSTA;
167 extern __sfr __at (TXREG_ADDR) TXREG;
168 extern __sfr __at (RCREG_ADDR) RCREG;
169 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
170 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
171 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
172 extern __sfr __at (ADRESH_ADDR) ADRESH;
173 extern __sfr __at (ADCON0_ADDR) ADCON0;
175 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
176 extern __sfr __at (TRISA_ADDR) TRISA;
177 extern __sfr __at (TRISB_ADDR) TRISB;
178 extern __sfr __at (TRISC_ADDR) TRISC;
179 extern __sfr __at (TRISD_ADDR) TRISD;
180 extern __sfr __at (TRISE_ADDR) TRISE;
181 extern __sfr __at (PIE1_ADDR) PIE1;
182 extern __sfr __at (PIE2_ADDR) PIE2;
183 extern __sfr __at (PCON_ADDR) PCON;
184 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
185 extern __sfr __at (PR2_ADDR) PR2;
186 extern __sfr __at (SSPADD_ADDR) SSPADD;
187 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
188 extern __sfr __at (TXSTA_ADDR) TXSTA;
189 extern __sfr __at (SPBRG_ADDR) SPBRG;
190 extern __sfr __at (ADRESL_ADDR) ADRESL;
191 extern __sfr __at (ADCON1_ADDR) ADCON1;
193 extern __sfr __at (EEDATA_ADDR) EEDATA;
194 extern __sfr __at (EEADR_ADDR) EEADR;
195 extern __sfr __at (EEDATH_ADDR) EEDATH;
196 extern __sfr __at (EEADRH_ADDR) EEADRH;
198 extern __sfr __at (EECON1_ADDR) EECON1;
199 extern __sfr __at (EECON2_ADDR) EECON2;
200 //----- STATUS Bits --------------------------------------------------------
203 //----- INTCON Bits --------------------------------------------------------
206 //----- PIR1 Bits ----------------------------------------------------------
209 //----- PIR2 Bits ----------------------------------------------------------
212 //----- T1CON Bits ---------------------------------------------------------
215 //----- T2CON Bits ---------------------------------------------------------
218 //----- SSPCON Bits --------------------------------------------------------
221 //----- CCP1CON Bits -------------------------------------------------------
224 //----- RCSTA Bits ---------------------------------------------------------
227 //----- CCP2CON Bits -------------------------------------------------------
230 //----- ADCON0 Bits --------------------------------------------------------
233 //----- OPTION Bits --------------------------------------------------------
236 //----- TRISE Bits ---------------------------------------------------------
239 //----- PIE1 Bits ----------------------------------------------------------
242 //----- PIE2 Bits ----------------------------------------------------------
245 //----- PCON Bits ----------------------------------------------------------
248 //----- SSPCON2 Bits --------------------------------------------------------
251 //----- SSPSTAT Bits -------------------------------------------------------
254 //----- TXSTA Bits ---------------------------------------------------------
257 //----- ADCON1 Bits --------------------------------------------------------
260 //----- EECON1 Bits --------------------------------------------------------
263 //==========================================================================
267 //==========================================================================
270 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
271 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
272 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
274 //==========================================================================
276 // Configuration Bits
278 //==========================================================================
280 #define _CP_ALL 0x0FCF
281 #define _CP_HALF 0x1FDF
282 #define _CP_UPPER_256 0x2FEF
283 #define _CP_OFF 0x3FFF
284 #define _DEBUG_ON 0x37FF
285 #define _DEBUG_OFF 0x3FFF
286 #define _WRT_ENABLE_ON 0x3FFF
287 #define _WRT_ENABLE_OFF 0x3DFF
288 #define _CPD_ON 0x3EFF
289 #define _CPD_OFF 0x3FFF
290 #define _LVP_ON 0x3FFF
291 #define _LVP_OFF 0x3F7F
292 #define _BODEN_ON 0x3FFF
293 #define _BODEN_OFF 0x3FBF
294 #define _PWRTE_OFF 0x3FFF
295 #define _PWRTE_ON 0x3FF7
296 #define _WDT_ON 0x3FFF
297 #define _WDT_OFF 0x3FFB
298 #define _LP_OSC 0x3FFC
299 #define _XT_OSC 0x3FFD
300 #define _HS_OSC 0x3FFE
301 #define _RC_OSC 0x3FFF
305 // ----- ADCON0 bits --------------------
308 unsigned char ADON:1;
311 unsigned char CHS0:1;
312 unsigned char CHS1:1;
313 unsigned char CHS2:1;
314 unsigned char ADCS0:1;
315 unsigned char ADCS1:1;
320 unsigned char NOT_DONE:1;
330 unsigned char GO_DONE:1;
338 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
340 #define ADON ADCON0_bits.ADON
341 #define GO ADCON0_bits.GO
342 #define NOT_DONE ADCON0_bits.NOT_DONE
343 #define GO_DONE ADCON0_bits.GO_DONE
344 #define CHS0 ADCON0_bits.CHS0
345 #define CHS1 ADCON0_bits.CHS1
346 #define CHS2 ADCON0_bits.CHS2
347 #define ADCS0 ADCON0_bits.ADCS0
348 #define ADCS1 ADCON0_bits.ADCS1
350 // ----- ADCON1 bits --------------------
353 unsigned char PCFG0:1;
354 unsigned char PCFG1:1;
355 unsigned char PCFG2:1;
356 unsigned char PCFG3:1;
360 unsigned char ADFM:1;
363 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
365 #define PCFG0 ADCON1_bits.PCFG0
366 #define PCFG1 ADCON1_bits.PCFG1
367 #define PCFG2 ADCON1_bits.PCFG2
368 #define PCFG3 ADCON1_bits.PCFG3
369 #define ADFM ADCON1_bits.ADFM
371 // ----- CCP1CON bits --------------------
374 unsigned char CCP1M0:1;
375 unsigned char CCP1M1:1;
376 unsigned char CCP1M2:1;
377 unsigned char CCP1M3:1;
378 unsigned char CCP1Y:1;
379 unsigned char CCP1X:1;
384 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
386 #define CCP1M0 CCP1CON_bits.CCP1M0
387 #define CCP1M1 CCP1CON_bits.CCP1M1
388 #define CCP1M2 CCP1CON_bits.CCP1M2
389 #define CCP1M3 CCP1CON_bits.CCP1M3
390 #define CCP1Y CCP1CON_bits.CCP1Y
391 #define CCP1X CCP1CON_bits.CCP1X
393 // ----- CCP2CON bits --------------------
396 unsigned char CCP2M0:1;
397 unsigned char CCP2M1:1;
398 unsigned char CCP2M2:1;
399 unsigned char CCP2M3:1;
400 unsigned char CCP2Y:1;
401 unsigned char CCP2X:1;
406 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
408 #define CCP2M0 CCP2CON_bits.CCP2M0
409 #define CCP2M1 CCP2CON_bits.CCP2M1
410 #define CCP2M2 CCP2CON_bits.CCP2M2
411 #define CCP2M3 CCP2CON_bits.CCP2M3
412 #define CCP2Y CCP2CON_bits.CCP2Y
413 #define CCP2X CCP2CON_bits.CCP2X
415 // ----- EECON1 bits --------------------
420 unsigned char WREN:1;
421 unsigned char WRERR:1;
425 unsigned char EEPGD:1;
428 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
430 #define RD EECON1_bits.RD
431 #define WR EECON1_bits.WR
432 #define WREN EECON1_bits.WREN
433 #define WRERR EECON1_bits.WRERR
434 #define EEPGD EECON1_bits.EEPGD
436 // ----- INTCON bits --------------------
439 unsigned char RBIF:1;
440 unsigned char INTF:1;
441 unsigned char T0IF:1;
442 unsigned char RBIE:1;
443 unsigned char INTE:1;
444 unsigned char T0IE:1;
445 unsigned char PEIE:1;
449 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
451 #define RBIF INTCON_bits.RBIF
452 #define INTF INTCON_bits.INTF
453 #define T0IF INTCON_bits.T0IF
454 #define RBIE INTCON_bits.RBIE
455 #define INTE INTCON_bits.INTE
456 #define T0IE INTCON_bits.T0IE
457 #define PEIE INTCON_bits.PEIE
458 #define GIE INTCON_bits.GIE
460 // ----- OPTION_REG bits --------------------
467 unsigned char T0SE:1;
468 unsigned char T0CS:1;
469 unsigned char INTEDG:1;
470 unsigned char NOT_RBPU:1;
472 } __OPTION_REG_bits_t;
473 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
475 #define PS0 OPTION_REG_bits.PS0
476 #define PS1 OPTION_REG_bits.PS1
477 #define PS2 OPTION_REG_bits.PS2
478 #define PSA OPTION_REG_bits.PSA
479 #define T0SE OPTION_REG_bits.T0SE
480 #define T0CS OPTION_REG_bits.T0CS
481 #define INTEDG OPTION_REG_bits.INTEDG
482 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
484 // ----- PCON bits --------------------
487 unsigned char NOT_BO:1;
488 unsigned char NOT_POR:1;
497 unsigned char NOT_BOR:1;
507 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
509 #define NOT_BO PCON_bits.NOT_BO
510 #define NOT_BOR PCON_bits.NOT_BOR
511 #define NOT_POR PCON_bits.NOT_POR
513 // ----- PIE1 bits --------------------
516 unsigned char TMR1IE:1;
517 unsigned char TMR2IE:1;
518 unsigned char CCP1IE:1;
519 unsigned char SSPIE:1;
520 unsigned char TXIE:1;
521 unsigned char RCIE:1;
522 unsigned char ADIE:1;
523 unsigned char PSPIE:1;
526 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
528 #define TMR1IE PIE1_bits.TMR1IE
529 #define TMR2IE PIE1_bits.TMR2IE
530 #define CCP1IE PIE1_bits.CCP1IE
531 #define SSPIE PIE1_bits.SSPIE
532 #define TXIE PIE1_bits.TXIE
533 #define RCIE PIE1_bits.RCIE
534 #define ADIE PIE1_bits.ADIE
535 #define PSPIE PIE1_bits.PSPIE
537 // ----- PIE2 bits --------------------
540 unsigned char CCP2IE:1;
543 unsigned char BCLIE:1;
544 unsigned char EEIE:1;
550 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
552 #define CCP2IE PIE2_bits.CCP2IE
553 #define BCLIE PIE2_bits.BCLIE
554 #define EEIE PIE2_bits.EEIE
556 // ----- PIR1 bits --------------------
559 unsigned char TMR1IF:1;
560 unsigned char TMR2IF:1;
561 unsigned char CCP1IF:1;
562 unsigned char SSPIF:1;
563 unsigned char TXIF:1;
564 unsigned char RCIF:1;
565 unsigned char ADIF:1;
566 unsigned char PSPIF:1;
569 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
571 #define TMR1IF PIR1_bits.TMR1IF
572 #define TMR2IF PIR1_bits.TMR2IF
573 #define CCP1IF PIR1_bits.CCP1IF
574 #define SSPIF PIR1_bits.SSPIF
575 #define TXIF PIR1_bits.TXIF
576 #define RCIF PIR1_bits.RCIF
577 #define ADIF PIR1_bits.ADIF
578 #define PSPIF PIR1_bits.PSPIF
580 // ----- PIR2 bits --------------------
583 unsigned char CCP2IF:1;
586 unsigned char BCLIF:1;
587 unsigned char EEIF:1;
593 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
595 #define CCP2IF PIR2_bits.CCP2IF
596 #define BCLIF PIR2_bits.BCLIF
597 #define EEIF PIR2_bits.EEIF
599 // ----- RCSTA bits --------------------
602 unsigned char RX9D:1;
603 unsigned char OERR:1;
604 unsigned char FERR:1;
605 unsigned char ADDEN:1;
606 unsigned char CREN:1;
607 unsigned char SREN:1;
609 unsigned char SPEN:1;
612 unsigned char RCD8:1;
628 unsigned char NOT_RC8:1;
638 unsigned char RC8_9:1;
642 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
644 #define RX9D RCSTA_bits.RX9D
645 #define RCD8 RCSTA_bits.RCD8
646 #define OERR RCSTA_bits.OERR
647 #define FERR RCSTA_bits.FERR
648 #define ADDEN RCSTA_bits.ADDEN
649 #define CREN RCSTA_bits.CREN
650 #define SREN RCSTA_bits.SREN
651 #define RX9 RCSTA_bits.RX9
652 #define RC9 RCSTA_bits.RC9
653 #define NOT_RC8 RCSTA_bits.NOT_RC8
654 #define RC8_9 RCSTA_bits.RC8_9
655 #define SPEN RCSTA_bits.SPEN
657 // ----- SSPCON bits --------------------
660 unsigned char SSPM0:1;
661 unsigned char SSPM1:1;
662 unsigned char SSPM2:1;
663 unsigned char SSPM3:1;
665 unsigned char SSPEN:1;
666 unsigned char SSPOV:1;
667 unsigned char WCOL:1;
670 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
672 #define SSPM0 SSPCON_bits.SSPM0
673 #define SSPM1 SSPCON_bits.SSPM1
674 #define SSPM2 SSPCON_bits.SSPM2
675 #define SSPM3 SSPCON_bits.SSPM3
676 #define CKP SSPCON_bits.CKP
677 #define SSPEN SSPCON_bits.SSPEN
678 #define SSPOV SSPCON_bits.SSPOV
679 #define WCOL SSPCON_bits.WCOL
681 // ----- SSPCON2 bits --------------------
685 unsigned char RSEN:1;
687 unsigned char RCEN:1;
688 unsigned char ACKEN:1;
689 unsigned char ACKDT:1;
690 unsigned char ACKSTAT:1;
691 unsigned char GCEN:1;
694 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
696 #define SEN SSPCON2_bits.SEN
697 #define RSEN SSPCON2_bits.RSEN
698 #define PEN SSPCON2_bits.PEN
699 #define RCEN SSPCON2_bits.RCEN
700 #define ACKEN SSPCON2_bits.ACKEN
701 #define ACKDT SSPCON2_bits.ACKDT
702 #define ACKSTAT SSPCON2_bits.ACKSTAT
703 #define GCEN SSPCON2_bits.GCEN
705 // ----- SSPSTAT bits --------------------
720 unsigned char I2C_READ:1;
721 unsigned char I2C_START:1;
722 unsigned char I2C_STOP:1;
723 unsigned char I2C_DATA:1;
730 unsigned char NOT_W:1;
733 unsigned char NOT_A:1;
740 unsigned char NOT_WRITE:1;
743 unsigned char NOT_ADDRESS:1;
760 unsigned char READ_WRITE:1;
763 unsigned char DATA_ADDRESS:1;
768 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
770 #define BF SSPSTAT_bits.BF
771 #define UA SSPSTAT_bits.UA
772 #define R SSPSTAT_bits.R
773 #define I2C_READ SSPSTAT_bits.I2C_READ
774 #define NOT_W SSPSTAT_bits.NOT_W
775 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
776 #define R_W SSPSTAT_bits.R_W
777 #define READ_WRITE SSPSTAT_bits.READ_WRITE
778 #define S SSPSTAT_bits.S
779 #define I2C_START SSPSTAT_bits.I2C_START
780 #define P SSPSTAT_bits.P
781 #define I2C_STOP SSPSTAT_bits.I2C_STOP
782 #define D SSPSTAT_bits.D
783 #define I2C_DATA SSPSTAT_bits.I2C_DATA
784 #define NOT_A SSPSTAT_bits.NOT_A
785 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
786 #define D_A SSPSTAT_bits.D_A
787 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
788 #define CKE SSPSTAT_bits.CKE
789 #define SMP SSPSTAT_bits.SMP
791 // ----- STATUS bits --------------------
797 unsigned char NOT_PD:1;
798 unsigned char NOT_TO:1;
804 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
806 #define C STATUS_bits.C
807 #define DC STATUS_bits.DC
808 #define Z STATUS_bits.Z
809 #define NOT_PD STATUS_bits.NOT_PD
810 #define NOT_TO STATUS_bits.NOT_TO
811 #define RP0 STATUS_bits.RP0
812 #define RP1 STATUS_bits.RP1
813 #define IRP STATUS_bits.IRP
815 // ----- T1CON bits --------------------
818 unsigned char TMR1ON:1;
819 unsigned char TMR1CS:1;
820 unsigned char NOT_T1SYNC:1;
821 unsigned char T1OSCEN:1;
822 unsigned char T1CKPS0:1;
823 unsigned char T1CKPS1:1;
830 unsigned char T1INSYNC:1;
840 unsigned char T1SYNC:1;
848 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
850 #define TMR1ON T1CON_bits.TMR1ON
851 #define TMR1CS T1CON_bits.TMR1CS
852 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
853 #define T1INSYNC T1CON_bits.T1INSYNC
854 #define T1SYNC T1CON_bits.T1SYNC
855 #define T1OSCEN T1CON_bits.T1OSCEN
856 #define T1CKPS0 T1CON_bits.T1CKPS0
857 #define T1CKPS1 T1CON_bits.T1CKPS1
859 // ----- T2CON bits --------------------
862 unsigned char T2CKPS0:1;
863 unsigned char T2CKPS1:1;
864 unsigned char TMR2ON:1;
865 unsigned char TOUTPS0:1;
866 unsigned char TOUTPS1:1;
867 unsigned char TOUTPS2:1;
868 unsigned char TOUTPS3:1;
872 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
874 #define T2CKPS0 T2CON_bits.T2CKPS0
875 #define T2CKPS1 T2CON_bits.T2CKPS1
876 #define TMR2ON T2CON_bits.TMR2ON
877 #define TOUTPS0 T2CON_bits.TOUTPS0
878 #define TOUTPS1 T2CON_bits.TOUTPS1
879 #define TOUTPS2 T2CON_bits.TOUTPS2
880 #define TOUTPS3 T2CON_bits.TOUTPS3
882 // ----- TRISE bits --------------------
885 unsigned char TRISE0:1;
886 unsigned char TRISE1:1;
887 unsigned char TRISE2:1;
889 unsigned char PSPMODE:1;
890 unsigned char IBOV:1;
895 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
897 #define TRISE0 TRISE_bits.TRISE0
898 #define TRISE1 TRISE_bits.TRISE1
899 #define TRISE2 TRISE_bits.TRISE2
900 #define PSPMODE TRISE_bits.PSPMODE
901 #define IBOV TRISE_bits.IBOV
902 #define OBF TRISE_bits.OBF
903 #define IBF TRISE_bits.IBF
905 // ----- TXSTA bits --------------------
908 unsigned char TX9D:1;
909 unsigned char TRMT:1;
910 unsigned char BRGH:1;
912 unsigned char SYNC:1;
913 unsigned char TXEN:1;
915 unsigned char CSRC:1;
918 unsigned char TXD8:1;
924 unsigned char NOT_TX8:1;
934 unsigned char TX8_9:1;
938 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
940 #define TX9D TXSTA_bits.TX9D
941 #define TXD8 TXSTA_bits.TXD8
942 #define TRMT TXSTA_bits.TRMT
943 #define BRGH TXSTA_bits.BRGH
944 #define SYNC TXSTA_bits.SYNC
945 #define TXEN TXSTA_bits.TXEN
946 #define TX9 TXSTA_bits.TX9
947 #define NOT_TX8 TXSTA_bits.NOT_TX8
948 #define TX8_9 TXSTA_bits.TX8_9
949 #define CSRC TXSTA_bits.CSRC