2 // Register Declarations for Microchip 16F873 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define ADRESL_ADDR 0x009E
72 #define ADCON1_ADDR 0x009F
73 #define EEDATA_ADDR 0x010C
74 #define EEADR_ADDR 0x010D
75 #define EEDATH_ADDR 0x010E
76 #define EEADRH_ADDR 0x010F
77 #define EECON1_ADDR 0x018C
78 #define EECON2_ADDR 0x018D
81 // Memory organization.
84 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
85 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
86 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
87 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
88 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
89 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
90 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
91 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
92 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
93 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
94 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
95 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
96 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
97 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
98 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
99 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
100 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
101 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
102 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
103 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
104 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
105 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
106 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
107 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
108 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
109 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
110 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
111 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
112 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
113 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
114 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
115 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
116 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
117 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
118 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
119 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
120 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
121 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
122 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
123 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
124 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
125 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
126 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
127 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
128 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
129 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
130 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
131 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
132 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
133 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
134 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
138 // P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
141 // This header file defines configurations, registers, and other useful bits of
142 // information for the PIC16F873 microcontroller. These names are taken to match
143 // the data sheets as closely as possible.
145 // Note that the processor must be selected before this file is
146 // included. The processor may be selected the following ways:
148 // 1. Command line switch:
149 // C:\ MPASM MYFILE.ASM /PIC16F873
150 // 2. LIST directive in the source file
152 // 3. Processor Type entry in the MPASM full-screen interface
154 //==========================================================================
158 //==========================================================================
162 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
163 // to match datasheet (DS30292B)
164 //1.11 10/18/98 Changes to file registers to match updated DOS
165 //1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1
166 //1.00 08/07/98 Initial Release
168 //==========================================================================
172 //==========================================================================
175 // MESSG "Processor-header file mismatch. Verify selected processor."
178 //==========================================================================
180 // Register Definitions
182 //==========================================================================
187 //----- Register Files------------------------------------------------------
189 extern __data __at (INDF_ADDR) volatile char INDF;
190 extern __sfr __at (TMR0_ADDR) TMR0;
191 extern __data __at (PCL_ADDR) volatile char PCL;
192 extern __sfr __at (STATUS_ADDR) STATUS;
193 extern __sfr __at (FSR_ADDR) FSR;
194 extern __sfr __at (PORTA_ADDR) PORTA;
195 extern __sfr __at (PORTB_ADDR) PORTB;
196 extern __sfr __at (PORTC_ADDR) PORTC;
197 extern __sfr __at (PCLATH_ADDR) PCLATH;
198 extern __sfr __at (INTCON_ADDR) INTCON;
199 extern __sfr __at (PIR1_ADDR) PIR1;
200 extern __sfr __at (PIR2_ADDR) PIR2;
201 extern __sfr __at (TMR1L_ADDR) TMR1L;
202 extern __sfr __at (TMR1H_ADDR) TMR1H;
203 extern __sfr __at (T1CON_ADDR) T1CON;
204 extern __sfr __at (TMR2_ADDR) TMR2;
205 extern __sfr __at (T2CON_ADDR) T2CON;
206 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
207 extern __sfr __at (SSPCON_ADDR) SSPCON;
208 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
209 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
210 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
211 extern __sfr __at (RCSTA_ADDR) RCSTA;
212 extern __sfr __at (TXREG_ADDR) TXREG;
213 extern __sfr __at (RCREG_ADDR) RCREG;
214 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
215 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
216 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
217 extern __sfr __at (ADRESH_ADDR) ADRESH;
218 extern __sfr __at (ADCON0_ADDR) ADCON0;
220 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
221 extern __sfr __at (TRISA_ADDR) TRISA;
222 extern __sfr __at (TRISB_ADDR) TRISB;
223 extern __sfr __at (TRISC_ADDR) TRISC;
224 extern __sfr __at (PIE1_ADDR) PIE1;
225 extern __sfr __at (PIE2_ADDR) PIE2;
226 extern __sfr __at (PCON_ADDR) PCON;
227 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
228 extern __sfr __at (PR2_ADDR) PR2;
229 extern __sfr __at (SSPADD_ADDR) SSPADD;
230 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
231 extern __sfr __at (TXSTA_ADDR) TXSTA;
232 extern __sfr __at (SPBRG_ADDR) SPBRG;
233 extern __sfr __at (ADRESL_ADDR) ADRESL;
234 extern __sfr __at (ADCON1_ADDR) ADCON1;
236 extern __sfr __at (EEDATA_ADDR) EEDATA;
237 extern __sfr __at (EEADR_ADDR) EEADR;
238 extern __sfr __at (EEDATH_ADDR) EEDATH;
239 extern __sfr __at (EEADRH_ADDR) EEADRH;
241 extern __sfr __at (EECON1_ADDR) EECON1;
242 extern __sfr __at (EECON2_ADDR) EECON2;
243 //----- STATUS Bits --------------------------------------------------------
246 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
251 //----- PIR2 Bits ----------------------------------------------------------
254 //----- T1CON Bits ---------------------------------------------------------
257 //----- T2CON Bits ---------------------------------------------------------
260 //----- SSPCON Bits --------------------------------------------------------
263 //----- CCP1CON Bits -------------------------------------------------------
266 //----- RCSTA Bits ---------------------------------------------------------
269 //----- CCP2CON Bits -------------------------------------------------------
272 //----- ADCON0 Bits --------------------------------------------------------
275 //----- OPTION Bits ----------------------------------------------------
278 //----- PIE1 Bits ----------------------------------------------------------
281 //----- PIE2 Bits ----------------------------------------------------------
284 //----- PCON Bits ----------------------------------------------------------
287 //----- SSPCON2 Bits --------------------------------------------------------
290 //----- SSPSTAT Bits -------------------------------------------------------
293 //----- TXSTA Bits ---------------------------------------------------------
296 //----- ADCON1 Bits --------------------------------------------------------
299 //----- EECON1 Bits --------------------------------------------------------
302 //==========================================================================
306 //==========================================================================
309 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
310 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
311 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
313 //==========================================================================
315 // Configuration Bits
317 //==========================================================================
319 #define _CP_ALL 0x0FCF
320 #define _CP_HALF 0x1FDF
321 #define _CP_UPPER_256 0x2FEF
322 #define _CP_OFF 0x3FFF
323 #define _DEBUG_ON 0x37FF
324 #define _DEBUG_OFF 0x3FFF
325 #define _WRT_ENABLE_ON 0x3FFF
326 #define _WRT_ENABLE_OFF 0x3DFF
327 #define _CPD_ON 0x3EFF
328 #define _CPD_OFF 0x3FFF
329 #define _LVP_ON 0x3FFF
330 #define _LVP_OFF 0x3F7F
331 #define _BODEN_ON 0x3FFF
332 #define _BODEN_OFF 0x3FBF
333 #define _PWRTE_OFF 0x3FFF
334 #define _PWRTE_ON 0x3FF7
335 #define _WDT_ON 0x3FFF
336 #define _WDT_OFF 0x3FFB
337 #define _LP_OSC 0x3FFC
338 #define _XT_OSC 0x3FFD
339 #define _HS_OSC 0x3FFE
340 #define _RC_OSC 0x3FFF
344 // ----- ADCON0 bits --------------------
347 unsigned char ADON:1;
350 unsigned char CHS0:1;
351 unsigned char CHS1:1;
352 unsigned char CHS2:1;
353 unsigned char ADCS0:1;
354 unsigned char ADCS1:1;
359 unsigned char NOT_DONE:1;
369 unsigned char GO_DONE:1;
377 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
379 #define ADON ADCON0_bits.ADON
380 #define GO ADCON0_bits.GO
381 #define NOT_DONE ADCON0_bits.NOT_DONE
382 #define GO_DONE ADCON0_bits.GO_DONE
383 #define CHS0 ADCON0_bits.CHS0
384 #define CHS1 ADCON0_bits.CHS1
385 #define CHS2 ADCON0_bits.CHS2
386 #define ADCS0 ADCON0_bits.ADCS0
387 #define ADCS1 ADCON0_bits.ADCS1
389 // ----- ADCON1 bits --------------------
392 unsigned char PCFG0:1;
393 unsigned char PCFG1:1;
394 unsigned char PCFG2:1;
395 unsigned char PCFG3:1;
399 unsigned char ADFM:1;
402 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
404 #define PCFG0 ADCON1_bits.PCFG0
405 #define PCFG1 ADCON1_bits.PCFG1
406 #define PCFG2 ADCON1_bits.PCFG2
407 #define PCFG3 ADCON1_bits.PCFG3
408 #define ADFM ADCON1_bits.ADFM
410 // ----- CCP1CON bits --------------------
413 unsigned char CCP1M0:1;
414 unsigned char CCP1M1:1;
415 unsigned char CCP1M2:1;
416 unsigned char CCP1M3:1;
417 unsigned char CCP1Y:1;
418 unsigned char CCP1X:1;
423 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
425 #define CCP1M0 CCP1CON_bits.CCP1M0
426 #define CCP1M1 CCP1CON_bits.CCP1M1
427 #define CCP1M2 CCP1CON_bits.CCP1M2
428 #define CCP1M3 CCP1CON_bits.CCP1M3
429 #define CCP1Y CCP1CON_bits.CCP1Y
430 #define CCP1X CCP1CON_bits.CCP1X
432 // ----- CCP2CON bits --------------------
435 unsigned char CCP2M0:1;
436 unsigned char CCP2M1:1;
437 unsigned char CCP2M2:1;
438 unsigned char CCP2M3:1;
439 unsigned char CCP2Y:1;
440 unsigned char CCP2X:1;
445 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
447 #define CCP2M0 CCP2CON_bits.CCP2M0
448 #define CCP2M1 CCP2CON_bits.CCP2M1
449 #define CCP2M2 CCP2CON_bits.CCP2M2
450 #define CCP2M3 CCP2CON_bits.CCP2M3
451 #define CCP2Y CCP2CON_bits.CCP2Y
452 #define CCP2X CCP2CON_bits.CCP2X
454 // ----- EECON1 bits --------------------
459 unsigned char WREN:1;
460 unsigned char WRERR:1;
464 unsigned char EEPGD:1;
467 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
469 #define RD EECON1_bits.RD
470 #define WR EECON1_bits.WR
471 #define WREN EECON1_bits.WREN
472 #define WRERR EECON1_bits.WRERR
473 #define EEPGD EECON1_bits.EEPGD
475 // ----- INTCON bits --------------------
478 unsigned char RBIF:1;
479 unsigned char INTF:1;
480 unsigned char T0IF:1;
481 unsigned char RBIE:1;
482 unsigned char INTE:1;
483 unsigned char T0IE:1;
484 unsigned char PEIE:1;
488 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
490 #define RBIF INTCON_bits.RBIF
491 #define INTF INTCON_bits.INTF
492 #define T0IF INTCON_bits.T0IF
493 #define RBIE INTCON_bits.RBIE
494 #define INTE INTCON_bits.INTE
495 #define T0IE INTCON_bits.T0IE
496 #define PEIE INTCON_bits.PEIE
497 #define GIE INTCON_bits.GIE
499 // ----- OPTION_REG bits --------------------
506 unsigned char T0SE:1;
507 unsigned char T0CS:1;
508 unsigned char INTEDG:1;
509 unsigned char NOT_RBPU:1;
511 } __OPTION_REG_bits_t;
512 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
514 #define PS0 OPTION_REG_bits.PS0
515 #define PS1 OPTION_REG_bits.PS1
516 #define PS2 OPTION_REG_bits.PS2
517 #define PSA OPTION_REG_bits.PSA
518 #define T0SE OPTION_REG_bits.T0SE
519 #define T0CS OPTION_REG_bits.T0CS
520 #define INTEDG OPTION_REG_bits.INTEDG
521 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
523 // ----- PCON bits --------------------
526 unsigned char NOT_BO:1;
527 unsigned char NOT_POR:1;
536 unsigned char NOT_BOR:1;
546 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
548 #define NOT_BO PCON_bits.NOT_BO
549 #define NOT_BOR PCON_bits.NOT_BOR
550 #define NOT_POR PCON_bits.NOT_POR
552 // ----- PIE1 bits --------------------
555 unsigned char TMR1IE:1;
556 unsigned char TMR2IE:1;
557 unsigned char CCP1IE:1;
558 unsigned char SSPIE:1;
559 unsigned char TXIE:1;
560 unsigned char RCIE:1;
561 unsigned char ADIE:1;
565 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
567 #define TMR1IE PIE1_bits.TMR1IE
568 #define TMR2IE PIE1_bits.TMR2IE
569 #define CCP1IE PIE1_bits.CCP1IE
570 #define SSPIE PIE1_bits.SSPIE
571 #define TXIE PIE1_bits.TXIE
572 #define RCIE PIE1_bits.RCIE
573 #define ADIE PIE1_bits.ADIE
575 // ----- PIE2 bits --------------------
578 unsigned char CCP2IE:1;
581 unsigned char BCLIE:1;
582 unsigned char EEIE:1;
588 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
590 #define CCP2IE PIE2_bits.CCP2IE
591 #define BCLIE PIE2_bits.BCLIE
592 #define EEIE PIE2_bits.EEIE
594 // ----- PIR1 bits --------------------
597 unsigned char TMR1IF:1;
598 unsigned char TMR2IF:1;
599 unsigned char CCP1IF:1;
600 unsigned char SSPIF:1;
601 unsigned char TXIF:1;
602 unsigned char RCIF:1;
603 unsigned char ADIF:1;
607 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
609 #define TMR1IF PIR1_bits.TMR1IF
610 #define TMR2IF PIR1_bits.TMR2IF
611 #define CCP1IF PIR1_bits.CCP1IF
612 #define SSPIF PIR1_bits.SSPIF
613 #define TXIF PIR1_bits.TXIF
614 #define RCIF PIR1_bits.RCIF
615 #define ADIF PIR1_bits.ADIF
617 // ----- PIR2 bits --------------------
620 unsigned char CCP2IF:1;
623 unsigned char BCLIF:1;
624 unsigned char EEIF:1;
626 unsigned char CMIF:1;
630 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
632 #define CCP2IF PIR2_bits.CCP2IF
633 #define BCLIF PIR2_bits.BCLIF
634 #define EEIF PIR2_bits.EEIF
635 #define CMIF PIR2_bits.CMIF
637 // ----- RCSTA bits --------------------
640 unsigned char RX9D:1;
641 unsigned char OERR:1;
642 unsigned char FERR:1;
643 unsigned char ADDEN:1;
644 unsigned char CREN:1;
645 unsigned char SREN:1;
647 unsigned char SPEN:1;
650 unsigned char RCD8:1;
666 unsigned char NOT_RC8:1;
676 unsigned char RC8_9:1;
680 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
682 #define RX9D RCSTA_bits.RX9D
683 #define RCD8 RCSTA_bits.RCD8
684 #define OERR RCSTA_bits.OERR
685 #define FERR RCSTA_bits.FERR
686 #define ADDEN RCSTA_bits.ADDEN
687 #define CREN RCSTA_bits.CREN
688 #define SREN RCSTA_bits.SREN
689 #define RX9 RCSTA_bits.RX9
690 #define RC9 RCSTA_bits.RC9
691 #define NOT_RC8 RCSTA_bits.NOT_RC8
692 #define RC8_9 RCSTA_bits.RC8_9
693 #define SPEN RCSTA_bits.SPEN
695 // ----- SSPCON bits --------------------
698 unsigned char SSPM0:1;
699 unsigned char SSPM1:1;
700 unsigned char SSPM2:1;
701 unsigned char SSPM3:1;
703 unsigned char SSPEN:1;
704 unsigned char SSPOV:1;
705 unsigned char WCOL:1;
708 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
710 #define SSPM0 SSPCON_bits.SSPM0
711 #define SSPM1 SSPCON_bits.SSPM1
712 #define SSPM2 SSPCON_bits.SSPM2
713 #define SSPM3 SSPCON_bits.SSPM3
714 #define CKP SSPCON_bits.CKP
715 #define SSPEN SSPCON_bits.SSPEN
716 #define SSPOV SSPCON_bits.SSPOV
717 #define WCOL SSPCON_bits.WCOL
719 // ----- SSPCON2 bits --------------------
723 unsigned char RSEN:1;
725 unsigned char RCEN:1;
726 unsigned char ACKEN:1;
727 unsigned char ACKDT:1;
728 unsigned char ACKSTAT:1;
729 unsigned char GCEN:1;
732 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
734 #define SEN SSPCON2_bits.SEN
735 #define RSEN SSPCON2_bits.RSEN
736 #define PEN SSPCON2_bits.PEN
737 #define RCEN SSPCON2_bits.RCEN
738 #define ACKEN SSPCON2_bits.ACKEN
739 #define ACKDT SSPCON2_bits.ACKDT
740 #define ACKSTAT SSPCON2_bits.ACKSTAT
741 #define GCEN SSPCON2_bits.GCEN
743 // ----- SSPSTAT bits --------------------
758 unsigned char I2C_READ:1;
759 unsigned char I2C_START:1;
760 unsigned char I2C_STOP:1;
761 unsigned char I2C_DATA:1;
768 unsigned char NOT_W:1;
771 unsigned char NOT_A:1;
778 unsigned char NOT_WRITE:1;
781 unsigned char NOT_ADDRESS:1;
798 unsigned char READ_WRITE:1;
801 unsigned char DATA_ADDRESS:1;
806 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
808 #define BF SSPSTAT_bits.BF
809 #define UA SSPSTAT_bits.UA
810 #define R SSPSTAT_bits.R
811 #define I2C_READ SSPSTAT_bits.I2C_READ
812 #define NOT_W SSPSTAT_bits.NOT_W
813 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
814 #define R_W SSPSTAT_bits.R_W
815 #define READ_WRITE SSPSTAT_bits.READ_WRITE
816 #define S SSPSTAT_bits.S
817 #define I2C_START SSPSTAT_bits.I2C_START
818 #define P SSPSTAT_bits.P
819 #define I2C_STOP SSPSTAT_bits.I2C_STOP
820 #define D SSPSTAT_bits.D
821 #define I2C_DATA SSPSTAT_bits.I2C_DATA
822 #define NOT_A SSPSTAT_bits.NOT_A
823 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
824 #define D_A SSPSTAT_bits.D_A
825 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
826 #define CKE SSPSTAT_bits.CKE
827 #define SMP SSPSTAT_bits.SMP
829 // ----- STATUS bits --------------------
835 unsigned char NOT_PD:1;
836 unsigned char NOT_TO:1;
842 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
844 #define C STATUS_bits.C
845 #define DC STATUS_bits.DC
846 #define Z STATUS_bits.Z
847 #define NOT_PD STATUS_bits.NOT_PD
848 #define NOT_TO STATUS_bits.NOT_TO
849 #define RP0 STATUS_bits.RP0
850 #define RP1 STATUS_bits.RP1
851 #define IRP STATUS_bits.IRP
853 // ----- T1CON bits --------------------
856 unsigned char TMR1ON:1;
857 unsigned char TMR1CS:1;
858 unsigned char NOT_T1SYNC:1;
859 unsigned char T1OSCEN:1;
860 unsigned char T1CKPS0:1;
861 unsigned char T1CKPS1:1;
868 unsigned char T1INSYNC:1;
878 unsigned char T1SYNC:1;
886 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
888 #define TMR1ON T1CON_bits.TMR1ON
889 #define TMR1CS T1CON_bits.TMR1CS
890 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
891 #define T1INSYNC T1CON_bits.T1INSYNC
892 #define T1SYNC T1CON_bits.T1SYNC
893 #define T1OSCEN T1CON_bits.T1OSCEN
894 #define T1CKPS0 T1CON_bits.T1CKPS0
895 #define T1CKPS1 T1CON_bits.T1CKPS1
897 // ----- T2CON bits --------------------
900 unsigned char T2CKPS0:1;
901 unsigned char T2CKPS1:1;
902 unsigned char TMR2ON:1;
903 unsigned char TOUTPS0:1;
904 unsigned char TOUTPS1:1;
905 unsigned char TOUTPS2:1;
906 unsigned char TOUTPS3:1;
910 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
912 #define T2CKPS0 T2CON_bits.T2CKPS0
913 #define T2CKPS1 T2CON_bits.T2CKPS1
914 #define TMR2ON T2CON_bits.TMR2ON
915 #define TOUTPS0 T2CON_bits.TOUTPS0
916 #define TOUTPS1 T2CON_bits.TOUTPS1
917 #define TOUTPS2 T2CON_bits.TOUTPS2
918 #define TOUTPS3 T2CON_bits.TOUTPS3
920 // ----- TXSTA bits --------------------
923 unsigned char TX9D:1;
924 unsigned char TRMT:1;
925 unsigned char BRGH:1;
927 unsigned char SYNC:1;
928 unsigned char TXEN:1;
930 unsigned char CSRC:1;
933 unsigned char TXD8:1;
939 unsigned char NOT_TX8:1;
949 unsigned char TX8_9:1;
953 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
955 #define TX9D TXSTA_bits.TX9D
956 #define TXD8 TXSTA_bits.TXD8
957 #define TRMT TXSTA_bits.TRMT
958 #define BRGH TXSTA_bits.BRGH
959 #define SYNC TXSTA_bits.SYNC
960 #define TXEN TXSTA_bits.TXEN
961 #define TX9 TXSTA_bits.TX9
962 #define NOT_TX8 TXSTA_bits.NOT_TX8
963 #define TX8_9 TXSTA_bits.TX8_9
964 #define CSRC TXSTA_bits.CSRC