2 // Register Declarations for Microchip 16F873 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define ADRESL_ADDR 0x009E
72 #define ADCON1_ADDR 0x009F
73 #define EEDATA_ADDR 0x010C
74 #define EEADR_ADDR 0x010D
75 #define EEDATH_ADDR 0x010E
76 #define EEADRH_ADDR 0x010F
77 #define EECON1_ADDR 0x018C
78 #define EECON2_ADDR 0x018D
81 // Memory organization.
87 // P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
90 // This header file defines configurations, registers, and other useful bits of
91 // information for the PIC16F873 microcontroller. These names are taken to match
92 // the data sheets as closely as possible.
94 // Note that the processor must be selected before this file is
95 // included. The processor may be selected the following ways:
97 // 1. Command line switch:
98 // C:\ MPASM MYFILE.ASM /PIC16F873
99 // 2. LIST directive in the source file
101 // 3. Processor Type entry in the MPASM full-screen interface
103 //==========================================================================
107 //==========================================================================
111 //1.12 01/12/00 Changed some bit names, a register name, configuration bits
112 // to match datasheet (DS30292B)
113 //1.11 10/18/98 Changes to file registers to match updated DOS
114 //1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1
115 //1.00 08/07/98 Initial Release
117 //==========================================================================
121 //==========================================================================
124 // MESSG "Processor-header file mismatch. Verify selected processor."
127 //==========================================================================
129 // Register Definitions
131 //==========================================================================
136 //----- Register Files------------------------------------------------------
138 extern __data __at (INDF_ADDR) volatile char INDF;
139 extern __sfr __at (TMR0_ADDR) TMR0;
140 extern __data __at (PCL_ADDR) volatile char PCL;
141 extern __sfr __at (STATUS_ADDR) STATUS;
142 extern __sfr __at (FSR_ADDR) FSR;
143 extern __sfr __at (PORTA_ADDR) PORTA;
144 extern __sfr __at (PORTB_ADDR) PORTB;
145 extern __sfr __at (PORTC_ADDR) PORTC;
146 extern __sfr __at (PCLATH_ADDR) PCLATH;
147 extern __sfr __at (INTCON_ADDR) INTCON;
148 extern __sfr __at (PIR1_ADDR) PIR1;
149 extern __sfr __at (PIR2_ADDR) PIR2;
150 extern __sfr __at (TMR1L_ADDR) TMR1L;
151 extern __sfr __at (TMR1H_ADDR) TMR1H;
152 extern __sfr __at (T1CON_ADDR) T1CON;
153 extern __sfr __at (TMR2_ADDR) TMR2;
154 extern __sfr __at (T2CON_ADDR) T2CON;
155 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
156 extern __sfr __at (SSPCON_ADDR) SSPCON;
157 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
158 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
159 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
160 extern __sfr __at (RCSTA_ADDR) RCSTA;
161 extern __sfr __at (TXREG_ADDR) TXREG;
162 extern __sfr __at (RCREG_ADDR) RCREG;
163 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
164 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
165 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
166 extern __sfr __at (ADRESH_ADDR) ADRESH;
167 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
170 extern __sfr __at (TRISA_ADDR) TRISA;
171 extern __sfr __at (TRISB_ADDR) TRISB;
172 extern __sfr __at (TRISC_ADDR) TRISC;
173 extern __sfr __at (PIE1_ADDR) PIE1;
174 extern __sfr __at (PIE2_ADDR) PIE2;
175 extern __sfr __at (PCON_ADDR) PCON;
176 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
177 extern __sfr __at (PR2_ADDR) PR2;
178 extern __sfr __at (SSPADD_ADDR) SSPADD;
179 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
180 extern __sfr __at (TXSTA_ADDR) TXSTA;
181 extern __sfr __at (SPBRG_ADDR) SPBRG;
182 extern __sfr __at (ADRESL_ADDR) ADRESL;
183 extern __sfr __at (ADCON1_ADDR) ADCON1;
185 extern __sfr __at (EEDATA_ADDR) EEDATA;
186 extern __sfr __at (EEADR_ADDR) EEADR;
187 extern __sfr __at (EEDATH_ADDR) EEDATH;
188 extern __sfr __at (EEADRH_ADDR) EEADRH;
190 extern __sfr __at (EECON1_ADDR) EECON1;
191 extern __sfr __at (EECON2_ADDR) EECON2;
192 //----- STATUS Bits --------------------------------------------------------
195 //----- INTCON Bits --------------------------------------------------------
198 //----- PIR1 Bits ----------------------------------------------------------
200 //----- PIR2 Bits ----------------------------------------------------------
203 //----- T1CON Bits ---------------------------------------------------------
206 //----- T2CON Bits ---------------------------------------------------------
209 //----- SSPCON Bits --------------------------------------------------------
212 //----- CCP1CON Bits -------------------------------------------------------
215 //----- RCSTA Bits ---------------------------------------------------------
218 //----- CCP2CON Bits -------------------------------------------------------
221 //----- ADCON0 Bits --------------------------------------------------------
224 //----- OPTION Bits ----------------------------------------------------
227 //----- PIE1 Bits ----------------------------------------------------------
230 //----- PIE2 Bits ----------------------------------------------------------
233 //----- PCON Bits ----------------------------------------------------------
236 //----- SSPCON2 Bits --------------------------------------------------------
239 //----- SSPSTAT Bits -------------------------------------------------------
242 //----- TXSTA Bits ---------------------------------------------------------
245 //----- ADCON1 Bits --------------------------------------------------------
248 //----- EECON1 Bits --------------------------------------------------------
251 //==========================================================================
255 //==========================================================================
258 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D'
259 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
260 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
262 //==========================================================================
264 // Configuration Bits
266 //==========================================================================
268 #define _CP_ALL 0x0FCF
269 #define _CP_HALF 0x1FDF
270 #define _CP_UPPER_256 0x2FEF
271 #define _CP_OFF 0x3FFF
272 #define _DEBUG_ON 0x37FF
273 #define _DEBUG_OFF 0x3FFF
274 #define _WRT_ENABLE_ON 0x3FFF
275 #define _WRT_ENABLE_OFF 0x3DFF
276 #define _CPD_ON 0x3EFF
277 #define _CPD_OFF 0x3FFF
278 #define _LVP_ON 0x3FFF
279 #define _LVP_OFF 0x3F7F
280 #define _BODEN_ON 0x3FFF
281 #define _BODEN_OFF 0x3FBF
282 #define _PWRTE_OFF 0x3FFF
283 #define _PWRTE_ON 0x3FF7
284 #define _WDT_ON 0x3FFF
285 #define _WDT_OFF 0x3FFB
286 #define _LP_OSC 0x3FFC
287 #define _XT_OSC 0x3FFD
288 #define _HS_OSC 0x3FFE
289 #define _RC_OSC 0x3FFF
293 // ----- ADCON0 bits --------------------
296 unsigned char ADON:1;
299 unsigned char CHS0:1;
300 unsigned char CHS1:1;
301 unsigned char CHS2:1;
302 unsigned char ADCS0:1;
303 unsigned char ADCS1:1;
308 unsigned char NOT_DONE:1;
318 unsigned char GO_DONE:1;
326 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
328 #define ADON ADCON0_bits.ADON
329 #define GO ADCON0_bits.GO
330 #define NOT_DONE ADCON0_bits.NOT_DONE
331 #define GO_DONE ADCON0_bits.GO_DONE
332 #define CHS0 ADCON0_bits.CHS0
333 #define CHS1 ADCON0_bits.CHS1
334 #define CHS2 ADCON0_bits.CHS2
335 #define ADCS0 ADCON0_bits.ADCS0
336 #define ADCS1 ADCON0_bits.ADCS1
338 // ----- ADCON1 bits --------------------
341 unsigned char PCFG0:1;
342 unsigned char PCFG1:1;
343 unsigned char PCFG2:1;
344 unsigned char PCFG3:1;
348 unsigned char ADFM:1;
351 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
353 #define PCFG0 ADCON1_bits.PCFG0
354 #define PCFG1 ADCON1_bits.PCFG1
355 #define PCFG2 ADCON1_bits.PCFG2
356 #define PCFG3 ADCON1_bits.PCFG3
357 #define ADFM ADCON1_bits.ADFM
359 // ----- CCP1CON bits --------------------
362 unsigned char CCP1M0:1;
363 unsigned char CCP1M1:1;
364 unsigned char CCP1M2:1;
365 unsigned char CCP1M3:1;
366 unsigned char CCP1Y:1;
367 unsigned char CCP1X:1;
372 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
374 #define CCP1M0 CCP1CON_bits.CCP1M0
375 #define CCP1M1 CCP1CON_bits.CCP1M1
376 #define CCP1M2 CCP1CON_bits.CCP1M2
377 #define CCP1M3 CCP1CON_bits.CCP1M3
378 #define CCP1Y CCP1CON_bits.CCP1Y
379 #define CCP1X CCP1CON_bits.CCP1X
381 // ----- CCP2CON bits --------------------
384 unsigned char CCP2M0:1;
385 unsigned char CCP2M1:1;
386 unsigned char CCP2M2:1;
387 unsigned char CCP2M3:1;
388 unsigned char CCP2Y:1;
389 unsigned char CCP2X:1;
394 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
396 #define CCP2M0 CCP2CON_bits.CCP2M0
397 #define CCP2M1 CCP2CON_bits.CCP2M1
398 #define CCP2M2 CCP2CON_bits.CCP2M2
399 #define CCP2M3 CCP2CON_bits.CCP2M3
400 #define CCP2Y CCP2CON_bits.CCP2Y
401 #define CCP2X CCP2CON_bits.CCP2X
403 // ----- EECON1 bits --------------------
408 unsigned char WREN:1;
409 unsigned char WRERR:1;
413 unsigned char EEPGD:1;
416 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
418 #define RD EECON1_bits.RD
419 #define WR EECON1_bits.WR
420 #define WREN EECON1_bits.WREN
421 #define WRERR EECON1_bits.WRERR
422 #define EEPGD EECON1_bits.EEPGD
424 // ----- INTCON bits --------------------
427 unsigned char RBIF:1;
428 unsigned char INTF:1;
429 unsigned char T0IF:1;
430 unsigned char RBIE:1;
431 unsigned char INTE:1;
432 unsigned char T0IE:1;
433 unsigned char PEIE:1;
437 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
439 #define RBIF INTCON_bits.RBIF
440 #define INTF INTCON_bits.INTF
441 #define T0IF INTCON_bits.T0IF
442 #define RBIE INTCON_bits.RBIE
443 #define INTE INTCON_bits.INTE
444 #define T0IE INTCON_bits.T0IE
445 #define PEIE INTCON_bits.PEIE
446 #define GIE INTCON_bits.GIE
448 // ----- OPTION_REG bits --------------------
455 unsigned char T0SE:1;
456 unsigned char T0CS:1;
457 unsigned char INTEDG:1;
458 unsigned char NOT_RBPU:1;
460 } __OPTION_REG_bits_t;
461 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
463 #define PS0 OPTION_REG_bits.PS0
464 #define PS1 OPTION_REG_bits.PS1
465 #define PS2 OPTION_REG_bits.PS2
466 #define PSA OPTION_REG_bits.PSA
467 #define T0SE OPTION_REG_bits.T0SE
468 #define T0CS OPTION_REG_bits.T0CS
469 #define INTEDG OPTION_REG_bits.INTEDG
470 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
472 // ----- PCON bits --------------------
475 unsigned char NOT_BO:1;
476 unsigned char NOT_POR:1;
485 unsigned char NOT_BOR:1;
495 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
497 #define NOT_BO PCON_bits.NOT_BO
498 #define NOT_BOR PCON_bits.NOT_BOR
499 #define NOT_POR PCON_bits.NOT_POR
501 // ----- PIE1 bits --------------------
504 unsigned char TMR1IE:1;
505 unsigned char TMR2IE:1;
506 unsigned char CCP1IE:1;
507 unsigned char SSPIE:1;
508 unsigned char TXIE:1;
509 unsigned char RCIE:1;
510 unsigned char ADIE:1;
514 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
516 #define TMR1IE PIE1_bits.TMR1IE
517 #define TMR2IE PIE1_bits.TMR2IE
518 #define CCP1IE PIE1_bits.CCP1IE
519 #define SSPIE PIE1_bits.SSPIE
520 #define TXIE PIE1_bits.TXIE
521 #define RCIE PIE1_bits.RCIE
522 #define ADIE PIE1_bits.ADIE
524 // ----- PIE2 bits --------------------
527 unsigned char CCP2IE:1;
530 unsigned char BCLIE:1;
531 unsigned char EEIE:1;
537 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
539 #define CCP2IE PIE2_bits.CCP2IE
540 #define BCLIE PIE2_bits.BCLIE
541 #define EEIE PIE2_bits.EEIE
543 // ----- PIR1 bits --------------------
546 unsigned char TMR1IF:1;
547 unsigned char TMR2IF:1;
548 unsigned char CCP1IF:1;
549 unsigned char SSPIF:1;
550 unsigned char TXIF:1;
551 unsigned char RCIF:1;
552 unsigned char ADIF:1;
556 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
558 #define TMR1IF PIR1_bits.TMR1IF
559 #define TMR2IF PIR1_bits.TMR2IF
560 #define CCP1IF PIR1_bits.CCP1IF
561 #define SSPIF PIR1_bits.SSPIF
562 #define TXIF PIR1_bits.TXIF
563 #define RCIF PIR1_bits.RCIF
564 #define ADIF PIR1_bits.ADIF
566 // ----- PIR2 bits --------------------
569 unsigned char CCP2IF:1;
572 unsigned char BCLIF:1;
573 unsigned char EEIF:1;
575 unsigned char CMIF:1;
579 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
581 #define CCP2IF PIR2_bits.CCP2IF
582 #define BCLIF PIR2_bits.BCLIF
583 #define EEIF PIR2_bits.EEIF
584 #define CMIF PIR2_bits.CMIF
586 // ----- RCSTA bits --------------------
589 unsigned char RX9D:1;
590 unsigned char OERR:1;
591 unsigned char FERR:1;
592 unsigned char ADDEN:1;
593 unsigned char CREN:1;
594 unsigned char SREN:1;
596 unsigned char SPEN:1;
599 unsigned char RCD8:1;
615 unsigned char NOT_RC8:1;
625 unsigned char RC8_9:1;
629 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
631 #define RX9D RCSTA_bits.RX9D
632 #define RCD8 RCSTA_bits.RCD8
633 #define OERR RCSTA_bits.OERR
634 #define FERR RCSTA_bits.FERR
635 #define ADDEN RCSTA_bits.ADDEN
636 #define CREN RCSTA_bits.CREN
637 #define SREN RCSTA_bits.SREN
638 #define RX9 RCSTA_bits.RX9
639 #define RC9 RCSTA_bits.RC9
640 #define NOT_RC8 RCSTA_bits.NOT_RC8
641 #define RC8_9 RCSTA_bits.RC8_9
642 #define SPEN RCSTA_bits.SPEN
644 // ----- SSPCON bits --------------------
647 unsigned char SSPM0:1;
648 unsigned char SSPM1:1;
649 unsigned char SSPM2:1;
650 unsigned char SSPM3:1;
652 unsigned char SSPEN:1;
653 unsigned char SSPOV:1;
654 unsigned char WCOL:1;
657 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
659 #define SSPM0 SSPCON_bits.SSPM0
660 #define SSPM1 SSPCON_bits.SSPM1
661 #define SSPM2 SSPCON_bits.SSPM2
662 #define SSPM3 SSPCON_bits.SSPM3
663 #define CKP SSPCON_bits.CKP
664 #define SSPEN SSPCON_bits.SSPEN
665 #define SSPOV SSPCON_bits.SSPOV
666 #define WCOL SSPCON_bits.WCOL
668 // ----- SSPCON2 bits --------------------
672 unsigned char RSEN:1;
674 unsigned char RCEN:1;
675 unsigned char ACKEN:1;
676 unsigned char ACKDT:1;
677 unsigned char ACKSTAT:1;
678 unsigned char GCEN:1;
681 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
683 #define SEN SSPCON2_bits.SEN
684 #define RSEN SSPCON2_bits.RSEN
685 #define PEN SSPCON2_bits.PEN
686 #define RCEN SSPCON2_bits.RCEN
687 #define ACKEN SSPCON2_bits.ACKEN
688 #define ACKDT SSPCON2_bits.ACKDT
689 #define ACKSTAT SSPCON2_bits.ACKSTAT
690 #define GCEN SSPCON2_bits.GCEN
692 // ----- SSPSTAT bits --------------------
707 unsigned char I2C_READ:1;
708 unsigned char I2C_START:1;
709 unsigned char I2C_STOP:1;
710 unsigned char I2C_DATA:1;
717 unsigned char NOT_W:1;
720 unsigned char NOT_A:1;
727 unsigned char NOT_WRITE:1;
730 unsigned char NOT_ADDRESS:1;
747 unsigned char READ_WRITE:1;
750 unsigned char DATA_ADDRESS:1;
755 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
757 #define BF SSPSTAT_bits.BF
758 #define UA SSPSTAT_bits.UA
759 #define R SSPSTAT_bits.R
760 #define I2C_READ SSPSTAT_bits.I2C_READ
761 #define NOT_W SSPSTAT_bits.NOT_W
762 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
763 #define R_W SSPSTAT_bits.R_W
764 #define READ_WRITE SSPSTAT_bits.READ_WRITE
765 #define S SSPSTAT_bits.S
766 #define I2C_START SSPSTAT_bits.I2C_START
767 #define P SSPSTAT_bits.P
768 #define I2C_STOP SSPSTAT_bits.I2C_STOP
769 #define D SSPSTAT_bits.D
770 #define I2C_DATA SSPSTAT_bits.I2C_DATA
771 #define NOT_A SSPSTAT_bits.NOT_A
772 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
773 #define D_A SSPSTAT_bits.D_A
774 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
775 #define CKE SSPSTAT_bits.CKE
776 #define SMP SSPSTAT_bits.SMP
778 // ----- STATUS bits --------------------
784 unsigned char NOT_PD:1;
785 unsigned char NOT_TO:1;
791 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
793 #define C STATUS_bits.C
794 #define DC STATUS_bits.DC
795 #define Z STATUS_bits.Z
796 #define NOT_PD STATUS_bits.NOT_PD
797 #define NOT_TO STATUS_bits.NOT_TO
798 #define RP0 STATUS_bits.RP0
799 #define RP1 STATUS_bits.RP1
800 #define IRP STATUS_bits.IRP
802 // ----- T1CON bits --------------------
805 unsigned char TMR1ON:1;
806 unsigned char TMR1CS:1;
807 unsigned char NOT_T1SYNC:1;
808 unsigned char T1OSCEN:1;
809 unsigned char T1CKPS0:1;
810 unsigned char T1CKPS1:1;
817 unsigned char T1INSYNC:1;
827 unsigned char T1SYNC:1;
835 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
837 #define TMR1ON T1CON_bits.TMR1ON
838 #define TMR1CS T1CON_bits.TMR1CS
839 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
840 #define T1INSYNC T1CON_bits.T1INSYNC
841 #define T1SYNC T1CON_bits.T1SYNC
842 #define T1OSCEN T1CON_bits.T1OSCEN
843 #define T1CKPS0 T1CON_bits.T1CKPS0
844 #define T1CKPS1 T1CON_bits.T1CKPS1
846 // ----- T2CON bits --------------------
849 unsigned char T2CKPS0:1;
850 unsigned char T2CKPS1:1;
851 unsigned char TMR2ON:1;
852 unsigned char TOUTPS0:1;
853 unsigned char TOUTPS1:1;
854 unsigned char TOUTPS2:1;
855 unsigned char TOUTPS3:1;
859 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
861 #define T2CKPS0 T2CON_bits.T2CKPS0
862 #define T2CKPS1 T2CON_bits.T2CKPS1
863 #define TMR2ON T2CON_bits.TMR2ON
864 #define TOUTPS0 T2CON_bits.TOUTPS0
865 #define TOUTPS1 T2CON_bits.TOUTPS1
866 #define TOUTPS2 T2CON_bits.TOUTPS2
867 #define TOUTPS3 T2CON_bits.TOUTPS3
869 // ----- TXSTA bits --------------------
872 unsigned char TX9D:1;
873 unsigned char TRMT:1;
874 unsigned char BRGH:1;
876 unsigned char SYNC:1;
877 unsigned char TXEN:1;
879 unsigned char CSRC:1;
882 unsigned char TXD8:1;
888 unsigned char NOT_TX8:1;
898 unsigned char TX8_9:1;
902 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
904 #define TX9D TXSTA_bits.TX9D
905 #define TXD8 TXSTA_bits.TXD8
906 #define TRMT TXSTA_bits.TRMT
907 #define BRGH TXSTA_bits.BRGH
908 #define SYNC TXSTA_bits.SYNC
909 #define TXEN TXSTA_bits.TXEN
910 #define TX9 TXSTA_bits.TX9
911 #define NOT_TX8 TXSTA_bits.NOT_TX8
912 #define TX8_9 TXSTA_bits.TX8_9
913 #define CSRC TXSTA_bits.CSRC