2 // Register Declarations for Microchip 16F872 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define SSPCON2_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define SSPADD_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define ADRESL_ADDR 0x009E
64 #define ADCON1_ADDR 0x009F
65 #define EEDATA_ADDR 0x010C
66 #define EEADR_ADDR 0x010D
67 #define EEDATH_ADDR 0x010E
68 #define EEADRH_ADDR 0x010F
69 #define EECON1_ADDR 0x018C
70 #define EECON2_ADDR 0x018D
73 // Memory organization.
76 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
77 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
78 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
79 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
80 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
81 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
82 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
83 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
84 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
85 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
86 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
87 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
88 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
89 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
90 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
91 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
92 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
93 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
94 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
95 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
96 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
97 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
98 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
99 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
100 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
101 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
102 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
103 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
104 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
105 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
106 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
107 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
108 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
109 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
110 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
111 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
112 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
113 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
114 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
115 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
116 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
117 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
118 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
122 // P16F872.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
125 // This header file defines configurations, registers, and other useful bits of
126 // information for the PIC16F872 microcontroller. These names are taken to match
127 // the data sheets as closely as possible.
129 // Note that the processor must be selected before this file is
130 // included. The processor may be selected the following ways:
132 // 1. Command line switch:
133 // C:\ MPASM MYFILE.ASM /PIC16F872
134 // 2. LIST directive in the source file
136 // 3. Processor Type entry in the MPASM full-screen interface
138 //==========================================================================
142 //==========================================================================
146 //1.00 01/25/98 Initial Release
148 //==========================================================================
152 //==========================================================================
155 // MESSG "Processor-header file mismatch. Verify selected processor."
158 //==========================================================================
160 // Register Definitions
162 //==========================================================================
167 //----- Register Files------------------------------------------------------
169 extern __data __at (INDF_ADDR) volatile char INDF;
170 extern __sfr __at (TMR0_ADDR) TMR0;
171 extern __data __at (PCL_ADDR) volatile char PCL;
172 extern __sfr __at (STATUS_ADDR) STATUS;
173 extern __sfr __at (FSR_ADDR) FSR;
174 extern __sfr __at (PORTA_ADDR) PORTA;
175 extern __sfr __at (PORTB_ADDR) PORTB;
176 extern __sfr __at (PORTC_ADDR) PORTC;
177 extern __sfr __at (PCLATH_ADDR) PCLATH;
178 extern __sfr __at (INTCON_ADDR) INTCON;
179 extern __sfr __at (PIR1_ADDR) PIR1;
180 extern __sfr __at (PIR2_ADDR) PIR2;
181 extern __sfr __at (TMR1L_ADDR) TMR1L;
182 extern __sfr __at (TMR1H_ADDR) TMR1H;
183 extern __sfr __at (T1CON_ADDR) T1CON;
184 extern __sfr __at (TMR2_ADDR) TMR2;
185 extern __sfr __at (T2CON_ADDR) T2CON;
186 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
187 extern __sfr __at (SSPCON_ADDR) SSPCON;
188 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
189 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
190 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
191 extern __sfr __at (ADRESH_ADDR) ADRESH;
192 extern __sfr __at (ADCON0_ADDR) ADCON0;
194 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
195 extern __sfr __at (TRISA_ADDR) TRISA;
196 extern __sfr __at (TRISB_ADDR) TRISB;
197 extern __sfr __at (TRISC_ADDR) TRISC;
198 extern __sfr __at (PIE1_ADDR) PIE1;
199 extern __sfr __at (PIE2_ADDR) PIE2;
200 extern __sfr __at (PCON_ADDR) PCON;
201 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
202 extern __sfr __at (PR2_ADDR) PR2;
203 extern __sfr __at (SSPADD_ADDR) SSPADD;
204 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
205 extern __sfr __at (ADRESL_ADDR) ADRESL;
206 extern __sfr __at (ADCON1_ADDR) ADCON1;
208 extern __sfr __at (EEDATA_ADDR) EEDATA;
209 extern __sfr __at (EEADR_ADDR) EEADR;
210 extern __sfr __at (EEDATH_ADDR) EEDATH;
211 extern __sfr __at (EEADRH_ADDR) EEADRH;
213 extern __sfr __at (EECON1_ADDR) EECON1;
214 extern __sfr __at (EECON2_ADDR) EECON2;
216 //----- STATUS Bits --------------------------------------------------------
219 //----- INTCON Bits --------------------------------------------------------
222 //----- PIR1 Bits ----------------------------------------------------------
225 //----- PIR2 Bits ----------------------------------------------------------
228 //----- T1CON Bits ---------------------------------------------------------
231 //----- T2CON Bits ---------------------------------------------------------
234 //----- SSPCON Bits --------------------------------------------------------
237 //----- CCP1CON Bits -------------------------------------------------------
240 //----- ADCON0 Bits --------------------------------------------------------
243 //----- OPTION Bits -----------------------------------------------------
246 //----- PIE1 Bits ----------------------------------------------------------
249 //----- PIE2 Bits ----------------------------------------------------------
252 //----- PCON Bits ----------------------------------------------------------
255 //----- SSPCON2 Bits --------------------------------------------------------
258 //----- SSPSTAT Bits -------------------------------------------------------
261 //----- ADCON1 Bits --------------------------------------------------------
264 //----- EECON1 Bits --------------------------------------------------------
267 //==========================================================================
271 //==========================================================================
274 // __BADRAM H'008'-H'009', H'018'-H'01D', H'088'-H'089'
275 // __BADRAM H'08F'-H'090', H'095'-H'09D', H'0C0'-H'0EF'
276 // __BADRAM H'105', H'107'-H'109'
277 // __BADRAM H'110'-H'11F', H'185'
278 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F',H'1C0'-H'1EF'
280 //==========================================================================
282 // Configuration Bits
284 // Code protection for the PIC16C872 is different than for other PIC16C87X devices.
285 // The CP_ALL and CP_OFF switches operate as expected.
286 // CP_HALF protects the lower half of program memory. The upper half is open.
287 // CP_UPPER_256 protects everything EXCEPT the top 256 words.
288 //==========================================================================
290 #define _CP_ALL 0x0FCF
291 #define _CP_HALF 0x1FDF
292 #define _CP_UPPER_256 0x2FEF
293 #define _CP_OFF 0x3FFF
294 #define _DEBUG_ON 0x37FF
295 #define _DEBUG_OFF 0x3FFF
296 #define _WRT_ENABLE_ON 0x3FFF
297 #define _WRT_ENABLE_OFF 0x3DFF
298 #define _CPD_ON 0x3EFF
299 #define _CPD_OFF 0x3FFF
300 #define _LVP_ON 0x3FFF
301 #define _LVP_OFF 0x3F7F
302 #define _BODEN_ON 0x3FFF
303 #define _BODEN_OFF 0x3FBF
304 #define _PWRTE_OFF 0x3FFF
305 #define _PWRTE_ON 0x3FF7
306 #define _WDT_ON 0x3FFF
307 #define _WDT_OFF 0x3FFB
308 #define _LP_OSC 0x3FFC
309 #define _XT_OSC 0x3FFD
310 #define _HS_OSC 0x3FFE
311 #define _RC_OSC 0x3FFF
315 // ----- ADCON0 bits --------------------
318 unsigned char ADON:1;
321 unsigned char CHS0:1;
322 unsigned char CHS1:1;
323 unsigned char CHS2:1;
324 unsigned char ADCS0:1;
325 unsigned char ADCS1:1;
330 unsigned char NOT_DONE:1;
340 unsigned char GO_DONE:1;
348 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
350 #define ADON ADCON0_bits.ADON
351 #define GO ADCON0_bits.GO
352 #define NOT_DONE ADCON0_bits.NOT_DONE
353 #define GO_DONE ADCON0_bits.GO_DONE
354 #define CHS0 ADCON0_bits.CHS0
355 #define CHS1 ADCON0_bits.CHS1
356 #define CHS2 ADCON0_bits.CHS2
357 #define ADCS0 ADCON0_bits.ADCS0
358 #define ADCS1 ADCON0_bits.ADCS1
360 // ----- ADCON1 bits --------------------
363 unsigned char PCFG0:1;
364 unsigned char PCFG1:1;
365 unsigned char PCFG2:1;
366 unsigned char PCFG3:1;
370 unsigned char ADFM:1;
373 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
375 #define PCFG0 ADCON1_bits.PCFG0
376 #define PCFG1 ADCON1_bits.PCFG1
377 #define PCFG2 ADCON1_bits.PCFG2
378 #define PCFG3 ADCON1_bits.PCFG3
379 #define ADFM ADCON1_bits.ADFM
381 // ----- CCP1CON bits --------------------
384 unsigned char CCP1M0:1;
385 unsigned char CCP1M1:1;
386 unsigned char CCP1M2:1;
387 unsigned char CCP1M3:1;
388 unsigned char CCP1Y:1;
389 unsigned char CCP1X:1;
394 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
396 #define CCP1M0 CCP1CON_bits.CCP1M0
397 #define CCP1M1 CCP1CON_bits.CCP1M1
398 #define CCP1M2 CCP1CON_bits.CCP1M2
399 #define CCP1M3 CCP1CON_bits.CCP1M3
400 #define CCP1Y CCP1CON_bits.CCP1Y
401 #define CCP1X CCP1CON_bits.CCP1X
403 // ----- EECON1 bits --------------------
408 unsigned char WREN:1;
409 unsigned char WRERR:1;
413 unsigned char EEPGD:1;
416 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
418 #define RD EECON1_bits.RD
419 #define WR EECON1_bits.WR
420 #define WREN EECON1_bits.WREN
421 #define WRERR EECON1_bits.WRERR
422 #define EEPGD EECON1_bits.EEPGD
424 // ----- INTCON bits --------------------
427 unsigned char RBIF:1;
428 unsigned char INTF:1;
429 unsigned char T0IF:1;
430 unsigned char RBIE:1;
431 unsigned char INTE:1;
432 unsigned char T0IE:1;
433 unsigned char PEIE:1;
437 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
439 #define RBIF INTCON_bits.RBIF
440 #define INTF INTCON_bits.INTF
441 #define T0IF INTCON_bits.T0IF
442 #define RBIE INTCON_bits.RBIE
443 #define INTE INTCON_bits.INTE
444 #define T0IE INTCON_bits.T0IE
445 #define PEIE INTCON_bits.PEIE
446 #define GIE INTCON_bits.GIE
448 // ----- OPTION_REG bits --------------------
455 unsigned char T0SE:1;
456 unsigned char T0CS:1;
457 unsigned char INTEDG:1;
458 unsigned char NOT_RBPU:1;
460 } __OPTION_REG_bits_t;
461 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
463 #define PS0 OPTION_REG_bits.PS0
464 #define PS1 OPTION_REG_bits.PS1
465 #define PS2 OPTION_REG_bits.PS2
466 #define PSA OPTION_REG_bits.PSA
467 #define T0SE OPTION_REG_bits.T0SE
468 #define T0CS OPTION_REG_bits.T0CS
469 #define INTEDG OPTION_REG_bits.INTEDG
470 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
472 // ----- PCON bits --------------------
475 unsigned char NOT_BO:1;
476 unsigned char NOT_POR:1;
485 unsigned char NOT_BOR:1;
495 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
497 #define NOT_BO PCON_bits.NOT_BO
498 #define NOT_BOR PCON_bits.NOT_BOR
499 #define NOT_POR PCON_bits.NOT_POR
501 // ----- PIE1 bits --------------------
504 unsigned char TMR1IE:1;
505 unsigned char TMR2IE:1;
506 unsigned char CCP1IE:1;
507 unsigned char SSPIE:1;
510 unsigned char ADIE:1;
514 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
516 #define TMR1IE PIE1_bits.TMR1IE
517 #define TMR2IE PIE1_bits.TMR2IE
518 #define CCP1IE PIE1_bits.CCP1IE
519 #define SSPIE PIE1_bits.SSPIE
520 #define ADIE PIE1_bits.ADIE
522 // ----- PIE2 bits --------------------
528 unsigned char BCLIE:1;
529 unsigned char EEIE:1;
535 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
537 #define BCLIE PIE2_bits.BCLIE
538 #define EEIE PIE2_bits.EEIE
540 // ----- PIR1 bits --------------------
543 unsigned char TMR1IF:1;
544 unsigned char TMR2IF:1;
545 unsigned char CCP1IF:1;
546 unsigned char SSPIF:1;
549 unsigned char ADIF:1;
553 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
555 #define TMR1IF PIR1_bits.TMR1IF
556 #define TMR2IF PIR1_bits.TMR2IF
557 #define CCP1IF PIR1_bits.CCP1IF
558 #define SSPIF PIR1_bits.SSPIF
559 #define ADIF PIR1_bits.ADIF
561 // ----- PIR2 bits --------------------
567 unsigned char BCLIF:1;
568 unsigned char EEIF:1;
574 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
576 #define BCLIF PIR2_bits.BCLIF
577 #define EEIF PIR2_bits.EEIF
579 // ----- SSPCON bits --------------------
582 unsigned char SSPM0:1;
583 unsigned char SSPM1:1;
584 unsigned char SSPM2:1;
585 unsigned char SSPM3:1;
587 unsigned char SSPEN:1;
588 unsigned char SSPOV:1;
589 unsigned char WCOL:1;
592 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
594 #define SSPM0 SSPCON_bits.SSPM0
595 #define SSPM1 SSPCON_bits.SSPM1
596 #define SSPM2 SSPCON_bits.SSPM2
597 #define SSPM3 SSPCON_bits.SSPM3
598 #define CKP SSPCON_bits.CKP
599 #define SSPEN SSPCON_bits.SSPEN
600 #define SSPOV SSPCON_bits.SSPOV
601 #define WCOL SSPCON_bits.WCOL
603 // ----- SSPCON2 bits --------------------
607 unsigned char RSEN:1;
609 unsigned char RCEN:1;
610 unsigned char ACKEN:1;
611 unsigned char ACKDT:1;
612 unsigned char ACKSTAT:1;
613 unsigned char GCEN:1;
616 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
618 #define SEN SSPCON2_bits.SEN
619 #define RSEN SSPCON2_bits.RSEN
620 #define PEN SSPCON2_bits.PEN
621 #define RCEN SSPCON2_bits.RCEN
622 #define ACKEN SSPCON2_bits.ACKEN
623 #define ACKDT SSPCON2_bits.ACKDT
624 #define ACKSTAT SSPCON2_bits.ACKSTAT
625 #define GCEN SSPCON2_bits.GCEN
627 // ----- SSPSTAT bits --------------------
642 unsigned char I2C_READ:1;
643 unsigned char I2C_START:1;
644 unsigned char I2C_STOP:1;
645 unsigned char I2C_DATA:1;
652 unsigned char NOT_W:1;
655 unsigned char NOT_A:1;
662 unsigned char NOT_WRITE:1;
665 unsigned char NOT_ADDRESS:1;
682 unsigned char READ_WRITE:1;
685 unsigned char DATA_ADDRESS:1;
690 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
692 #define BF SSPSTAT_bits.BF
693 #define UA SSPSTAT_bits.UA
694 #define R SSPSTAT_bits.R
695 #define I2C_READ SSPSTAT_bits.I2C_READ
696 #define NOT_W SSPSTAT_bits.NOT_W
697 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
698 #define R_W SSPSTAT_bits.R_W
699 #define READ_WRITE SSPSTAT_bits.READ_WRITE
700 #define S SSPSTAT_bits.S
701 #define I2C_START SSPSTAT_bits.I2C_START
702 #define P SSPSTAT_bits.P
703 #define I2C_STOP SSPSTAT_bits.I2C_STOP
704 #define D SSPSTAT_bits.D
705 #define I2C_DATA SSPSTAT_bits.I2C_DATA
706 #define NOT_A SSPSTAT_bits.NOT_A
707 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
708 #define D_A SSPSTAT_bits.D_A
709 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
710 #define CKE SSPSTAT_bits.CKE
711 #define SMP SSPSTAT_bits.SMP
713 // ----- STATUS bits --------------------
719 unsigned char NOT_PD:1;
720 unsigned char NOT_TO:1;
726 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
728 #define C STATUS_bits.C
729 #define DC STATUS_bits.DC
730 #define Z STATUS_bits.Z
731 #define NOT_PD STATUS_bits.NOT_PD
732 #define NOT_TO STATUS_bits.NOT_TO
733 #define RP0 STATUS_bits.RP0
734 #define RP1 STATUS_bits.RP1
735 #define IRP STATUS_bits.IRP
737 // ----- T1CON bits --------------------
740 unsigned char TMR1ON:1;
741 unsigned char TMR1CS:1;
742 unsigned char NOT_T1SYNC:1;
743 unsigned char T1OSCEN:1;
744 unsigned char T1CKPS0:1;
745 unsigned char T1CKPS1:1;
752 unsigned char T1INSYNC:1;
762 unsigned char T1SYNC:1;
770 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
772 #define TMR1ON T1CON_bits.TMR1ON
773 #define TMR1CS T1CON_bits.TMR1CS
774 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
775 #define T1INSYNC T1CON_bits.T1INSYNC
776 #define T1SYNC T1CON_bits.T1SYNC
777 #define T1OSCEN T1CON_bits.T1OSCEN
778 #define T1CKPS0 T1CON_bits.T1CKPS0
779 #define T1CKPS1 T1CON_bits.T1CKPS1
781 // ----- T2CON bits --------------------
784 unsigned char T2CKPS0:1;
785 unsigned char T2CKPS1:1;
786 unsigned char TMR2ON:1;
787 unsigned char TOUTPS0:1;
788 unsigned char TOUTPS1:1;
789 unsigned char TOUTPS2:1;
790 unsigned char TOUTPS3:1;
794 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
796 #define T2CKPS0 T2CON_bits.T2CKPS0
797 #define T2CKPS1 T2CON_bits.T2CKPS1
798 #define TMR2ON T2CON_bits.TMR2ON
799 #define TOUTPS0 T2CON_bits.TOUTPS0
800 #define TOUTPS1 T2CON_bits.TOUTPS1
801 #define TOUTPS2 T2CON_bits.TOUTPS2
802 #define TOUTPS3 T2CON_bits.TOUTPS3