2 // Register Declarations for Microchip 16F872 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define SSPCON2_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define SSPADD_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define ADRESL_ADDR 0x009E
64 #define ADCON1_ADDR 0x009F
65 #define EEDATA_ADDR 0x010C
66 #define EEADR_ADDR 0x010D
67 #define EEDATH_ADDR 0x010E
68 #define EEADRH_ADDR 0x010F
69 #define EECON1_ADDR 0x018C
70 #define EECON2_ADDR 0x018D
73 // Memory organization.
79 // P16F872.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
82 // This header file defines configurations, registers, and other useful bits of
83 // information for the PIC16F872 microcontroller. These names are taken to match
84 // the data sheets as closely as possible.
86 // Note that the processor must be selected before this file is
87 // included. The processor may be selected the following ways:
89 // 1. Command line switch:
90 // C:\ MPASM MYFILE.ASM /PIC16F872
91 // 2. LIST directive in the source file
93 // 3. Processor Type entry in the MPASM full-screen interface
95 //==========================================================================
99 //==========================================================================
103 //1.01 11/17/05 Added the INTCON bits TMR0IE and TMR0IF
104 //1.00 01/25/98 Initial Release
106 //==========================================================================
110 //==========================================================================
113 // MESSG "Processor-header file mismatch. Verify selected processor."
116 //==========================================================================
118 // Register Definitions
120 //==========================================================================
125 //----- Register Files------------------------------------------------------
127 extern __sfr __at (INDF_ADDR) INDF;
128 extern __sfr __at (TMR0_ADDR) TMR0;
129 extern __sfr __at (PCL_ADDR) PCL;
130 extern __sfr __at (STATUS_ADDR) STATUS;
131 extern __sfr __at (FSR_ADDR) FSR;
132 extern __sfr __at (PORTA_ADDR) PORTA;
133 extern __sfr __at (PORTB_ADDR) PORTB;
134 extern __sfr __at (PORTC_ADDR) PORTC;
135 extern __sfr __at (PCLATH_ADDR) PCLATH;
136 extern __sfr __at (INTCON_ADDR) INTCON;
137 extern __sfr __at (PIR1_ADDR) PIR1;
138 extern __sfr __at (PIR2_ADDR) PIR2;
139 extern __sfr __at (TMR1L_ADDR) TMR1L;
140 extern __sfr __at (TMR1H_ADDR) TMR1H;
141 extern __sfr __at (T1CON_ADDR) T1CON;
142 extern __sfr __at (TMR2_ADDR) TMR2;
143 extern __sfr __at (T2CON_ADDR) T2CON;
144 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
145 extern __sfr __at (SSPCON_ADDR) SSPCON;
146 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
147 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
148 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
149 extern __sfr __at (ADRESH_ADDR) ADRESH;
150 extern __sfr __at (ADCON0_ADDR) ADCON0;
152 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
153 extern __sfr __at (TRISA_ADDR) TRISA;
154 extern __sfr __at (TRISB_ADDR) TRISB;
155 extern __sfr __at (TRISC_ADDR) TRISC;
156 extern __sfr __at (PIE1_ADDR) PIE1;
157 extern __sfr __at (PIE2_ADDR) PIE2;
158 extern __sfr __at (PCON_ADDR) PCON;
159 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
160 extern __sfr __at (PR2_ADDR) PR2;
161 extern __sfr __at (SSPADD_ADDR) SSPADD;
162 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
163 extern __sfr __at (ADRESL_ADDR) ADRESL;
164 extern __sfr __at (ADCON1_ADDR) ADCON1;
166 extern __sfr __at (EEDATA_ADDR) EEDATA;
167 extern __sfr __at (EEADR_ADDR) EEADR;
168 extern __sfr __at (EEDATH_ADDR) EEDATH;
169 extern __sfr __at (EEADRH_ADDR) EEADRH;
171 extern __sfr __at (EECON1_ADDR) EECON1;
172 extern __sfr __at (EECON2_ADDR) EECON2;
174 //----- STATUS Bits --------------------------------------------------------
177 //----- INTCON Bits --------------------------------------------------------
180 //----- PIR1 Bits ----------------------------------------------------------
183 //----- PIR2 Bits ----------------------------------------------------------
186 //----- T1CON Bits ---------------------------------------------------------
189 //----- T2CON Bits ---------------------------------------------------------
192 //----- SSPCON Bits --------------------------------------------------------
195 //----- CCP1CON Bits -------------------------------------------------------
198 //----- ADCON0 Bits --------------------------------------------------------
201 //----- OPTION_REG Bits -----------------------------------------------------
204 //----- PIE1 Bits ----------------------------------------------------------
207 //----- PIE2 Bits ----------------------------------------------------------
210 //----- PCON Bits ----------------------------------------------------------
213 //----- SSPCON2 Bits --------------------------------------------------------
216 //----- SSPSTAT Bits -------------------------------------------------------
219 //----- ADCON1 Bits --------------------------------------------------------
222 //----- EECON1 Bits --------------------------------------------------------
225 //==========================================================================
229 //==========================================================================
232 // __BADRAM H'008'-H'009', H'018'-H'01D', H'088'-H'089'
233 // __BADRAM H'08F'-H'090', H'095'-H'09D', H'0C0'-H'0EF'
234 // __BADRAM H'105', H'107'-H'109'
235 // __BADRAM H'110'-H'11F', H'185'
236 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F',H'1C0'-H'1EF'
238 //==========================================================================
240 // Configuration Bits
242 // Code protection for the PIC16C872 is different than for other PIC16C87X devices.
243 // The CP_ALL and CP_OFF switches operate as expected.
244 // CP_HALF protects the lower half of program memory. The upper half is open.
245 // CP_UPPER_256 protects everything EXCEPT the top 256 words.
246 //==========================================================================
248 #define _CP_ALL 0x0FCF
249 #define _CP_HALF 0x1FDF
250 #define _CP_UPPER_256 0x2FEF
251 #define _CP_OFF 0x3FFF
252 #define _DEBUG_ON 0x37FF
253 #define _DEBUG_OFF 0x3FFF
254 #define _WRT_ENABLE_ON 0x3FFF
255 #define _WRT_ENABLE_OFF 0x3DFF
256 #define _CPD_ON 0x3EFF
257 #define _CPD_OFF 0x3FFF
258 #define _LVP_ON 0x3FFF
259 #define _LVP_OFF 0x3F7F
260 #define _BODEN_ON 0x3FFF
261 #define _BODEN_OFF 0x3FBF
262 #define _PWRTE_OFF 0x3FFF
263 #define _PWRTE_ON 0x3FF7
264 #define _WDT_ON 0x3FFF
265 #define _WDT_OFF 0x3FFB
266 #define _LP_OSC 0x3FFC
267 #define _XT_OSC 0x3FFD
268 #define _HS_OSC 0x3FFE
269 #define _RC_OSC 0x3FFF
273 // ----- ADCON0 bits --------------------
276 unsigned char ADON:1;
279 unsigned char CHS0:1;
280 unsigned char CHS1:1;
281 unsigned char CHS2:1;
282 unsigned char ADCS0:1;
283 unsigned char ADCS1:1;
288 unsigned char NOT_DONE:1;
298 unsigned char GO_DONE:1;
306 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
308 #ifndef NO_BIT_DEFINES
309 #define ADON ADCON0_bits.ADON
310 #define GO ADCON0_bits.GO
311 #define NOT_DONE ADCON0_bits.NOT_DONE
312 #define GO_DONE ADCON0_bits.GO_DONE
313 #define CHS0 ADCON0_bits.CHS0
314 #define CHS1 ADCON0_bits.CHS1
315 #define CHS2 ADCON0_bits.CHS2
316 #define ADCS0 ADCON0_bits.ADCS0
317 #define ADCS1 ADCON0_bits.ADCS1
318 #endif /* NO_BIT_DEFINES */
320 // ----- ADCON1 bits --------------------
323 unsigned char PCFG0:1;
324 unsigned char PCFG1:1;
325 unsigned char PCFG2:1;
326 unsigned char PCFG3:1;
330 unsigned char ADFM:1;
333 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
335 #ifndef NO_BIT_DEFINES
336 #define PCFG0 ADCON1_bits.PCFG0
337 #define PCFG1 ADCON1_bits.PCFG1
338 #define PCFG2 ADCON1_bits.PCFG2
339 #define PCFG3 ADCON1_bits.PCFG3
340 #define ADFM ADCON1_bits.ADFM
341 #endif /* NO_BIT_DEFINES */
343 // ----- CCP1CON bits --------------------
346 unsigned char CCP1M0:1;
347 unsigned char CCP1M1:1;
348 unsigned char CCP1M2:1;
349 unsigned char CCP1M3:1;
350 unsigned char CCP1Y:1;
351 unsigned char CCP1X:1;
356 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
358 #ifndef NO_BIT_DEFINES
359 #define CCP1M0 CCP1CON_bits.CCP1M0
360 #define CCP1M1 CCP1CON_bits.CCP1M1
361 #define CCP1M2 CCP1CON_bits.CCP1M2
362 #define CCP1M3 CCP1CON_bits.CCP1M3
363 #define CCP1Y CCP1CON_bits.CCP1Y
364 #define CCP1X CCP1CON_bits.CCP1X
365 #endif /* NO_BIT_DEFINES */
367 // ----- EECON1 bits --------------------
372 unsigned char WREN:1;
373 unsigned char WRERR:1;
377 unsigned char EEPGD:1;
380 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
382 #ifndef NO_BIT_DEFINES
383 #define RD EECON1_bits.RD
384 #define WR EECON1_bits.WR
385 #define WREN EECON1_bits.WREN
386 #define WRERR EECON1_bits.WRERR
387 #define EEPGD EECON1_bits.EEPGD
388 #endif /* NO_BIT_DEFINES */
390 // ----- INTCON bits --------------------
393 unsigned char RBIF:1;
394 unsigned char INTF:1;
395 unsigned char T0IF:1;
396 unsigned char RBIE:1;
397 unsigned char INTE:1;
398 unsigned char T0IE:1;
399 unsigned char PEIE:1;
405 unsigned char TMR0IF:1;
408 unsigned char TMR0IE:1;
413 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
415 #ifndef NO_BIT_DEFINES
416 #define RBIF INTCON_bits.RBIF
417 #define INTF INTCON_bits.INTF
418 #define T0IF INTCON_bits.T0IF
419 #define TMR0IF INTCON_bits.TMR0IF
420 #define RBIE INTCON_bits.RBIE
421 #define INTE INTCON_bits.INTE
422 #define T0IE INTCON_bits.T0IE
423 #define TMR0IE INTCON_bits.TMR0IE
424 #define PEIE INTCON_bits.PEIE
425 #define GIE INTCON_bits.GIE
426 #endif /* NO_BIT_DEFINES */
428 // ----- OPTION_REG bits --------------------
435 unsigned char T0SE:1;
436 unsigned char T0CS:1;
437 unsigned char INTEDG:1;
438 unsigned char NOT_RBPU:1;
440 } __OPTION_REG_bits_t;
441 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
443 #ifndef NO_BIT_DEFINES
444 #define PS0 OPTION_REG_bits.PS0
445 #define PS1 OPTION_REG_bits.PS1
446 #define PS2 OPTION_REG_bits.PS2
447 #define PSA OPTION_REG_bits.PSA
448 #define T0SE OPTION_REG_bits.T0SE
449 #define T0CS OPTION_REG_bits.T0CS
450 #define INTEDG OPTION_REG_bits.INTEDG
451 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
452 #endif /* NO_BIT_DEFINES */
454 // ----- PCON bits --------------------
457 unsigned char NOT_BO:1;
458 unsigned char NOT_POR:1;
467 unsigned char NOT_BOR:1;
477 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
479 #ifndef NO_BIT_DEFINES
480 #define NOT_BO PCON_bits.NOT_BO
481 #define NOT_BOR PCON_bits.NOT_BOR
482 #define NOT_POR PCON_bits.NOT_POR
483 #endif /* NO_BIT_DEFINES */
485 // ----- PIE1 bits --------------------
488 unsigned char TMR1IE:1;
489 unsigned char TMR2IE:1;
490 unsigned char CCP1IE:1;
491 unsigned char SSPIE:1;
494 unsigned char ADIE:1;
498 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
500 #ifndef NO_BIT_DEFINES
501 #define TMR1IE PIE1_bits.TMR1IE
502 #define TMR2IE PIE1_bits.TMR2IE
503 #define CCP1IE PIE1_bits.CCP1IE
504 #define SSPIE PIE1_bits.SSPIE
505 #define ADIE PIE1_bits.ADIE
506 #endif /* NO_BIT_DEFINES */
508 // ----- PIE2 bits --------------------
514 unsigned char BCLIE:1;
515 unsigned char EEIE:1;
521 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
523 #ifndef NO_BIT_DEFINES
524 #define BCLIE PIE2_bits.BCLIE
525 #define EEIE PIE2_bits.EEIE
526 #endif /* NO_BIT_DEFINES */
528 // ----- PIR1 bits --------------------
531 unsigned char TMR1IF:1;
532 unsigned char TMR2IF:1;
533 unsigned char CCP1IF:1;
534 unsigned char SSPIF:1;
537 unsigned char ADIF:1;
541 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
543 #ifndef NO_BIT_DEFINES
544 #define TMR1IF PIR1_bits.TMR1IF
545 #define TMR2IF PIR1_bits.TMR2IF
546 #define CCP1IF PIR1_bits.CCP1IF
547 #define SSPIF PIR1_bits.SSPIF
548 #define ADIF PIR1_bits.ADIF
549 #endif /* NO_BIT_DEFINES */
551 // ----- PIR2 bits --------------------
557 unsigned char BCLIF:1;
558 unsigned char EEIF:1;
564 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
566 #ifndef NO_BIT_DEFINES
567 #define BCLIF PIR2_bits.BCLIF
568 #define EEIF PIR2_bits.EEIF
569 #endif /* NO_BIT_DEFINES */
571 // ----- PORTA bits --------------------
584 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
586 #ifndef NO_BIT_DEFINES
587 #define RA0 PORTA_bits.RA0
588 #define RA1 PORTA_bits.RA1
589 #define RA2 PORTA_bits.RA2
590 #define RA3 PORTA_bits.RA3
591 #define RA4 PORTA_bits.RA4
592 #define RA5 PORTA_bits.RA5
593 #endif /* NO_BIT_DEFINES */
595 // ----- PORTB bits --------------------
608 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
610 #ifndef NO_BIT_DEFINES
611 #define RB0 PORTB_bits.RB0
612 #define RB1 PORTB_bits.RB1
613 #define RB2 PORTB_bits.RB2
614 #define RB3 PORTB_bits.RB3
615 #define RB4 PORTB_bits.RB4
616 #define RB5 PORTB_bits.RB5
617 #define RB6 PORTB_bits.RB6
618 #define RB7 PORTB_bits.RB7
619 #endif /* NO_BIT_DEFINES */
621 // ----- PORTC bits --------------------
634 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
636 #ifndef NO_BIT_DEFINES
637 #define RC0 PORTC_bits.RC0
638 #define RC1 PORTC_bits.RC1
639 #define RC2 PORTC_bits.RC2
640 #define RC3 PORTC_bits.RC3
641 #define RC4 PORTC_bits.RC4
642 #define RC5 PORTC_bits.RC5
643 #define RC6 PORTC_bits.RC6
644 #define RC7 PORTC_bits.RC7
645 #endif /* NO_BIT_DEFINES */
647 // ----- SSPCON bits --------------------
650 unsigned char SSPM0:1;
651 unsigned char SSPM1:1;
652 unsigned char SSPM2:1;
653 unsigned char SSPM3:1;
655 unsigned char SSPEN:1;
656 unsigned char SSPOV:1;
657 unsigned char WCOL:1;
660 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
662 #ifndef NO_BIT_DEFINES
663 #define SSPM0 SSPCON_bits.SSPM0
664 #define SSPM1 SSPCON_bits.SSPM1
665 #define SSPM2 SSPCON_bits.SSPM2
666 #define SSPM3 SSPCON_bits.SSPM3
667 #define CKP SSPCON_bits.CKP
668 #define SSPEN SSPCON_bits.SSPEN
669 #define SSPOV SSPCON_bits.SSPOV
670 #define WCOL SSPCON_bits.WCOL
671 #endif /* NO_BIT_DEFINES */
673 // ----- SSPCON2 bits --------------------
677 unsigned char RSEN:1;
679 unsigned char RCEN:1;
680 unsigned char ACKEN:1;
681 unsigned char ACKDT:1;
682 unsigned char ACKSTAT:1;
683 unsigned char GCEN:1;
686 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
688 #ifndef NO_BIT_DEFINES
689 #define SEN SSPCON2_bits.SEN
690 #define RSEN SSPCON2_bits.RSEN
691 #define PEN SSPCON2_bits.PEN
692 #define RCEN SSPCON2_bits.RCEN
693 #define ACKEN SSPCON2_bits.ACKEN
694 #define ACKDT SSPCON2_bits.ACKDT
695 #define ACKSTAT SSPCON2_bits.ACKSTAT
696 #define GCEN SSPCON2_bits.GCEN
697 #endif /* NO_BIT_DEFINES */
699 // ----- SSPSTAT bits --------------------
714 unsigned char I2C_READ:1;
715 unsigned char I2C_START:1;
716 unsigned char I2C_STOP:1;
717 unsigned char I2C_DATA:1;
724 unsigned char NOT_W:1;
727 unsigned char NOT_A:1;
734 unsigned char NOT_WRITE:1;
737 unsigned char NOT_ADDRESS:1;
754 unsigned char READ_WRITE:1;
757 unsigned char DATA_ADDRESS:1;
762 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
764 #ifndef NO_BIT_DEFINES
765 #define BF SSPSTAT_bits.BF
766 #define UA SSPSTAT_bits.UA
767 #define R SSPSTAT_bits.R
768 #define I2C_READ SSPSTAT_bits.I2C_READ
769 #define NOT_W SSPSTAT_bits.NOT_W
770 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
771 #define R_W SSPSTAT_bits.R_W
772 #define READ_WRITE SSPSTAT_bits.READ_WRITE
773 #define S SSPSTAT_bits.S
774 #define I2C_START SSPSTAT_bits.I2C_START
775 #define P SSPSTAT_bits.P
776 #define I2C_STOP SSPSTAT_bits.I2C_STOP
777 #define D SSPSTAT_bits.D
778 #define I2C_DATA SSPSTAT_bits.I2C_DATA
779 #define NOT_A SSPSTAT_bits.NOT_A
780 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
781 #define D_A SSPSTAT_bits.D_A
782 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
783 #define CKE SSPSTAT_bits.CKE
784 #define SMP SSPSTAT_bits.SMP
785 #endif /* NO_BIT_DEFINES */
787 // ----- STATUS bits --------------------
793 unsigned char NOT_PD:1;
794 unsigned char NOT_TO:1;
800 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
802 #ifndef NO_BIT_DEFINES
803 #define C STATUS_bits.C
804 #define DC STATUS_bits.DC
805 #define Z STATUS_bits.Z
806 #define NOT_PD STATUS_bits.NOT_PD
807 #define NOT_TO STATUS_bits.NOT_TO
808 #define RP0 STATUS_bits.RP0
809 #define RP1 STATUS_bits.RP1
810 #define IRP STATUS_bits.IRP
811 #endif /* NO_BIT_DEFINES */
813 // ----- T1CON bits --------------------
816 unsigned char TMR1ON:1;
817 unsigned char TMR1CS:1;
818 unsigned char NOT_T1SYNC:1;
819 unsigned char T1OSCEN:1;
820 unsigned char T1CKPS0:1;
821 unsigned char T1CKPS1:1;
828 unsigned char T1INSYNC:1;
838 unsigned char T1SYNC:1;
846 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
848 #ifndef NO_BIT_DEFINES
849 #define TMR1ON T1CON_bits.TMR1ON
850 #define TMR1CS T1CON_bits.TMR1CS
851 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
852 #define T1INSYNC T1CON_bits.T1INSYNC
853 #define T1SYNC T1CON_bits.T1SYNC
854 #define T1OSCEN T1CON_bits.T1OSCEN
855 #define T1CKPS0 T1CON_bits.T1CKPS0
856 #define T1CKPS1 T1CON_bits.T1CKPS1
857 #endif /* NO_BIT_DEFINES */
859 // ----- T2CON bits --------------------
862 unsigned char T2CKPS0:1;
863 unsigned char T2CKPS1:1;
864 unsigned char TMR2ON:1;
865 unsigned char TOUTPS0:1;
866 unsigned char TOUTPS1:1;
867 unsigned char TOUTPS2:1;
868 unsigned char TOUTPS3:1;
872 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
874 #ifndef NO_BIT_DEFINES
875 #define T2CKPS0 T2CON_bits.T2CKPS0
876 #define T2CKPS1 T2CON_bits.T2CKPS1
877 #define TMR2ON T2CON_bits.TMR2ON
878 #define TOUTPS0 T2CON_bits.TOUTPS0
879 #define TOUTPS1 T2CON_bits.TOUTPS1
880 #define TOUTPS2 T2CON_bits.TOUTPS2
881 #define TOUTPS3 T2CON_bits.TOUTPS3
882 #endif /* NO_BIT_DEFINES */
884 // ----- TRISA bits --------------------
887 unsigned char TRISA0:1;
888 unsigned char TRISA1:1;
889 unsigned char TRISA2:1;
890 unsigned char TRISA3:1;
891 unsigned char TRISA4:1;
892 unsigned char TRISA5:1;
897 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
899 #ifndef NO_BIT_DEFINES
900 #define TRISA0 TRISA_bits.TRISA0
901 #define TRISA1 TRISA_bits.TRISA1
902 #define TRISA2 TRISA_bits.TRISA2
903 #define TRISA3 TRISA_bits.TRISA3
904 #define TRISA4 TRISA_bits.TRISA4
905 #define TRISA5 TRISA_bits.TRISA5
906 #endif /* NO_BIT_DEFINES */
908 // ----- TRISB bits --------------------
911 unsigned char TRISB0:1;
912 unsigned char TRISB1:1;
913 unsigned char TRISB2:1;
914 unsigned char TRISB3:1;
915 unsigned char TRISB4:1;
916 unsigned char TRISB5:1;
917 unsigned char TRISB6:1;
918 unsigned char TRISB7:1;
921 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
923 #ifndef NO_BIT_DEFINES
924 #define TRISB0 TRISB_bits.TRISB0
925 #define TRISB1 TRISB_bits.TRISB1
926 #define TRISB2 TRISB_bits.TRISB2
927 #define TRISB3 TRISB_bits.TRISB3
928 #define TRISB4 TRISB_bits.TRISB4
929 #define TRISB5 TRISB_bits.TRISB5
930 #define TRISB6 TRISB_bits.TRISB6
931 #define TRISB7 TRISB_bits.TRISB7
932 #endif /* NO_BIT_DEFINES */
934 // ----- TRISC bits --------------------
937 unsigned char TRISC0:1;
938 unsigned char TRISC1:1;
939 unsigned char TRISC2:1;
940 unsigned char TRISC3:1;
941 unsigned char TRISC4:1;
942 unsigned char TRISC5:1;
943 unsigned char TRISC6:1;
944 unsigned char TRISC7:1;
947 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
949 #ifndef NO_BIT_DEFINES
950 #define TRISC0 TRISC_bits.TRISC0
951 #define TRISC1 TRISC_bits.TRISC1
952 #define TRISC2 TRISC_bits.TRISC2
953 #define TRISC3 TRISC_bits.TRISC3
954 #define TRISC4 TRISC_bits.TRISC4
955 #define TRISC5 TRISC_bits.TRISC5
956 #define TRISC6 TRISC_bits.TRISC6
957 #define TRISC7 TRISC_bits.TRISC7
958 #endif /* NO_BIT_DEFINES */