2 // Register Declarations for Microchip 16F872 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define SSPCON2_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define SSPADD_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define ADRESL_ADDR 0x009E
64 #define ADCON1_ADDR 0x009F
65 #define EEDATA_ADDR 0x010C
66 #define EEADR_ADDR 0x010D
67 #define EEDATH_ADDR 0x010E
68 #define EEADRH_ADDR 0x010F
69 #define EECON1_ADDR 0x018C
70 #define EECON2_ADDR 0x018D
73 // Memory organization.
79 // P16F872.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
82 // This header file defines configurations, registers, and other useful bits of
83 // information for the PIC16F872 microcontroller. These names are taken to match
84 // the data sheets as closely as possible.
86 // Note that the processor must be selected before this file is
87 // included. The processor may be selected the following ways:
89 // 1. Command line switch:
90 // C:\ MPASM MYFILE.ASM /PIC16F872
91 // 2. LIST directive in the source file
93 // 3. Processor Type entry in the MPASM full-screen interface
95 //==========================================================================
99 //==========================================================================
103 //1.00 01/25/98 Initial Release
105 //==========================================================================
109 //==========================================================================
112 // MESSG "Processor-header file mismatch. Verify selected processor."
115 //==========================================================================
117 // Register Definitions
119 //==========================================================================
124 //----- Register Files------------------------------------------------------
126 extern __data __at (INDF_ADDR) volatile char INDF;
127 extern __sfr __at (TMR0_ADDR) TMR0;
128 extern __data __at (PCL_ADDR) volatile char PCL;
129 extern __sfr __at (STATUS_ADDR) STATUS;
130 extern __sfr __at (FSR_ADDR) FSR;
131 extern __sfr __at (PORTA_ADDR) PORTA;
132 extern __sfr __at (PORTB_ADDR) PORTB;
133 extern __sfr __at (PORTC_ADDR) PORTC;
134 extern __sfr __at (PCLATH_ADDR) PCLATH;
135 extern __sfr __at (INTCON_ADDR) INTCON;
136 extern __sfr __at (PIR1_ADDR) PIR1;
137 extern __sfr __at (PIR2_ADDR) PIR2;
138 extern __sfr __at (TMR1L_ADDR) TMR1L;
139 extern __sfr __at (TMR1H_ADDR) TMR1H;
140 extern __sfr __at (T1CON_ADDR) T1CON;
141 extern __sfr __at (TMR2_ADDR) TMR2;
142 extern __sfr __at (T2CON_ADDR) T2CON;
143 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
144 extern __sfr __at (SSPCON_ADDR) SSPCON;
145 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
146 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
147 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
148 extern __sfr __at (ADRESH_ADDR) ADRESH;
149 extern __sfr __at (ADCON0_ADDR) ADCON0;
151 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
152 extern __sfr __at (TRISA_ADDR) TRISA;
153 extern __sfr __at (TRISB_ADDR) TRISB;
154 extern __sfr __at (TRISC_ADDR) TRISC;
155 extern __sfr __at (PIE1_ADDR) PIE1;
156 extern __sfr __at (PIE2_ADDR) PIE2;
157 extern __sfr __at (PCON_ADDR) PCON;
158 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
159 extern __sfr __at (PR2_ADDR) PR2;
160 extern __sfr __at (SSPADD_ADDR) SSPADD;
161 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
162 extern __sfr __at (ADRESL_ADDR) ADRESL;
163 extern __sfr __at (ADCON1_ADDR) ADCON1;
165 extern __sfr __at (EEDATA_ADDR) EEDATA;
166 extern __sfr __at (EEADR_ADDR) EEADR;
167 extern __sfr __at (EEDATH_ADDR) EEDATH;
168 extern __sfr __at (EEADRH_ADDR) EEADRH;
170 extern __sfr __at (EECON1_ADDR) EECON1;
171 extern __sfr __at (EECON2_ADDR) EECON2;
173 //----- STATUS Bits --------------------------------------------------------
176 //----- INTCON Bits --------------------------------------------------------
179 //----- PIR1 Bits ----------------------------------------------------------
182 //----- PIR2 Bits ----------------------------------------------------------
185 //----- T1CON Bits ---------------------------------------------------------
188 //----- T2CON Bits ---------------------------------------------------------
191 //----- SSPCON Bits --------------------------------------------------------
194 //----- CCP1CON Bits -------------------------------------------------------
197 //----- ADCON0 Bits --------------------------------------------------------
200 //----- OPTION_REG Bits -----------------------------------------------------
203 //----- PIE1 Bits ----------------------------------------------------------
206 //----- PIE2 Bits ----------------------------------------------------------
209 //----- PCON Bits ----------------------------------------------------------
212 //----- SSPCON2 Bits --------------------------------------------------------
215 //----- SSPSTAT Bits -------------------------------------------------------
218 //----- ADCON1 Bits --------------------------------------------------------
221 //----- EECON1 Bits --------------------------------------------------------
224 //==========================================================================
228 //==========================================================================
231 // __BADRAM H'008'-H'009', H'018'-H'01D', H'088'-H'089'
232 // __BADRAM H'08F'-H'090', H'095'-H'09D', H'0C0'-H'0EF'
233 // __BADRAM H'105', H'107'-H'109'
234 // __BADRAM H'110'-H'11F', H'185'
235 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F',H'1C0'-H'1EF'
237 //==========================================================================
239 // Configuration Bits
241 // Code protection for the PIC16C872 is different than for other PIC16C87X devices.
242 // The CP_ALL and CP_OFF switches operate as expected.
243 // CP_HALF protects the lower half of program memory. The upper half is open.
244 // CP_UPPER_256 protects everything EXCEPT the top 256 words.
245 //==========================================================================
247 #define _CP_ALL 0x0FCF
248 #define _CP_HALF 0x1FDF
249 #define _CP_UPPER_256 0x2FEF
250 #define _CP_OFF 0x3FFF
251 #define _DEBUG_ON 0x37FF
252 #define _DEBUG_OFF 0x3FFF
253 #define _WRT_ENABLE_ON 0x3FFF
254 #define _WRT_ENABLE_OFF 0x3DFF
255 #define _CPD_ON 0x3EFF
256 #define _CPD_OFF 0x3FFF
257 #define _LVP_ON 0x3FFF
258 #define _LVP_OFF 0x3F7F
259 #define _BODEN_ON 0x3FFF
260 #define _BODEN_OFF 0x3FBF
261 #define _PWRTE_OFF 0x3FFF
262 #define _PWRTE_ON 0x3FF7
263 #define _WDT_ON 0x3FFF
264 #define _WDT_OFF 0x3FFB
265 #define _LP_OSC 0x3FFC
266 #define _XT_OSC 0x3FFD
267 #define _HS_OSC 0x3FFE
268 #define _RC_OSC 0x3FFF
272 // ----- ADCON0 bits --------------------
275 unsigned char ADON:1;
278 unsigned char CHS0:1;
279 unsigned char CHS1:1;
280 unsigned char CHS2:1;
281 unsigned char ADCS0:1;
282 unsigned char ADCS1:1;
287 unsigned char NOT_DONE:1;
297 unsigned char GO_DONE:1;
305 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
307 #define ADON ADCON0_bits.ADON
308 #define GO ADCON0_bits.GO
309 #define NOT_DONE ADCON0_bits.NOT_DONE
310 #define GO_DONE ADCON0_bits.GO_DONE
311 #define CHS0 ADCON0_bits.CHS0
312 #define CHS1 ADCON0_bits.CHS1
313 #define CHS2 ADCON0_bits.CHS2
314 #define ADCS0 ADCON0_bits.ADCS0
315 #define ADCS1 ADCON0_bits.ADCS1
317 // ----- ADCON1 bits --------------------
320 unsigned char PCFG0:1;
321 unsigned char PCFG1:1;
322 unsigned char PCFG2:1;
323 unsigned char PCFG3:1;
327 unsigned char ADFM:1;
330 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
332 #define PCFG0 ADCON1_bits.PCFG0
333 #define PCFG1 ADCON1_bits.PCFG1
334 #define PCFG2 ADCON1_bits.PCFG2
335 #define PCFG3 ADCON1_bits.PCFG3
336 #define ADFM ADCON1_bits.ADFM
338 // ----- CCP1CON bits --------------------
341 unsigned char CCP1M0:1;
342 unsigned char CCP1M1:1;
343 unsigned char CCP1M2:1;
344 unsigned char CCP1M3:1;
345 unsigned char CCP1Y:1;
346 unsigned char CCP1X:1;
351 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
353 #define CCP1M0 CCP1CON_bits.CCP1M0
354 #define CCP1M1 CCP1CON_bits.CCP1M1
355 #define CCP1M2 CCP1CON_bits.CCP1M2
356 #define CCP1M3 CCP1CON_bits.CCP1M3
357 #define CCP1Y CCP1CON_bits.CCP1Y
358 #define CCP1X CCP1CON_bits.CCP1X
360 // ----- EECON1 bits --------------------
365 unsigned char WREN:1;
366 unsigned char WRERR:1;
370 unsigned char EEPGD:1;
373 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
375 #define RD EECON1_bits.RD
376 #define WR EECON1_bits.WR
377 #define WREN EECON1_bits.WREN
378 #define WRERR EECON1_bits.WRERR
379 #define EEPGD EECON1_bits.EEPGD
381 // ----- INTCON bits --------------------
384 unsigned char RBIF:1;
385 unsigned char INTF:1;
386 unsigned char T0IF:1;
387 unsigned char RBIE:1;
388 unsigned char INTE:1;
389 unsigned char T0IE:1;
390 unsigned char PEIE:1;
394 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
396 #define RBIF INTCON_bits.RBIF
397 #define INTF INTCON_bits.INTF
398 #define T0IF INTCON_bits.T0IF
399 #define RBIE INTCON_bits.RBIE
400 #define INTE INTCON_bits.INTE
401 #define T0IE INTCON_bits.T0IE
402 #define PEIE INTCON_bits.PEIE
403 #define GIE INTCON_bits.GIE
405 // ----- OPTION_REG bits --------------------
412 unsigned char T0SE:1;
413 unsigned char T0CS:1;
414 unsigned char INTEDG:1;
415 unsigned char NOT_RBPU:1;
417 } __OPTION_REG_bits_t;
418 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
420 #define PS0 OPTION_REG_bits.PS0
421 #define PS1 OPTION_REG_bits.PS1
422 #define PS2 OPTION_REG_bits.PS2
423 #define PSA OPTION_REG_bits.PSA
424 #define T0SE OPTION_REG_bits.T0SE
425 #define T0CS OPTION_REG_bits.T0CS
426 #define INTEDG OPTION_REG_bits.INTEDG
427 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
429 // ----- PCON bits --------------------
432 unsigned char NOT_BO:1;
433 unsigned char NOT_POR:1;
442 unsigned char NOT_BOR:1;
452 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
454 #define NOT_BO PCON_bits.NOT_BO
455 #define NOT_BOR PCON_bits.NOT_BOR
456 #define NOT_POR PCON_bits.NOT_POR
458 // ----- PIE1 bits --------------------
461 unsigned char TMR1IE:1;
462 unsigned char TMR2IE:1;
463 unsigned char CCP1IE:1;
464 unsigned char SSPIE:1;
467 unsigned char ADIE:1;
471 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
473 #define TMR1IE PIE1_bits.TMR1IE
474 #define TMR2IE PIE1_bits.TMR2IE
475 #define CCP1IE PIE1_bits.CCP1IE
476 #define SSPIE PIE1_bits.SSPIE
477 #define ADIE PIE1_bits.ADIE
479 // ----- PIE2 bits --------------------
485 unsigned char BCLIE:1;
486 unsigned char EEIE:1;
492 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
494 #define BCLIE PIE2_bits.BCLIE
495 #define EEIE PIE2_bits.EEIE
497 // ----- PIR1 bits --------------------
500 unsigned char TMR1IF:1;
501 unsigned char TMR2IF:1;
502 unsigned char CCP1IF:1;
503 unsigned char SSPIF:1;
506 unsigned char ADIF:1;
510 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
512 #define TMR1IF PIR1_bits.TMR1IF
513 #define TMR2IF PIR1_bits.TMR2IF
514 #define CCP1IF PIR1_bits.CCP1IF
515 #define SSPIF PIR1_bits.SSPIF
516 #define ADIF PIR1_bits.ADIF
518 // ----- PIR2 bits --------------------
524 unsigned char BCLIF:1;
525 unsigned char EEIF:1;
531 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
533 #define BCLIF PIR2_bits.BCLIF
534 #define EEIF PIR2_bits.EEIF
536 // ----- PORTA bits --------------------
549 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
551 #define RA0 PORTA_bits.RA0
552 #define RA1 PORTA_bits.RA1
553 #define RA2 PORTA_bits.RA2
554 #define RA3 PORTA_bits.RA3
555 #define RA4 PORTA_bits.RA4
556 #define RA5 PORTA_bits.RA5
558 // ----- PORTB bits --------------------
571 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
573 #define RB0 PORTB_bits.RB0
574 #define RB1 PORTB_bits.RB1
575 #define RB2 PORTB_bits.RB2
576 #define RB3 PORTB_bits.RB3
577 #define RB4 PORTB_bits.RB4
578 #define RB5 PORTB_bits.RB5
579 #define RB6 PORTB_bits.RB6
580 #define RB7 PORTB_bits.RB7
582 // ----- PORTC bits --------------------
595 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
597 #define RC0 PORTC_bits.RC0
598 #define RC1 PORTC_bits.RC1
599 #define RC2 PORTC_bits.RC2
600 #define RC3 PORTC_bits.RC3
601 #define RC4 PORTC_bits.RC4
602 #define RC5 PORTC_bits.RC5
603 #define RC6 PORTC_bits.RC6
604 #define RC7 PORTC_bits.RC7
606 // ----- SSPCON bits --------------------
609 unsigned char SSPM0:1;
610 unsigned char SSPM1:1;
611 unsigned char SSPM2:1;
612 unsigned char SSPM3:1;
614 unsigned char SSPEN:1;
615 unsigned char SSPOV:1;
616 unsigned char WCOL:1;
619 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
621 #define SSPM0 SSPCON_bits.SSPM0
622 #define SSPM1 SSPCON_bits.SSPM1
623 #define SSPM2 SSPCON_bits.SSPM2
624 #define SSPM3 SSPCON_bits.SSPM3
625 #define CKP SSPCON_bits.CKP
626 #define SSPEN SSPCON_bits.SSPEN
627 #define SSPOV SSPCON_bits.SSPOV
628 #define WCOL SSPCON_bits.WCOL
630 // ----- SSPCON2 bits --------------------
634 unsigned char RSEN:1;
636 unsigned char RCEN:1;
637 unsigned char ACKEN:1;
638 unsigned char ACKDT:1;
639 unsigned char ACKSTAT:1;
640 unsigned char GCEN:1;
643 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
645 #define SEN SSPCON2_bits.SEN
646 #define RSEN SSPCON2_bits.RSEN
647 #define PEN SSPCON2_bits.PEN
648 #define RCEN SSPCON2_bits.RCEN
649 #define ACKEN SSPCON2_bits.ACKEN
650 #define ACKDT SSPCON2_bits.ACKDT
651 #define ACKSTAT SSPCON2_bits.ACKSTAT
652 #define GCEN SSPCON2_bits.GCEN
654 // ----- SSPSTAT bits --------------------
669 unsigned char I2C_READ:1;
670 unsigned char I2C_START:1;
671 unsigned char I2C_STOP:1;
672 unsigned char I2C_DATA:1;
679 unsigned char NOT_W:1;
682 unsigned char NOT_A:1;
689 unsigned char NOT_WRITE:1;
692 unsigned char NOT_ADDRESS:1;
709 unsigned char READ_WRITE:1;
712 unsigned char DATA_ADDRESS:1;
717 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
719 #define BF SSPSTAT_bits.BF
720 #define UA SSPSTAT_bits.UA
721 #define R SSPSTAT_bits.R
722 #define I2C_READ SSPSTAT_bits.I2C_READ
723 #define NOT_W SSPSTAT_bits.NOT_W
724 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
725 #define R_W SSPSTAT_bits.R_W
726 #define READ_WRITE SSPSTAT_bits.READ_WRITE
727 #define S SSPSTAT_bits.S
728 #define I2C_START SSPSTAT_bits.I2C_START
729 #define P SSPSTAT_bits.P
730 #define I2C_STOP SSPSTAT_bits.I2C_STOP
731 #define D SSPSTAT_bits.D
732 #define I2C_DATA SSPSTAT_bits.I2C_DATA
733 #define NOT_A SSPSTAT_bits.NOT_A
734 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
735 #define D_A SSPSTAT_bits.D_A
736 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
737 #define CKE SSPSTAT_bits.CKE
738 #define SMP SSPSTAT_bits.SMP
740 // ----- STATUS bits --------------------
746 unsigned char NOT_PD:1;
747 unsigned char NOT_TO:1;
753 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
755 #define C STATUS_bits.C
756 #define DC STATUS_bits.DC
757 #define Z STATUS_bits.Z
758 #define NOT_PD STATUS_bits.NOT_PD
759 #define NOT_TO STATUS_bits.NOT_TO
760 #define RP0 STATUS_bits.RP0
761 #define RP1 STATUS_bits.RP1
762 #define IRP STATUS_bits.IRP
764 // ----- T1CON bits --------------------
767 unsigned char TMR1ON:1;
768 unsigned char TMR1CS:1;
769 unsigned char NOT_T1SYNC:1;
770 unsigned char T1OSCEN:1;
771 unsigned char T1CKPS0:1;
772 unsigned char T1CKPS1:1;
779 unsigned char T1INSYNC:1;
789 unsigned char T1SYNC:1;
797 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
799 #define TMR1ON T1CON_bits.TMR1ON
800 #define TMR1CS T1CON_bits.TMR1CS
801 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
802 #define T1INSYNC T1CON_bits.T1INSYNC
803 #define T1SYNC T1CON_bits.T1SYNC
804 #define T1OSCEN T1CON_bits.T1OSCEN
805 #define T1CKPS0 T1CON_bits.T1CKPS0
806 #define T1CKPS1 T1CON_bits.T1CKPS1
808 // ----- T2CON bits --------------------
811 unsigned char T2CKPS0:1;
812 unsigned char T2CKPS1:1;
813 unsigned char TMR2ON:1;
814 unsigned char TOUTPS0:1;
815 unsigned char TOUTPS1:1;
816 unsigned char TOUTPS2:1;
817 unsigned char TOUTPS3:1;
821 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
823 #define T2CKPS0 T2CON_bits.T2CKPS0
824 #define T2CKPS1 T2CON_bits.T2CKPS1
825 #define TMR2ON T2CON_bits.TMR2ON
826 #define TOUTPS0 T2CON_bits.TOUTPS0
827 #define TOUTPS1 T2CON_bits.TOUTPS1
828 #define TOUTPS2 T2CON_bits.TOUTPS2
829 #define TOUTPS3 T2CON_bits.TOUTPS3
831 // ----- TRISA bits --------------------
834 unsigned char TRISA0:1;
835 unsigned char TRISA1:1;
836 unsigned char TRISA2:1;
837 unsigned char TRISA3:1;
838 unsigned char TRISA4:1;
839 unsigned char TRISA5:1;
844 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
846 #define TRISA0 TRISA_bits.TRISA0
847 #define TRISA1 TRISA_bits.TRISA1
848 #define TRISA2 TRISA_bits.TRISA2
849 #define TRISA3 TRISA_bits.TRISA3
850 #define TRISA4 TRISA_bits.TRISA4
851 #define TRISA5 TRISA_bits.TRISA5
853 // ----- TRISB bits --------------------
856 unsigned char TRISB0:1;
857 unsigned char TRISB1:1;
858 unsigned char TRISB2:1;
859 unsigned char TRISB3:1;
860 unsigned char TRISB4:1;
861 unsigned char TRISB5:1;
862 unsigned char TRISB6:1;
863 unsigned char TRISB7:1;
866 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
868 #define TRISB0 TRISB_bits.TRISB0
869 #define TRISB1 TRISB_bits.TRISB1
870 #define TRISB2 TRISB_bits.TRISB2
871 #define TRISB3 TRISB_bits.TRISB3
872 #define TRISB4 TRISB_bits.TRISB4
873 #define TRISB5 TRISB_bits.TRISB5
874 #define TRISB6 TRISB_bits.TRISB6
875 #define TRISB7 TRISB_bits.TRISB7
877 // ----- TRISC bits --------------------
880 unsigned char TRISC0:1;
881 unsigned char TRISC1:1;
882 unsigned char TRISC2:1;
883 unsigned char TRISC3:1;
884 unsigned char TRISC4:1;
885 unsigned char TRISC5:1;
886 unsigned char TRISC6:1;
887 unsigned char TRISC7:1;
890 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
892 #define TRISC0 TRISC_bits.TRISC0
893 #define TRISC1 TRISC_bits.TRISC1
894 #define TRISC2 TRISC_bits.TRISC2
895 #define TRISC3 TRISC_bits.TRISC3
896 #define TRISC4 TRISC_bits.TRISC4
897 #define TRISC5 TRISC_bits.TRISC5
898 #define TRISC6 TRISC_bits.TRISC6
899 #define TRISC7 TRISC_bits.TRISC7