2 // Register Declarations for Microchip 16F871 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define ADRESH_ADDR 0x001E
54 #define ADCON0_ADDR 0x001F
55 #define OPTION_REG_ADDR 0x0081
56 #define TRISA_ADDR 0x0085
57 #define TRISB_ADDR 0x0086
58 #define TRISC_ADDR 0x0087
59 #define TRISD_ADDR 0x0088
60 #define TRISE_ADDR 0x0089
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define PR2_ADDR 0x0092
65 #define TXSTA_ADDR 0x0098
66 #define SPBRG_ADDR 0x0099
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDATA_ADDR 0x010C
70 #define EEADR_ADDR 0x010D
71 #define EEDATH_ADDR 0x010E
72 #define EEADRH_ADDR 0x010F
73 #define EECON1_ADDR 0x018C
74 #define EECON2_ADDR 0x018D
77 // Memory organization.
83 // P16F871.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
86 // This header file defines configurations, registers, and other useful bits of
87 // information for the PIC16F871 microcontroller. These names are taken to match
88 // the data sheets as closely as possible.
90 // Note that the processor must be selected before this file is
91 // included. The processor may be selected the following ways:
93 // 1. Command line switch:
94 // C:\ MPASM MYFILE.ASM /PIC16F871
95 // 2. LIST directive in the source file
97 // 3. Processor Type entry in the MPASM full-screen interface
99 //==========================================================================
103 //==========================================================================
107 //1.00 08/07/98 Initial Release - cloned from 16F873
109 //==========================================================================
113 //==========================================================================
116 // MESSG "Processor-header file mismatch. Verify selected processor."
119 //==========================================================================
121 // Register Definitions
123 //==========================================================================
128 //----- Register Files------------------------------------------------------
130 extern __data __at (INDF_ADDR) volatile char INDF;
131 extern __sfr __at (TMR0_ADDR) TMR0;
132 extern __data __at (PCL_ADDR) volatile char PCL;
133 extern __sfr __at (STATUS_ADDR) STATUS;
134 extern __sfr __at (FSR_ADDR) FSR;
135 extern __sfr __at (PORTA_ADDR) PORTA;
136 extern __sfr __at (PORTB_ADDR) PORTB;
137 extern __sfr __at (PORTC_ADDR) PORTC;
138 extern __sfr __at (PORTD_ADDR) PORTD;
139 extern __sfr __at (PORTE_ADDR) PORTE;
140 extern __sfr __at (PCLATH_ADDR) PCLATH;
141 extern __sfr __at (INTCON_ADDR) INTCON;
142 extern __sfr __at (PIR1_ADDR) PIR1;
143 extern __sfr __at (PIR2_ADDR) PIR2;
144 extern __sfr __at (TMR1L_ADDR) TMR1L;
145 extern __sfr __at (TMR1H_ADDR) TMR1H;
146 extern __sfr __at (T1CON_ADDR) T1CON;
147 extern __sfr __at (TMR2_ADDR) TMR2;
148 extern __sfr __at (T2CON_ADDR) T2CON;
149 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
150 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
151 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
152 extern __sfr __at (RCSTA_ADDR) RCSTA;
153 extern __sfr __at (TXREG_ADDR) TXREG;
154 extern __sfr __at (RCREG_ADDR) RCREG;
155 extern __sfr __at (ADRESH_ADDR) ADRESH;
156 extern __sfr __at (ADCON0_ADDR) ADCON0;
158 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
159 extern __sfr __at (TRISA_ADDR) TRISA;
160 extern __sfr __at (TRISB_ADDR) TRISB;
161 extern __sfr __at (TRISC_ADDR) TRISC;
162 extern __sfr __at (TRISD_ADDR) TRISD;
163 extern __sfr __at (TRISE_ADDR) TRISE;
164 extern __sfr __at (PIE1_ADDR) PIE1;
165 extern __sfr __at (PIE2_ADDR) PIE2;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (PR2_ADDR) PR2;
168 extern __sfr __at (TXSTA_ADDR) TXSTA;
169 extern __sfr __at (SPBRG_ADDR) SPBRG;
170 extern __sfr __at (ADRESL_ADDR) ADRESL;
171 extern __sfr __at (ADCON1_ADDR) ADCON1;
173 extern __sfr __at (EEDATA_ADDR) EEDATA;
174 extern __sfr __at (EEADR_ADDR) EEADR;
175 extern __sfr __at (EEDATH_ADDR) EEDATH;
176 extern __sfr __at (EEADRH_ADDR) EEADRH;
178 extern __sfr __at (EECON1_ADDR) EECON1;
179 extern __sfr __at (EECON2_ADDR) EECON2;
181 //----- STATUS Bits --------------------------------------------------------
184 //----- OPTION Bits ----------------------------------------------------
187 //----- INTCON Bits --------------------------------------------------------
190 //----- PIE1 Bits ----------------------------------------------------------
193 //----- PIR1 Bits ----------------------------------------------------------
196 //----- PIE2 Bits ----------------------------------------------------------
199 //----- PIR2 Bits ----------------------------------------------------------
203 //----- PCON Bits ----------------------------------------------------------
207 //----- TRISE Bits ---------------------------------------------------------
210 //----- EECON1 Bits --------------------------------------------------------
213 //----- T1CON Bits ---------------------------------------------------------
216 //----- T2CON Bits ---------------------------------------------------------
219 //----- CCP1CON Bits -------------------------------------------------------
223 //----- TXSTA Bits ---------------------------------------------------------
227 //----- RCSTA Bits ---------------------------------------------------------
230 //----- ADCON0 Bits --------------------------------------------------------
233 //----- ADCON1 Bits --------------------------------------------------------
236 //==========================================================================
240 //==========================================================================
243 // __BADRAM H'13'-H'14', H'1B'-H'1D'
244 // __BADRAM H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF'
245 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
246 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF'
248 //==========================================================================
250 // Configuration Bits
252 //==========================================================================
254 #define _CP_ALL 0x0FCF
255 #define _CP_OFF 0x3FFF
256 #define _DEBUG_ON 0x37FF
257 #define _DEBUG_OFF 0x3FFF
258 #define _WRT_ENABLE_ON 0x3FFF
259 #define _WRT_ENABLE_OFF 0x3DFF
260 #define _CPD_ON 0x3EFF
261 #define _CPD_OFF 0x3FFF
262 #define _LVP_ON 0x3FFF
263 #define _LVP_OFF 0x3F7F
264 #define _BODEN_ON 0x3FFF
265 #define _BODEN_OFF 0x3FBF
266 #define _PWRTE_OFF 0x3FFF
267 #define _PWRTE_ON 0x3FF7
268 #define _WDT_ON 0x3FFF
269 #define _WDT_OFF 0x3FFB
270 #define _LP_OSC 0x3FFC
271 #define _XT_OSC 0x3FFD
272 #define _HS_OSC 0x3FFE
273 #define _RC_OSC 0x3FFF
277 // ----- ADCON0 bits --------------------
280 unsigned char ADON:1;
283 unsigned char CHS0:1;
284 unsigned char CHS1:1;
285 unsigned char CHS2:1;
286 unsigned char ADCS0:1;
287 unsigned char ADCS1:1;
292 unsigned char NOT_DONE:1;
302 unsigned char GO_DONE:1;
310 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
312 #define ADON ADCON0_bits.ADON
313 #define GO ADCON0_bits.GO
314 #define NOT_DONE ADCON0_bits.NOT_DONE
315 #define GO_DONE ADCON0_bits.GO_DONE
316 #define CHS0 ADCON0_bits.CHS0
317 #define CHS1 ADCON0_bits.CHS1
318 #define CHS2 ADCON0_bits.CHS2
319 #define ADCS0 ADCON0_bits.ADCS0
320 #define ADCS1 ADCON0_bits.ADCS1
322 // ----- ADCON1 bits --------------------
325 unsigned char PCFG0:1;
326 unsigned char PCFG1:1;
327 unsigned char PCFG2:1;
328 unsigned char PCFG3:1;
332 unsigned char ADFM:1;
335 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
337 #define PCFG0 ADCON1_bits.PCFG0
338 #define PCFG1 ADCON1_bits.PCFG1
339 #define PCFG2 ADCON1_bits.PCFG2
340 #define PCFG3 ADCON1_bits.PCFG3
341 #define ADFM ADCON1_bits.ADFM
343 // ----- CCP1CON bits --------------------
346 unsigned char CCP1M0:1;
347 unsigned char CCP1M1:1;
348 unsigned char CCP1M2:1;
349 unsigned char CCP1M3:1;
350 unsigned char CCP1Y:1;
351 unsigned char CCP1X:1;
356 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
358 #define CCP1M0 CCP1CON_bits.CCP1M0
359 #define CCP1M1 CCP1CON_bits.CCP1M1
360 #define CCP1M2 CCP1CON_bits.CCP1M2
361 #define CCP1M3 CCP1CON_bits.CCP1M3
362 #define CCP1Y CCP1CON_bits.CCP1Y
363 #define CCP1X CCP1CON_bits.CCP1X
365 // ----- EECON1 bits --------------------
370 unsigned char WREN:1;
371 unsigned char WRERR:1;
375 unsigned char EEPGD:1;
378 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
380 #define RD EECON1_bits.RD
381 #define WR EECON1_bits.WR
382 #define WREN EECON1_bits.WREN
383 #define WRERR EECON1_bits.WRERR
384 #define EEPGD EECON1_bits.EEPGD
386 // ----- INTCON bits --------------------
389 unsigned char RBIF:1;
390 unsigned char INTF:1;
391 unsigned char T0IF:1;
392 unsigned char RBIE:1;
393 unsigned char INTE:1;
394 unsigned char T0IE:1;
395 unsigned char PEIE:1;
399 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
401 #define RBIF INTCON_bits.RBIF
402 #define INTF INTCON_bits.INTF
403 #define T0IF INTCON_bits.T0IF
404 #define RBIE INTCON_bits.RBIE
405 #define INTE INTCON_bits.INTE
406 #define T0IE INTCON_bits.T0IE
407 #define PEIE INTCON_bits.PEIE
408 #define GIE INTCON_bits.GIE
410 // ----- OPTION_REG bits --------------------
417 unsigned char T0SE:1;
418 unsigned char T0CS:1;
419 unsigned char INTEDG:1;
420 unsigned char NOT_RBPU:1;
422 } __OPTION_REG_bits_t;
423 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
425 #define PS0 OPTION_REG_bits.PS0
426 #define PS1 OPTION_REG_bits.PS1
427 #define PS2 OPTION_REG_bits.PS2
428 #define PSA OPTION_REG_bits.PSA
429 #define T0SE OPTION_REG_bits.T0SE
430 #define T0CS OPTION_REG_bits.T0CS
431 #define INTEDG OPTION_REG_bits.INTEDG
432 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
434 // ----- PCON bits --------------------
437 unsigned char NOT_BO:1;
438 unsigned char NOT_POR:1;
447 unsigned char NOT_BOR:1;
457 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
459 #define NOT_BO PCON_bits.NOT_BO
460 #define NOT_BOR PCON_bits.NOT_BOR
461 #define NOT_POR PCON_bits.NOT_POR
463 // ----- PIE1 bits --------------------
466 unsigned char TMR1IE:1;
467 unsigned char TMR2IE:1;
468 unsigned char CCP1IE:1;
470 unsigned char TXIE:1;
471 unsigned char RCIE:1;
472 unsigned char ADIE:1;
473 unsigned char PSPIE:1;
476 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
478 #define TMR1IE PIE1_bits.TMR1IE
479 #define TMR2IE PIE1_bits.TMR2IE
480 #define CCP1IE PIE1_bits.CCP1IE
481 #define TXIE PIE1_bits.TXIE
482 #define RCIE PIE1_bits.RCIE
483 #define ADIE PIE1_bits.ADIE
484 #define PSPIE PIE1_bits.PSPIE
486 // ----- PIE2 bits --------------------
493 unsigned char EEIE:1;
499 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
501 #define EEIE PIE2_bits.EEIE
503 // ----- PIR1 bits --------------------
506 unsigned char TMR1IF:1;
507 unsigned char TMR2IF:1;
508 unsigned char CCP1IF:1;
510 unsigned char TXIF:1;
511 unsigned char RCIF:1;
512 unsigned char ADIF:1;
513 unsigned char PSPIF:1;
516 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
518 #define TMR1IF PIR1_bits.TMR1IF
519 #define TMR2IF PIR1_bits.TMR2IF
520 #define CCP1IF PIR1_bits.CCP1IF
521 #define TXIF PIR1_bits.TXIF
522 #define RCIF PIR1_bits.RCIF
523 #define ADIF PIR1_bits.ADIF
524 #define PSPIF PIR1_bits.PSPIF
526 // ----- PIR2 bits --------------------
533 unsigned char EEIF:1;
539 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
541 #define EEIF PIR2_bits.EEIF
543 // ----- RCSTA bits --------------------
546 unsigned char RX9D:1;
547 unsigned char OERR:1;
548 unsigned char FERR:1;
549 unsigned char ADDEN:1;
550 unsigned char CREN:1;
551 unsigned char SREN:1;
553 unsigned char SPEN:1;
556 unsigned char RCD8:1;
572 unsigned char NOT_RC8:1;
582 unsigned char RC8_9:1;
586 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
588 #define RX9D RCSTA_bits.RX9D
589 #define RCD8 RCSTA_bits.RCD8
590 #define OERR RCSTA_bits.OERR
591 #define FERR RCSTA_bits.FERR
592 #define ADDEN RCSTA_bits.ADDEN
593 #define CREN RCSTA_bits.CREN
594 #define SREN RCSTA_bits.SREN
595 #define RX9 RCSTA_bits.RX9
596 #define RC9 RCSTA_bits.RC9
597 #define NOT_RC8 RCSTA_bits.NOT_RC8
598 #define RC8_9 RCSTA_bits.RC8_9
599 #define SPEN RCSTA_bits.SPEN
601 // ----- STATUS bits --------------------
607 unsigned char NOT_PD:1;
608 unsigned char NOT_TO:1;
614 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
616 #define C STATUS_bits.C
617 #define DC STATUS_bits.DC
618 #define Z STATUS_bits.Z
619 #define NOT_PD STATUS_bits.NOT_PD
620 #define NOT_TO STATUS_bits.NOT_TO
621 #define RP0 STATUS_bits.RP0
622 #define RP1 STATUS_bits.RP1
623 #define IRP STATUS_bits.IRP
625 // ----- T1CON bits --------------------
628 unsigned char TMR1ON:1;
629 unsigned char TMR1CS:1;
630 unsigned char NOT_T1SYNC:1;
631 unsigned char T1OSCEN:1;
632 unsigned char T1CKPS0:1;
633 unsigned char T1CKPS1:1;
640 unsigned char T1INSYNC:1;
650 unsigned char T1SYNC:1;
658 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
660 #define TMR1ON T1CON_bits.TMR1ON
661 #define TMR1CS T1CON_bits.TMR1CS
662 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
663 #define T1INSYNC T1CON_bits.T1INSYNC
664 #define T1SYNC T1CON_bits.T1SYNC
665 #define T1OSCEN T1CON_bits.T1OSCEN
666 #define T1CKPS0 T1CON_bits.T1CKPS0
667 #define T1CKPS1 T1CON_bits.T1CKPS1
669 // ----- T2CON bits --------------------
672 unsigned char T2CKPS0:1;
673 unsigned char T2CKPS1:1;
674 unsigned char TMR2ON:1;
675 unsigned char TOUTPS0:1;
676 unsigned char TOUTPS1:1;
677 unsigned char TOUTPS2:1;
678 unsigned char TOUTPS3:1;
682 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
684 #define T2CKPS0 T2CON_bits.T2CKPS0
685 #define T2CKPS1 T2CON_bits.T2CKPS1
686 #define TMR2ON T2CON_bits.TMR2ON
687 #define TOUTPS0 T2CON_bits.TOUTPS0
688 #define TOUTPS1 T2CON_bits.TOUTPS1
689 #define TOUTPS2 T2CON_bits.TOUTPS2
690 #define TOUTPS3 T2CON_bits.TOUTPS3
692 // ----- TRISE bits --------------------
695 unsigned char TRISE0:1;
696 unsigned char TRISE1:1;
697 unsigned char TRISE2:1;
699 unsigned char PSPMODE:1;
700 unsigned char IBOV:1;
705 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
707 #define TRISE0 TRISE_bits.TRISE0
708 #define TRISE1 TRISE_bits.TRISE1
709 #define TRISE2 TRISE_bits.TRISE2
710 #define PSPMODE TRISE_bits.PSPMODE
711 #define IBOV TRISE_bits.IBOV
712 #define OBF TRISE_bits.OBF
713 #define IBF TRISE_bits.IBF
715 // ----- TXSTA bits --------------------
718 unsigned char TX9D:1;
719 unsigned char TRMT:1;
720 unsigned char BRGH:1;
722 unsigned char SYNC:1;
723 unsigned char TXEN:1;
725 unsigned char CSRC:1;
728 unsigned char TXD8:1;
734 unsigned char NOT_TX8:1;
744 unsigned char TX8_9:1;
748 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
750 #define TX9D TXSTA_bits.TX9D
751 #define TXD8 TXSTA_bits.TXD8
752 #define TRMT TXSTA_bits.TRMT
753 #define BRGH TXSTA_bits.BRGH
754 #define SYNC TXSTA_bits.SYNC
755 #define TXEN TXSTA_bits.TXEN
756 #define TX9 TXSTA_bits.TX9
757 #define NOT_TX8 TXSTA_bits.NOT_TX8
758 #define TX8_9 TXSTA_bits.TX8_9
759 #define CSRC TXSTA_bits.CSRC