2 // Register Declarations for Microchip 16F871 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define ADRESH_ADDR 0x001E
54 #define ADCON0_ADDR 0x001F
55 #define OPTION_REG_ADDR 0x0081
56 #define TRISA_ADDR 0x0085
57 #define TRISB_ADDR 0x0086
58 #define TRISC_ADDR 0x0087
59 #define TRISD_ADDR 0x0088
60 #define TRISE_ADDR 0x0089
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define PR2_ADDR 0x0092
65 #define TXSTA_ADDR 0x0098
66 #define SPBRG_ADDR 0x0099
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDATA_ADDR 0x010C
70 #define EEADR_ADDR 0x010D
71 #define EEDATH_ADDR 0x010E
72 #define EEADRH_ADDR 0x010F
73 #define EECON1_ADDR 0x018C
74 #define EECON2_ADDR 0x018D
77 // Memory organization.
80 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
81 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
82 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
83 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
84 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
85 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
86 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
87 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
88 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
89 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
90 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
91 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
92 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
93 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
94 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
95 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
96 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
97 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
98 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
99 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
100 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
101 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
102 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
103 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
104 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
105 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
106 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
107 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
108 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
109 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
110 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
111 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
112 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
113 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
114 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
115 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
116 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
117 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
118 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
119 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
120 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
121 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
122 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
123 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
124 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
125 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
126 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
130 // P16F871.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
133 // This header file defines configurations, registers, and other useful bits of
134 // information for the PIC16F871 microcontroller. These names are taken to match
135 // the data sheets as closely as possible.
137 // Note that the processor must be selected before this file is
138 // included. The processor may be selected the following ways:
140 // 1. Command line switch:
141 // C:\ MPASM MYFILE.ASM /PIC16F871
142 // 2. LIST directive in the source file
144 // 3. Processor Type entry in the MPASM full-screen interface
146 //==========================================================================
150 //==========================================================================
154 //1.00 08/07/98 Initial Release - cloned from 16F873
156 //==========================================================================
160 //==========================================================================
163 // MESSG "Processor-header file mismatch. Verify selected processor."
166 //==========================================================================
168 // Register Definitions
170 //==========================================================================
175 //----- Register Files------------------------------------------------------
177 extern data __at (INDF_ADDR) volatile char INDF;
178 extern sfr __at (TMR0_ADDR) TMR0;
179 extern data __at (PCL_ADDR) volatile char PCL;
180 extern sfr __at (STATUS_ADDR) STATUS;
181 extern sfr __at (FSR_ADDR) FSR;
182 extern sfr __at (PORTA_ADDR) PORTA;
183 extern sfr __at (PORTB_ADDR) PORTB;
184 extern sfr __at (PORTC_ADDR) PORTC;
185 extern sfr __at (PORTD_ADDR) PORTD;
186 extern sfr __at (PORTE_ADDR) PORTE;
187 extern sfr __at (PCLATH_ADDR) PCLATH;
188 extern sfr __at (INTCON_ADDR) INTCON;
189 extern sfr __at (PIR1_ADDR) PIR1;
190 extern sfr __at (PIR2_ADDR) PIR2;
191 extern sfr __at (TMR1L_ADDR) TMR1L;
192 extern sfr __at (TMR1H_ADDR) TMR1H;
193 extern sfr __at (T1CON_ADDR) T1CON;
194 extern sfr __at (TMR2_ADDR) TMR2;
195 extern sfr __at (T2CON_ADDR) T2CON;
196 extern sfr __at (CCPR1L_ADDR) CCPR1L;
197 extern sfr __at (CCPR1H_ADDR) CCPR1H;
198 extern sfr __at (CCP1CON_ADDR) CCP1CON;
199 extern sfr __at (RCSTA_ADDR) RCSTA;
200 extern sfr __at (TXREG_ADDR) TXREG;
201 extern sfr __at (RCREG_ADDR) RCREG;
202 extern sfr __at (ADRESH_ADDR) ADRESH;
203 extern sfr __at (ADCON0_ADDR) ADCON0;
205 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
206 extern sfr __at (TRISA_ADDR) TRISA;
207 extern sfr __at (TRISB_ADDR) TRISB;
208 extern sfr __at (TRISC_ADDR) TRISC;
209 extern sfr __at (TRISD_ADDR) TRISD;
210 extern sfr __at (TRISE_ADDR) TRISE;
211 extern sfr __at (PIE1_ADDR) PIE1;
212 extern sfr __at (PIE2_ADDR) PIE2;
213 extern sfr __at (PCON_ADDR) PCON;
214 extern sfr __at (PR2_ADDR) PR2;
215 extern sfr __at (TXSTA_ADDR) TXSTA;
216 extern sfr __at (SPBRG_ADDR) SPBRG;
217 extern sfr __at (ADRESL_ADDR) ADRESL;
218 extern sfr __at (ADCON1_ADDR) ADCON1;
220 extern sfr __at (EEDATA_ADDR) EEDATA;
221 extern sfr __at (EEADR_ADDR) EEADR;
222 extern sfr __at (EEDATH_ADDR) EEDATH;
223 extern sfr __at (EEADRH_ADDR) EEADRH;
225 extern sfr __at (EECON1_ADDR) EECON1;
226 extern sfr __at (EECON2_ADDR) EECON2;
228 //----- STATUS Bits --------------------------------------------------------
231 //----- OPTION Bits ----------------------------------------------------
234 //----- INTCON Bits --------------------------------------------------------
237 //----- PIE1 Bits ----------------------------------------------------------
240 //----- PIR1 Bits ----------------------------------------------------------
243 //----- PIE2 Bits ----------------------------------------------------------
246 //----- PIR2 Bits ----------------------------------------------------------
250 //----- PCON Bits ----------------------------------------------------------
254 //----- TRISE Bits ---------------------------------------------------------
257 //----- EECON1 Bits --------------------------------------------------------
260 //----- T1CON Bits ---------------------------------------------------------
263 //----- T2CON Bits ---------------------------------------------------------
266 //----- CCP1CON Bits -------------------------------------------------------
270 //----- TXSTA Bits ---------------------------------------------------------
274 //----- RCSTA Bits ---------------------------------------------------------
277 //----- ADCON0 Bits --------------------------------------------------------
280 //----- ADCON1 Bits --------------------------------------------------------
283 //==========================================================================
287 //==========================================================================
290 // __BADRAM H'13'-H'14', H'1B'-H'1D'
291 // __BADRAM H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF'
292 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
293 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF'
295 //==========================================================================
297 // Configuration Bits
299 //==========================================================================
301 #define _CP_ALL 0x0FCF
302 #define _CP_OFF 0x3FFF
303 #define _DEBUG_ON 0x37FF
304 #define _DEBUG_OFF 0x3FFF
305 #define _WRT_ENABLE_ON 0x3FFF
306 #define _WRT_ENABLE_OFF 0x3DFF
307 #define _CPD_ON 0x3EFF
308 #define _CPD_OFF 0x3FFF
309 #define _LVP_ON 0x3FFF
310 #define _LVP_OFF 0x3F7F
311 #define _BODEN_ON 0x3FFF
312 #define _BODEN_OFF 0x3FBF
313 #define _PWRTE_OFF 0x3FFF
314 #define _PWRTE_ON 0x3FF7
315 #define _WDT_ON 0x3FFF
316 #define _WDT_OFF 0x3FFB
317 #define _LP_OSC 0x3FFC
318 #define _XT_OSC 0x3FFD
319 #define _HS_OSC 0x3FFE
320 #define _RC_OSC 0x3FFF
324 // ----- ADCON0 bits --------------------
327 unsigned char ADON:1;
330 unsigned char CHS0:1;
331 unsigned char CHS1:1;
332 unsigned char CHS2:1;
333 unsigned char ADCS0:1;
334 unsigned char ADCS1:1;
339 unsigned char NOT_DONE:1;
349 unsigned char GO_DONE:1;
357 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
359 #define ADON ADCON0_bits.ADON
360 #define GO ADCON0_bits.GO
361 #define NOT_DONE ADCON0_bits.NOT_DONE
362 #define GO_DONE ADCON0_bits.GO_DONE
363 #define CHS0 ADCON0_bits.CHS0
364 #define CHS1 ADCON0_bits.CHS1
365 #define CHS2 ADCON0_bits.CHS2
366 #define ADCS0 ADCON0_bits.ADCS0
367 #define ADCS1 ADCON0_bits.ADCS1
369 // ----- ADCON1 bits --------------------
372 unsigned char PCFG0:1;
373 unsigned char PCFG1:1;
374 unsigned char PCFG2:1;
375 unsigned char PCFG3:1;
379 unsigned char ADFM:1;
382 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
384 #define PCFG0 ADCON1_bits.PCFG0
385 #define PCFG1 ADCON1_bits.PCFG1
386 #define PCFG2 ADCON1_bits.PCFG2
387 #define PCFG3 ADCON1_bits.PCFG3
388 #define ADFM ADCON1_bits.ADFM
390 // ----- CCP1CON bits --------------------
393 unsigned char CCP1M0:1;
394 unsigned char CCP1M1:1;
395 unsigned char CCP1M2:1;
396 unsigned char CCP1M3:1;
397 unsigned char CCP1Y:1;
398 unsigned char CCP1X:1;
403 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
405 #define CCP1M0 CCP1CON_bits.CCP1M0
406 #define CCP1M1 CCP1CON_bits.CCP1M1
407 #define CCP1M2 CCP1CON_bits.CCP1M2
408 #define CCP1M3 CCP1CON_bits.CCP1M3
409 #define CCP1Y CCP1CON_bits.CCP1Y
410 #define CCP1X CCP1CON_bits.CCP1X
412 // ----- EECON1 bits --------------------
417 unsigned char WREN:1;
418 unsigned char WRERR:1;
422 unsigned char EEPGD:1;
425 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
427 #define RD EECON1_bits.RD
428 #define WR EECON1_bits.WR
429 #define WREN EECON1_bits.WREN
430 #define WRERR EECON1_bits.WRERR
431 #define EEPGD EECON1_bits.EEPGD
433 // ----- INTCON bits --------------------
436 unsigned char RBIF:1;
437 unsigned char INTF:1;
438 unsigned char T0IF:1;
439 unsigned char RBIE:1;
440 unsigned char INTE:1;
441 unsigned char T0IE:1;
442 unsigned char PEIE:1;
446 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
448 #define RBIF INTCON_bits.RBIF
449 #define INTF INTCON_bits.INTF
450 #define T0IF INTCON_bits.T0IF
451 #define RBIE INTCON_bits.RBIE
452 #define INTE INTCON_bits.INTE
453 #define T0IE INTCON_bits.T0IE
454 #define PEIE INTCON_bits.PEIE
455 #define GIE INTCON_bits.GIE
457 // ----- OPTION_REG bits --------------------
464 unsigned char T0SE:1;
465 unsigned char T0CS:1;
466 unsigned char INTEDG:1;
467 unsigned char NOT_RBPU:1;
469 } __OPTION_REG_bits_t;
470 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
472 #define PS0 OPTION_REG_bits.PS0
473 #define PS1 OPTION_REG_bits.PS1
474 #define PS2 OPTION_REG_bits.PS2
475 #define PSA OPTION_REG_bits.PSA
476 #define T0SE OPTION_REG_bits.T0SE
477 #define T0CS OPTION_REG_bits.T0CS
478 #define INTEDG OPTION_REG_bits.INTEDG
479 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
481 // ----- PCON bits --------------------
484 unsigned char NOT_BO:1;
485 unsigned char NOT_POR:1;
494 unsigned char NOT_BOR:1;
504 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
506 #define NOT_BO PCON_bits.NOT_BO
507 #define NOT_BOR PCON_bits.NOT_BOR
508 #define NOT_POR PCON_bits.NOT_POR
510 // ----- PIE1 bits --------------------
513 unsigned char TMR1IE:1;
514 unsigned char TMR2IE:1;
515 unsigned char CCP1IE:1;
517 unsigned char TXIE:1;
518 unsigned char RCIE:1;
519 unsigned char ADIE:1;
520 unsigned char PSPIE:1;
523 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
525 #define TMR1IE PIE1_bits.TMR1IE
526 #define TMR2IE PIE1_bits.TMR2IE
527 #define CCP1IE PIE1_bits.CCP1IE
528 #define TXIE PIE1_bits.TXIE
529 #define RCIE PIE1_bits.RCIE
530 #define ADIE PIE1_bits.ADIE
531 #define PSPIE PIE1_bits.PSPIE
533 // ----- PIE2 bits --------------------
540 unsigned char EEIE:1;
546 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
548 #define EEIE PIE2_bits.EEIE
550 // ----- PIR1 bits --------------------
553 unsigned char TMR1IF:1;
554 unsigned char TMR2IF:1;
555 unsigned char CCP1IF:1;
557 unsigned char TXIF:1;
558 unsigned char RCIF:1;
559 unsigned char ADIF:1;
560 unsigned char PSPIF:1;
563 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
565 #define TMR1IF PIR1_bits.TMR1IF
566 #define TMR2IF PIR1_bits.TMR2IF
567 #define CCP1IF PIR1_bits.CCP1IF
568 #define TXIF PIR1_bits.TXIF
569 #define RCIF PIR1_bits.RCIF
570 #define ADIF PIR1_bits.ADIF
571 #define PSPIF PIR1_bits.PSPIF
573 // ----- PIR2 bits --------------------
580 unsigned char EEIF:1;
586 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
588 #define EEIF PIR2_bits.EEIF
590 // ----- RCSTA bits --------------------
593 unsigned char RX9D:1;
594 unsigned char OERR:1;
595 unsigned char FERR:1;
596 unsigned char ADDEN:1;
597 unsigned char CREN:1;
598 unsigned char SREN:1;
600 unsigned char SPEN:1;
603 unsigned char RCD8:1;
619 unsigned char NOT_RC8:1;
629 unsigned char RC8_9:1;
633 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
635 #define RX9D RCSTA_bits.RX9D
636 #define RCD8 RCSTA_bits.RCD8
637 #define OERR RCSTA_bits.OERR
638 #define FERR RCSTA_bits.FERR
639 #define ADDEN RCSTA_bits.ADDEN
640 #define CREN RCSTA_bits.CREN
641 #define SREN RCSTA_bits.SREN
642 #define RX9 RCSTA_bits.RX9
643 #define RC9 RCSTA_bits.RC9
644 #define NOT_RC8 RCSTA_bits.NOT_RC8
645 #define RC8_9 RCSTA_bits.RC8_9
646 #define SPEN RCSTA_bits.SPEN
648 // ----- STATUS bits --------------------
654 unsigned char NOT_PD:1;
655 unsigned char NOT_TO:1;
661 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
663 #define C STATUS_bits.C
664 #define DC STATUS_bits.DC
665 #define Z STATUS_bits.Z
666 #define NOT_PD STATUS_bits.NOT_PD
667 #define NOT_TO STATUS_bits.NOT_TO
668 #define RP0 STATUS_bits.RP0
669 #define RP1 STATUS_bits.RP1
670 #define IRP STATUS_bits.IRP
672 // ----- T1CON bits --------------------
675 unsigned char TMR1ON:1;
676 unsigned char TMR1CS:1;
677 unsigned char NOT_T1SYNC:1;
678 unsigned char T1OSCEN:1;
679 unsigned char T1CKPS0:1;
680 unsigned char T1CKPS1:1;
687 unsigned char T1INSYNC:1;
697 unsigned char T1SYNC:1;
705 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
707 #define TMR1ON T1CON_bits.TMR1ON
708 #define TMR1CS T1CON_bits.TMR1CS
709 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
710 #define T1INSYNC T1CON_bits.T1INSYNC
711 #define T1SYNC T1CON_bits.T1SYNC
712 #define T1OSCEN T1CON_bits.T1OSCEN
713 #define T1CKPS0 T1CON_bits.T1CKPS0
714 #define T1CKPS1 T1CON_bits.T1CKPS1
716 // ----- T2CON bits --------------------
719 unsigned char T2CKPS0:1;
720 unsigned char T2CKPS1:1;
721 unsigned char TMR2ON:1;
722 unsigned char TOUTPS0:1;
723 unsigned char TOUTPS1:1;
724 unsigned char TOUTPS2:1;
725 unsigned char TOUTPS3:1;
729 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
731 #define T2CKPS0 T2CON_bits.T2CKPS0
732 #define T2CKPS1 T2CON_bits.T2CKPS1
733 #define TMR2ON T2CON_bits.TMR2ON
734 #define TOUTPS0 T2CON_bits.TOUTPS0
735 #define TOUTPS1 T2CON_bits.TOUTPS1
736 #define TOUTPS2 T2CON_bits.TOUTPS2
737 #define TOUTPS3 T2CON_bits.TOUTPS3
739 // ----- TRISE bits --------------------
742 unsigned char TRISE0:1;
743 unsigned char TRISE1:1;
744 unsigned char TRISE2:1;
746 unsigned char PSPMODE:1;
747 unsigned char IBOV:1;
752 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
754 #define TRISE0 TRISE_bits.TRISE0
755 #define TRISE1 TRISE_bits.TRISE1
756 #define TRISE2 TRISE_bits.TRISE2
757 #define PSPMODE TRISE_bits.PSPMODE
758 #define IBOV TRISE_bits.IBOV
759 #define OBF TRISE_bits.OBF
760 #define IBF TRISE_bits.IBF
762 // ----- TXSTA bits --------------------
765 unsigned char TX9D:1;
766 unsigned char TRMT:1;
767 unsigned char BRGH:1;
769 unsigned char SYNC:1;
770 unsigned char TXEN:1;
772 unsigned char CSRC:1;
775 unsigned char TXD8:1;
781 unsigned char NOT_TX8:1;
791 unsigned char TX8_9:1;
795 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
797 #define TX9D TXSTA_bits.TX9D
798 #define TXD8 TXSTA_bits.TXD8
799 #define TRMT TXSTA_bits.TRMT
800 #define BRGH TXSTA_bits.BRGH
801 #define SYNC TXSTA_bits.SYNC
802 #define TXEN TXSTA_bits.TXEN
803 #define TX9 TXSTA_bits.TX9
804 #define NOT_TX8 TXSTA_bits.NOT_TX8
805 #define TX8_9 TXSTA_bits.TX8_9
806 #define CSRC TXSTA_bits.CSRC