2 // Register Declarations for Microchip 16F870 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define RCSTA_ADDR 0x0018
49 #define TXREG_ADDR 0x0019
50 #define RCREG_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISB_ADDR 0x0086
56 #define TRISC_ADDR 0x0087
57 #define PIE1_ADDR 0x008C
58 #define PIE2_ADDR 0x008D
59 #define PCON_ADDR 0x008E
60 #define PR2_ADDR 0x0092
61 #define TXSTA_ADDR 0x0098
62 #define SPBRG_ADDR 0x0099
63 #define ADRESL_ADDR 0x009E
64 #define ADCON1_ADDR 0x009F
65 #define EEDATA_ADDR 0x010C
66 #define EEADR_ADDR 0x010D
67 #define EEDATH_ADDR 0x010E
68 #define EEADRH_ADDR 0x010F
69 #define EECON1_ADDR 0x018C
70 #define EECON2_ADDR 0x018D
73 // Memory organization.
76 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
77 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
78 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
79 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
80 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
81 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
82 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
83 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
84 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
85 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
86 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
87 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
88 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
89 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
90 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
91 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
92 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
93 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
94 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
95 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
96 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
97 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
98 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
99 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
100 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
101 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
102 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
103 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
104 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
105 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
106 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
107 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
108 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
109 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
110 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
111 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
112 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
113 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
114 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
115 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
116 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
117 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
118 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
122 // P16F870.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
125 // This header file defines configurations, registers, and other useful bits of
126 // information for the PIC16F870 microcontroller. These names are taken to match
127 // the data sheets as closely as possible.
129 // Note that the processor must be selected before this file is
130 // included. The processor may be selected the following ways:
132 // 1. Command line switch:
133 // C:\ MPASM MYFILE.ASM /PIC16F870
134 // 2. LIST directive in the source file
136 // 3. Processor Type entry in the MPASM full-screen interface
138 //==========================================================================
142 //==========================================================================
146 //1.00 08/07/98 Initial Release - cloned from 16F873
148 //==========================================================================
152 //==========================================================================
155 // MESSG "Processor-header file mismatch. Verify selected processor."
158 //==========================================================================
160 // Register Definitions
162 //==========================================================================
167 //----- Register Files------------------------------------------------------
169 extern data __at (INDF_ADDR) volatile char INDF;
170 extern sfr __at (TMR0_ADDR) TMR0;
171 extern data __at (PCL_ADDR) volatile char PCL;
172 extern sfr __at (STATUS_ADDR) STATUS;
173 extern sfr __at (FSR_ADDR) FSR;
174 extern sfr __at (PORTA_ADDR) PORTA;
175 extern sfr __at (PORTB_ADDR) PORTB;
176 extern sfr __at (PORTC_ADDR) PORTC;
177 extern sfr __at (PCLATH_ADDR) PCLATH;
178 extern sfr __at (INTCON_ADDR) INTCON;
179 extern sfr __at (PIR1_ADDR) PIR1;
180 extern sfr __at (PIR2_ADDR) PIR2;
181 extern sfr __at (TMR1L_ADDR) TMR1L;
182 extern sfr __at (TMR1H_ADDR) TMR1H;
183 extern sfr __at (T1CON_ADDR) T1CON;
184 extern sfr __at (TMR2_ADDR) TMR2;
185 extern sfr __at (T2CON_ADDR) T2CON;
186 extern sfr __at (CCPR1L_ADDR) CCPR1L;
187 extern sfr __at (CCPR1H_ADDR) CCPR1H;
188 extern sfr __at (CCP1CON_ADDR) CCP1CON;
189 extern sfr __at (RCSTA_ADDR) RCSTA;
190 extern sfr __at (TXREG_ADDR) TXREG;
191 extern sfr __at (RCREG_ADDR) RCREG;
192 extern sfr __at (ADRESH_ADDR) ADRESH;
193 extern sfr __at (ADCON0_ADDR) ADCON0;
195 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
196 extern sfr __at (TRISA_ADDR) TRISA;
197 extern sfr __at (TRISB_ADDR) TRISB;
198 extern sfr __at (TRISC_ADDR) TRISC;
200 extern sfr __at (PIE1_ADDR) PIE1;
201 extern sfr __at (PIE2_ADDR) PIE2;
202 extern sfr __at (PCON_ADDR) PCON;
203 extern sfr __at (PR2_ADDR) PR2;
204 extern sfr __at (TXSTA_ADDR) TXSTA;
205 extern sfr __at (SPBRG_ADDR) SPBRG;
206 extern sfr __at (ADRESL_ADDR) ADRESL;
207 extern sfr __at (ADCON1_ADDR) ADCON1;
209 extern sfr __at (EEDATA_ADDR) EEDATA;
210 extern sfr __at (EEADR_ADDR) EEADR;
211 extern sfr __at (EEDATH_ADDR) EEDATH;
212 extern sfr __at (EEADRH_ADDR) EEADRH;
214 extern sfr __at (EECON1_ADDR) EECON1;
215 extern sfr __at (EECON2_ADDR) EECON2;
217 //----- STATUS Bits --------------------------------------------------------
220 //----- OPTION Bits ----------------------------------------------------
223 //----- INTCON Bits --------------------------------------------------------
226 //----- PIE1 Bits ----------------------------------------------------------
229 //----- PIR1 Bits ----------------------------------------------------------
232 //----- PIE2 Bits ----------------------------------------------------------
235 //----- PIR2 Bits ----------------------------------------------------------
239 //----- PCON Bits ----------------------------------------------------------
242 //----- EECON1 Bits --------------------------------------------------------
245 //----- T1CON Bits ---------------------------------------------------------
248 //----- T2CON Bits ---------------------------------------------------------
251 //----- CCP1CON Bits -------------------------------------------------------
255 //----- TXSTA Bits ---------------------------------------------------------
259 //----- RCSTA Bits ---------------------------------------------------------
262 //----- ADCON0 Bits --------------------------------------------------------
265 //----- ADCON1 Bits --------------------------------------------------------
268 //==========================================================================
272 //==========================================================================
275 // __BADRAM H'08'-H'09', H'13'-H'14', H'1B'-H'1D'
276 // __BADRAM H'88'-H'89',H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF'
277 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
278 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF'
280 //==========================================================================
282 // Configuration Bits
284 //==========================================================================
286 #define _CP_ALL 0x0FCF
287 #define _CP_OFF 0x3FFF
288 #define _DEBUG_ON 0x37FF
289 #define _DEBUG_OFF 0x3FFF
290 #define _WRT_ENABLE_ON 0x3FFF
291 #define _WRT_ENABLE_OFF 0x3DFF
292 #define _CPD_ON 0x3EFF
293 #define _CPD_OFF 0x3FFF
294 #define _LVP_ON 0x3FFF
295 #define _LVP_OFF 0x3F7F
296 #define _BODEN_ON 0x3FFF
297 #define _BODEN_OFF 0x3FBF
298 #define _PWRTE_OFF 0x3FFF
299 #define _PWRTE_ON 0x3FF7
300 #define _WDT_ON 0x3FFF
301 #define _WDT_OFF 0x3FFB
302 #define _LP_OSC 0x3FFC
303 #define _XT_OSC 0x3FFD
304 #define _HS_OSC 0x3FFE
305 #define _RC_OSC 0x3FFF
309 // ----- ADCON0 bits --------------------
312 unsigned char ADON:1;
315 unsigned char CHS0:1;
316 unsigned char CHS1:1;
317 unsigned char CHS2:1;
318 unsigned char ADCS0:1;
319 unsigned char ADCS1:1;
324 unsigned char NOT_DONE:1;
334 unsigned char GO_DONE:1;
342 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
344 #define ADON ADCON0_bits.ADON
345 #define GO ADCON0_bits.GO
346 #define NOT_DONE ADCON0_bits.NOT_DONE
347 #define GO_DONE ADCON0_bits.GO_DONE
348 #define CHS0 ADCON0_bits.CHS0
349 #define CHS1 ADCON0_bits.CHS1
350 #define CHS2 ADCON0_bits.CHS2
351 #define ADCS0 ADCON0_bits.ADCS0
352 #define ADCS1 ADCON0_bits.ADCS1
354 // ----- ADCON1 bits --------------------
357 unsigned char PCFG0:1;
358 unsigned char PCFG1:1;
359 unsigned char PCFG2:1;
360 unsigned char PCFG3:1;
364 unsigned char ADFM:1;
367 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
369 #define PCFG0 ADCON1_bits.PCFG0
370 #define PCFG1 ADCON1_bits.PCFG1
371 #define PCFG2 ADCON1_bits.PCFG2
372 #define PCFG3 ADCON1_bits.PCFG3
373 #define ADFM ADCON1_bits.ADFM
375 // ----- CCP1CON bits --------------------
378 unsigned char CCP1M0:1;
379 unsigned char CCP1M1:1;
380 unsigned char CCP1M2:1;
381 unsigned char CCP1M3:1;
382 unsigned char CCP1Y:1;
383 unsigned char CCP1X:1;
388 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
390 #define CCP1M0 CCP1CON_bits.CCP1M0
391 #define CCP1M1 CCP1CON_bits.CCP1M1
392 #define CCP1M2 CCP1CON_bits.CCP1M2
393 #define CCP1M3 CCP1CON_bits.CCP1M3
394 #define CCP1Y CCP1CON_bits.CCP1Y
395 #define CCP1X CCP1CON_bits.CCP1X
397 // ----- EECON1 bits --------------------
402 unsigned char WREN:1;
403 unsigned char WRERR:1;
407 unsigned char EEPGD:1;
410 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
412 #define RD EECON1_bits.RD
413 #define WR EECON1_bits.WR
414 #define WREN EECON1_bits.WREN
415 #define WRERR EECON1_bits.WRERR
416 #define EEPGD EECON1_bits.EEPGD
418 // ----- INTCON bits --------------------
421 unsigned char RBIF:1;
422 unsigned char INTF:1;
423 unsigned char T0IF:1;
424 unsigned char RBIE:1;
425 unsigned char INTE:1;
426 unsigned char T0IE:1;
427 unsigned char PEIE:1;
431 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
433 #define RBIF INTCON_bits.RBIF
434 #define INTF INTCON_bits.INTF
435 #define T0IF INTCON_bits.T0IF
436 #define RBIE INTCON_bits.RBIE
437 #define INTE INTCON_bits.INTE
438 #define T0IE INTCON_bits.T0IE
439 #define PEIE INTCON_bits.PEIE
440 #define GIE INTCON_bits.GIE
442 // ----- OPTION_REG bits --------------------
449 unsigned char T0SE:1;
450 unsigned char T0CS:1;
451 unsigned char INTEDG:1;
452 unsigned char NOT_RBPU:1;
454 } __OPTION_REG_bits_t;
455 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
457 #define PS0 OPTION_REG_bits.PS0
458 #define PS1 OPTION_REG_bits.PS1
459 #define PS2 OPTION_REG_bits.PS2
460 #define PSA OPTION_REG_bits.PSA
461 #define T0SE OPTION_REG_bits.T0SE
462 #define T0CS OPTION_REG_bits.T0CS
463 #define INTEDG OPTION_REG_bits.INTEDG
464 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
466 // ----- PCON bits --------------------
469 unsigned char NOT_BO:1;
470 unsigned char NOT_POR:1;
479 unsigned char NOT_BOR:1;
489 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
491 #define NOT_BO PCON_bits.NOT_BO
492 #define NOT_BOR PCON_bits.NOT_BOR
493 #define NOT_POR PCON_bits.NOT_POR
495 // ----- PIE1 bits --------------------
498 unsigned char TMR1IE:1;
499 unsigned char TMR2IE:1;
500 unsigned char CCP1IE:1;
502 unsigned char TXIE:1;
503 unsigned char RCIE:1;
504 unsigned char ADIE:1;
508 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
510 #define TMR1IE PIE1_bits.TMR1IE
511 #define TMR2IE PIE1_bits.TMR2IE
512 #define CCP1IE PIE1_bits.CCP1IE
513 #define TXIE PIE1_bits.TXIE
514 #define RCIE PIE1_bits.RCIE
515 #define ADIE PIE1_bits.ADIE
517 // ----- PIE2 bits --------------------
524 unsigned char EEIE:1;
530 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
532 #define EEIE PIE2_bits.EEIE
534 // ----- PIR1 bits --------------------
537 unsigned char TMR1IF:1;
538 unsigned char TMR2IF:1;
539 unsigned char CCP1IF:1;
541 unsigned char TXIF:1;
542 unsigned char RCIF:1;
543 unsigned char ADIF:1;
547 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
549 #define TMR1IF PIR1_bits.TMR1IF
550 #define TMR2IF PIR1_bits.TMR2IF
551 #define CCP1IF PIR1_bits.CCP1IF
552 #define TXIF PIR1_bits.TXIF
553 #define RCIF PIR1_bits.RCIF
554 #define ADIF PIR1_bits.ADIF
556 // ----- PIR2 bits --------------------
563 unsigned char EEIF:1;
569 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
571 #define EEIF PIR2_bits.EEIF
573 // ----- RCSTA bits --------------------
576 unsigned char RX9D:1;
577 unsigned char OERR:1;
578 unsigned char FERR:1;
579 unsigned char ADDEN:1;
580 unsigned char CREN:1;
581 unsigned char SREN:1;
583 unsigned char SPEN:1;
586 unsigned char RCD8:1;
602 unsigned char NOT_RC8:1;
612 unsigned char RC8_9:1;
616 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
618 #define RX9D RCSTA_bits.RX9D
619 #define RCD8 RCSTA_bits.RCD8
620 #define OERR RCSTA_bits.OERR
621 #define FERR RCSTA_bits.FERR
622 #define ADDEN RCSTA_bits.ADDEN
623 #define CREN RCSTA_bits.CREN
624 #define SREN RCSTA_bits.SREN
625 #define RX9 RCSTA_bits.RX9
626 #define RC9 RCSTA_bits.RC9
627 #define NOT_RC8 RCSTA_bits.NOT_RC8
628 #define RC8_9 RCSTA_bits.RC8_9
629 #define SPEN RCSTA_bits.SPEN
631 // ----- STATUS bits --------------------
637 unsigned char NOT_PD:1;
638 unsigned char NOT_TO:1;
644 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
646 #define C STATUS_bits.C
647 #define DC STATUS_bits.DC
648 #define Z STATUS_bits.Z
649 #define NOT_PD STATUS_bits.NOT_PD
650 #define NOT_TO STATUS_bits.NOT_TO
651 #define RP0 STATUS_bits.RP0
652 #define RP1 STATUS_bits.RP1
653 #define IRP STATUS_bits.IRP
655 // ----- T1CON bits --------------------
658 unsigned char TMR1ON:1;
659 unsigned char TMR1CS:1;
660 unsigned char NOT_T1SYNC:1;
661 unsigned char T1OSCEN:1;
662 unsigned char T1CKPS0:1;
663 unsigned char T1CKPS1:1;
670 unsigned char T1INSYNC:1;
680 unsigned char T1SYNC:1;
688 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
690 #define TMR1ON T1CON_bits.TMR1ON
691 #define TMR1CS T1CON_bits.TMR1CS
692 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
693 #define T1INSYNC T1CON_bits.T1INSYNC
694 #define T1SYNC T1CON_bits.T1SYNC
695 #define T1OSCEN T1CON_bits.T1OSCEN
696 #define T1CKPS0 T1CON_bits.T1CKPS0
697 #define T1CKPS1 T1CON_bits.T1CKPS1
699 // ----- T2CON bits --------------------
702 unsigned char T2CKPS0:1;
703 unsigned char T2CKPS1:1;
704 unsigned char TMR2ON:1;
705 unsigned char TOUTPS0:1;
706 unsigned char TOUTPS1:1;
707 unsigned char TOUTPS2:1;
708 unsigned char TOUTPS3:1;
712 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
714 #define T2CKPS0 T2CON_bits.T2CKPS0
715 #define T2CKPS1 T2CON_bits.T2CKPS1
716 #define TMR2ON T2CON_bits.TMR2ON
717 #define TOUTPS0 T2CON_bits.TOUTPS0
718 #define TOUTPS1 T2CON_bits.TOUTPS1
719 #define TOUTPS2 T2CON_bits.TOUTPS2
720 #define TOUTPS3 T2CON_bits.TOUTPS3
722 // ----- TXSTA bits --------------------
725 unsigned char TX9D:1;
726 unsigned char TRMT:1;
727 unsigned char BRGH:1;
729 unsigned char SYNC:1;
730 unsigned char TXEN:1;
732 unsigned char CSRC:1;
735 unsigned char TXD8:1;
741 unsigned char NOT_TX8:1;
751 unsigned char TX8_9:1;
755 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
757 #define TX9D TXSTA_bits.TX9D
758 #define TXD8 TXSTA_bits.TXD8
759 #define TRMT TXSTA_bits.TRMT
760 #define BRGH TXSTA_bits.BRGH
761 #define SYNC TXSTA_bits.SYNC
762 #define TXEN TXSTA_bits.TXEN
763 #define TX9 TXSTA_bits.TX9
764 #define NOT_TX8 TXSTA_bits.NOT_TX8
765 #define TX8_9 TXSTA_bits.TX8_9
766 #define CSRC TXSTA_bits.CSRC