2 // Register Declarations for Microchip 16F870 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define RCSTA_ADDR 0x0018
49 #define TXREG_ADDR 0x0019
50 #define RCREG_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISB_ADDR 0x0086
56 #define TRISC_ADDR 0x0087
57 #define PIE1_ADDR 0x008C
58 #define PIE2_ADDR 0x008D
59 #define PCON_ADDR 0x008E
60 #define PR2_ADDR 0x0092
61 #define TXSTA_ADDR 0x0098
62 #define SPBRG_ADDR 0x0099
63 #define ADRESL_ADDR 0x009E
64 #define ADCON1_ADDR 0x009F
65 #define EEDATA_ADDR 0x010C
66 #define EEADR_ADDR 0x010D
67 #define EEDATH_ADDR 0x010E
68 #define EEADRH_ADDR 0x010F
69 #define EECON1_ADDR 0x018C
70 #define EECON2_ADDR 0x018D
73 // Memory organization.
79 // P16F870.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
82 // This header file defines configurations, registers, and other useful bits of
83 // information for the PIC16F870 microcontroller. These names are taken to match
84 // the data sheets as closely as possible.
86 // Note that the processor must be selected before this file is
87 // included. The processor may be selected the following ways:
89 // 1. Command line switch:
90 // C:\ MPASM MYFILE.ASM /PIC16F870
91 // 2. LIST directive in the source file
93 // 3. Processor Type entry in the MPASM full-screen interface
95 //==========================================================================
99 //==========================================================================
103 //1.00 08/07/98 Initial Release - cloned from 16F873
105 //==========================================================================
109 //==========================================================================
112 // MESSG "Processor-header file mismatch. Verify selected processor."
115 //==========================================================================
117 // Register Definitions
119 //==========================================================================
124 //----- Register Files------------------------------------------------------
126 extern __data __at (INDF_ADDR) volatile char INDF;
127 extern __sfr __at (TMR0_ADDR) TMR0;
128 extern __data __at (PCL_ADDR) volatile char PCL;
129 extern __sfr __at (STATUS_ADDR) STATUS;
130 extern __sfr __at (FSR_ADDR) FSR;
131 extern __sfr __at (PORTA_ADDR) PORTA;
132 extern __sfr __at (PORTB_ADDR) PORTB;
133 extern __sfr __at (PORTC_ADDR) PORTC;
134 extern __sfr __at (PCLATH_ADDR) PCLATH;
135 extern __sfr __at (INTCON_ADDR) INTCON;
136 extern __sfr __at (PIR1_ADDR) PIR1;
137 extern __sfr __at (PIR2_ADDR) PIR2;
138 extern __sfr __at (TMR1L_ADDR) TMR1L;
139 extern __sfr __at (TMR1H_ADDR) TMR1H;
140 extern __sfr __at (T1CON_ADDR) T1CON;
141 extern __sfr __at (TMR2_ADDR) TMR2;
142 extern __sfr __at (T2CON_ADDR) T2CON;
143 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
144 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
145 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
146 extern __sfr __at (RCSTA_ADDR) RCSTA;
147 extern __sfr __at (TXREG_ADDR) TXREG;
148 extern __sfr __at (RCREG_ADDR) RCREG;
149 extern __sfr __at (ADRESH_ADDR) ADRESH;
150 extern __sfr __at (ADCON0_ADDR) ADCON0;
152 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
153 extern __sfr __at (TRISA_ADDR) TRISA;
154 extern __sfr __at (TRISB_ADDR) TRISB;
155 extern __sfr __at (TRISC_ADDR) TRISC;
157 extern __sfr __at (PIE1_ADDR) PIE1;
158 extern __sfr __at (PIE2_ADDR) PIE2;
159 extern __sfr __at (PCON_ADDR) PCON;
160 extern __sfr __at (PR2_ADDR) PR2;
161 extern __sfr __at (TXSTA_ADDR) TXSTA;
162 extern __sfr __at (SPBRG_ADDR) SPBRG;
163 extern __sfr __at (ADRESL_ADDR) ADRESL;
164 extern __sfr __at (ADCON1_ADDR) ADCON1;
166 extern __sfr __at (EEDATA_ADDR) EEDATA;
167 extern __sfr __at (EEADR_ADDR) EEADR;
168 extern __sfr __at (EEDATH_ADDR) EEDATH;
169 extern __sfr __at (EEADRH_ADDR) EEADRH;
171 extern __sfr __at (EECON1_ADDR) EECON1;
172 extern __sfr __at (EECON2_ADDR) EECON2;
174 //----- STATUS Bits --------------------------------------------------------
177 //----- OPTION_REG Bits ----------------------------------------------------
180 //----- INTCON Bits --------------------------------------------------------
183 //----- PIE1 Bits ----------------------------------------------------------
186 //----- PIR1 Bits ----------------------------------------------------------
189 //----- PIE2 Bits ----------------------------------------------------------
192 //----- PIR2 Bits ----------------------------------------------------------
196 //----- PCON Bits ----------------------------------------------------------
199 //----- EECON1 Bits --------------------------------------------------------
202 //----- T1CON Bits ---------------------------------------------------------
205 //----- T2CON Bits ---------------------------------------------------------
208 //----- CCP1CON Bits -------------------------------------------------------
212 //----- TXSTA Bits ---------------------------------------------------------
216 //----- RCSTA Bits ---------------------------------------------------------
219 //----- ADCON0 Bits --------------------------------------------------------
222 //----- ADCON1 Bits --------------------------------------------------------
225 //==========================================================================
229 //==========================================================================
232 // __BADRAM H'08'-H'09', H'13'-H'14', H'1B'-H'1D'
233 // __BADRAM H'88'-H'89',H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF'
234 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
235 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF'
237 //==========================================================================
239 // Configuration Bits
241 //==========================================================================
243 #define _CP_ALL 0x0FCF
244 #define _CP_OFF 0x3FFF
245 #define _DEBUG_ON 0x37FF
246 #define _DEBUG_OFF 0x3FFF
247 #define _WRT_ENABLE_ON 0x3FFF
248 #define _WRT_ENABLE_OFF 0x3DFF
249 #define _CPD_ON 0x3EFF
250 #define _CPD_OFF 0x3FFF
251 #define _LVP_ON 0x3FFF
252 #define _LVP_OFF 0x3F7F
253 #define _BODEN_ON 0x3FFF
254 #define _BODEN_OFF 0x3FBF
255 #define _PWRTE_OFF 0x3FFF
256 #define _PWRTE_ON 0x3FF7
257 #define _WDT_ON 0x3FFF
258 #define _WDT_OFF 0x3FFB
259 #define _LP_OSC 0x3FFC
260 #define _XT_OSC 0x3FFD
261 #define _HS_OSC 0x3FFE
262 #define _RC_OSC 0x3FFF
266 // ----- ADCON0 bits --------------------
269 unsigned char ADON:1;
272 unsigned char CHS0:1;
273 unsigned char CHS1:1;
274 unsigned char CHS2:1;
275 unsigned char ADCS0:1;
276 unsigned char ADCS1:1;
281 unsigned char NOT_DONE:1;
291 unsigned char GO_DONE:1;
299 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
301 #define ADON ADCON0_bits.ADON
302 #define GO ADCON0_bits.GO
303 #define NOT_DONE ADCON0_bits.NOT_DONE
304 #define GO_DONE ADCON0_bits.GO_DONE
305 #define CHS0 ADCON0_bits.CHS0
306 #define CHS1 ADCON0_bits.CHS1
307 #define CHS2 ADCON0_bits.CHS2
308 #define ADCS0 ADCON0_bits.ADCS0
309 #define ADCS1 ADCON0_bits.ADCS1
311 // ----- ADCON1 bits --------------------
314 unsigned char PCFG0:1;
315 unsigned char PCFG1:1;
316 unsigned char PCFG2:1;
317 unsigned char PCFG3:1;
321 unsigned char ADFM:1;
324 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
326 #define PCFG0 ADCON1_bits.PCFG0
327 #define PCFG1 ADCON1_bits.PCFG1
328 #define PCFG2 ADCON1_bits.PCFG2
329 #define PCFG3 ADCON1_bits.PCFG3
330 #define ADFM ADCON1_bits.ADFM
332 // ----- CCP1CON bits --------------------
335 unsigned char CCP1M0:1;
336 unsigned char CCP1M1:1;
337 unsigned char CCP1M2:1;
338 unsigned char CCP1M3:1;
339 unsigned char CCP1Y:1;
340 unsigned char CCP1X:1;
345 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
347 #define CCP1M0 CCP1CON_bits.CCP1M0
348 #define CCP1M1 CCP1CON_bits.CCP1M1
349 #define CCP1M2 CCP1CON_bits.CCP1M2
350 #define CCP1M3 CCP1CON_bits.CCP1M3
351 #define CCP1Y CCP1CON_bits.CCP1Y
352 #define CCP1X CCP1CON_bits.CCP1X
354 // ----- EECON1 bits --------------------
359 unsigned char WREN:1;
360 unsigned char WRERR:1;
364 unsigned char EEPGD:1;
367 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
369 #define RD EECON1_bits.RD
370 #define WR EECON1_bits.WR
371 #define WREN EECON1_bits.WREN
372 #define WRERR EECON1_bits.WRERR
373 #define EEPGD EECON1_bits.EEPGD
375 // ----- INTCON bits --------------------
378 unsigned char RBIF:1;
379 unsigned char INTF:1;
380 unsigned char T0IF:1;
381 unsigned char RBIE:1;
382 unsigned char INTE:1;
383 unsigned char T0IE:1;
384 unsigned char PEIE:1;
388 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
390 #define RBIF INTCON_bits.RBIF
391 #define INTF INTCON_bits.INTF
392 #define T0IF INTCON_bits.T0IF
393 #define RBIE INTCON_bits.RBIE
394 #define INTE INTCON_bits.INTE
395 #define T0IE INTCON_bits.T0IE
396 #define PEIE INTCON_bits.PEIE
397 #define GIE INTCON_bits.GIE
399 // ----- OPTION_REG bits --------------------
406 unsigned char T0SE:1;
407 unsigned char T0CS:1;
408 unsigned char INTEDG:1;
409 unsigned char NOT_RBPU:1;
411 } __OPTION_REG_bits_t;
412 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
414 #define PS0 OPTION_REG_bits.PS0
415 #define PS1 OPTION_REG_bits.PS1
416 #define PS2 OPTION_REG_bits.PS2
417 #define PSA OPTION_REG_bits.PSA
418 #define T0SE OPTION_REG_bits.T0SE
419 #define T0CS OPTION_REG_bits.T0CS
420 #define INTEDG OPTION_REG_bits.INTEDG
421 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
423 // ----- PCON bits --------------------
426 unsigned char NOT_BO:1;
427 unsigned char NOT_POR:1;
436 unsigned char NOT_BOR:1;
446 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
448 #define NOT_BO PCON_bits.NOT_BO
449 #define NOT_BOR PCON_bits.NOT_BOR
450 #define NOT_POR PCON_bits.NOT_POR
452 // ----- PIE1 bits --------------------
455 unsigned char TMR1IE:1;
456 unsigned char TMR2IE:1;
457 unsigned char CCP1IE:1;
459 unsigned char TXIE:1;
460 unsigned char RCIE:1;
461 unsigned char ADIE:1;
465 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
467 #define TMR1IE PIE1_bits.TMR1IE
468 #define TMR2IE PIE1_bits.TMR2IE
469 #define CCP1IE PIE1_bits.CCP1IE
470 #define TXIE PIE1_bits.TXIE
471 #define RCIE PIE1_bits.RCIE
472 #define ADIE PIE1_bits.ADIE
474 // ----- PIE2 bits --------------------
481 unsigned char EEIE:1;
487 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
489 #define EEIE PIE2_bits.EEIE
491 // ----- PIR1 bits --------------------
494 unsigned char TMR1IF:1;
495 unsigned char TMR2IF:1;
496 unsigned char CCP1IF:1;
498 unsigned char TXIF:1;
499 unsigned char RCIF:1;
500 unsigned char ADIF:1;
504 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
506 #define TMR1IF PIR1_bits.TMR1IF
507 #define TMR2IF PIR1_bits.TMR2IF
508 #define CCP1IF PIR1_bits.CCP1IF
509 #define TXIF PIR1_bits.TXIF
510 #define RCIF PIR1_bits.RCIF
511 #define ADIF PIR1_bits.ADIF
513 // ----- PIR2 bits --------------------
520 unsigned char EEIF:1;
526 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
528 #define EEIF PIR2_bits.EEIF
530 // ----- PORTA bits --------------------
543 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
545 #define RA0 PORTA_bits.RA0
546 #define RA1 PORTA_bits.RA1
547 #define RA2 PORTA_bits.RA2
548 #define RA3 PORTA_bits.RA3
549 #define RA4 PORTA_bits.RA4
550 #define RA5 PORTA_bits.RA5
552 // ----- PORTB bits --------------------
565 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
567 #define RB0 PORTB_bits.RB0
568 #define RB1 PORTB_bits.RB1
569 #define RB2 PORTB_bits.RB2
570 #define RB3 PORTB_bits.RB3
571 #define RB4 PORTB_bits.RB4
572 #define RB5 PORTB_bits.RB5
573 #define RB6 PORTB_bits.RB6
574 #define RB7 PORTB_bits.RB7
576 // ----- PORTC bits --------------------
589 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
591 #define RC0 PORTC_bits.RC0
592 #define RC1 PORTC_bits.RC1
593 #define RC2 PORTC_bits.RC2
594 #define RC3 PORTC_bits.RC3
595 #define RC4 PORTC_bits.RC4
596 #define RC5 PORTC_bits.RC5
597 #define RC6 PORTC_bits.RC6
598 #define RC7 PORTC_bits.RC7
600 // ----- RCSTA bits --------------------
603 unsigned char RX9D:1;
604 unsigned char OERR:1;
605 unsigned char FERR:1;
606 unsigned char ADDEN:1;
607 unsigned char CREN:1;
608 unsigned char SREN:1;
610 unsigned char SPEN:1;
613 unsigned char RCD8:1;
629 unsigned char NOT_RC8:1;
639 unsigned char RC8_9:1;
643 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
645 #define RX9D RCSTA_bits.RX9D
646 #define RCD8 RCSTA_bits.RCD8
647 #define OERR RCSTA_bits.OERR
648 #define FERR RCSTA_bits.FERR
649 #define ADDEN RCSTA_bits.ADDEN
650 #define CREN RCSTA_bits.CREN
651 #define SREN RCSTA_bits.SREN
652 #define RX9 RCSTA_bits.RX9
653 #define RC9 RCSTA_bits.RC9
654 #define NOT_RC8 RCSTA_bits.NOT_RC8
655 #define RC8_9 RCSTA_bits.RC8_9
656 #define SPEN RCSTA_bits.SPEN
658 // ----- STATUS bits --------------------
664 unsigned char NOT_PD:1;
665 unsigned char NOT_TO:1;
671 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
673 #define C STATUS_bits.C
674 #define DC STATUS_bits.DC
675 #define Z STATUS_bits.Z
676 #define NOT_PD STATUS_bits.NOT_PD
677 #define NOT_TO STATUS_bits.NOT_TO
678 #define RP0 STATUS_bits.RP0
679 #define RP1 STATUS_bits.RP1
680 #define IRP STATUS_bits.IRP
682 // ----- T1CON bits --------------------
685 unsigned char TMR1ON:1;
686 unsigned char TMR1CS:1;
687 unsigned char NOT_T1SYNC:1;
688 unsigned char T1OSCEN:1;
689 unsigned char T1CKPS0:1;
690 unsigned char T1CKPS1:1;
697 unsigned char T1INSYNC:1;
707 unsigned char T1SYNC:1;
715 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
717 #define TMR1ON T1CON_bits.TMR1ON
718 #define TMR1CS T1CON_bits.TMR1CS
719 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
720 #define T1INSYNC T1CON_bits.T1INSYNC
721 #define T1SYNC T1CON_bits.T1SYNC
722 #define T1OSCEN T1CON_bits.T1OSCEN
723 #define T1CKPS0 T1CON_bits.T1CKPS0
724 #define T1CKPS1 T1CON_bits.T1CKPS1
726 // ----- T2CON bits --------------------
729 unsigned char T2CKPS0:1;
730 unsigned char T2CKPS1:1;
731 unsigned char TMR2ON:1;
732 unsigned char TOUTPS0:1;
733 unsigned char TOUTPS1:1;
734 unsigned char TOUTPS2:1;
735 unsigned char TOUTPS3:1;
739 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
741 #define T2CKPS0 T2CON_bits.T2CKPS0
742 #define T2CKPS1 T2CON_bits.T2CKPS1
743 #define TMR2ON T2CON_bits.TMR2ON
744 #define TOUTPS0 T2CON_bits.TOUTPS0
745 #define TOUTPS1 T2CON_bits.TOUTPS1
746 #define TOUTPS2 T2CON_bits.TOUTPS2
747 #define TOUTPS3 T2CON_bits.TOUTPS3
749 // ----- TRISA bits --------------------
752 unsigned char TRISA0:1;
753 unsigned char TRISA1:1;
754 unsigned char TRISA2:1;
755 unsigned char TRISA3:1;
756 unsigned char TRISA4:1;
757 unsigned char TRISA5:1;
762 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
764 #define TRISA0 TRISA_bits.TRISA0
765 #define TRISA1 TRISA_bits.TRISA1
766 #define TRISA2 TRISA_bits.TRISA2
767 #define TRISA3 TRISA_bits.TRISA3
768 #define TRISA4 TRISA_bits.TRISA4
769 #define TRISA5 TRISA_bits.TRISA5
771 // ----- TRISB bits --------------------
774 unsigned char TRISB0:1;
775 unsigned char TRISB1:1;
776 unsigned char TRISB2:1;
777 unsigned char TRISB3:1;
778 unsigned char TRISB4:1;
779 unsigned char TRISB5:1;
780 unsigned char TRISB6:1;
781 unsigned char TRISB7:1;
784 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
786 #define TRISB0 TRISB_bits.TRISB0
787 #define TRISB1 TRISB_bits.TRISB1
788 #define TRISB2 TRISB_bits.TRISB2
789 #define TRISB3 TRISB_bits.TRISB3
790 #define TRISB4 TRISB_bits.TRISB4
791 #define TRISB5 TRISB_bits.TRISB5
792 #define TRISB6 TRISB_bits.TRISB6
793 #define TRISB7 TRISB_bits.TRISB7
795 // ----- TRISC bits --------------------
798 unsigned char TRISC0:1;
799 unsigned char TRISC1:1;
800 unsigned char TRISC2:1;
801 unsigned char TRISC3:1;
802 unsigned char TRISC4:1;
803 unsigned char TRISC5:1;
804 unsigned char TRISC6:1;
805 unsigned char TRISC7:1;
808 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
810 #define TRISC0 TRISC_bits.TRISC0
811 #define TRISC1 TRISC_bits.TRISC1
812 #define TRISC2 TRISC_bits.TRISC2
813 #define TRISC3 TRISC_bits.TRISC3
814 #define TRISC4 TRISC_bits.TRISC4
815 #define TRISC5 TRISC_bits.TRISC5
816 #define TRISC6 TRISC_bits.TRISC6
817 #define TRISC7 TRISC_bits.TRISC7
819 // ----- TXSTA bits --------------------
822 unsigned char TX9D:1;
823 unsigned char TRMT:1;
824 unsigned char BRGH:1;
826 unsigned char SYNC:1;
827 unsigned char TXEN:1;
829 unsigned char CSRC:1;
832 unsigned char TXD8:1;
838 unsigned char NOT_TX8:1;
848 unsigned char TX8_9:1;
852 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
854 #define TX9D TXSTA_bits.TX9D
855 #define TXD8 TXSTA_bits.TXD8
856 #define TRMT TXSTA_bits.TRMT
857 #define BRGH TXSTA_bits.BRGH
858 #define SYNC TXSTA_bits.SYNC
859 #define TXEN TXSTA_bits.TXEN
860 #define TX9 TXSTA_bits.TX9
861 #define NOT_TX8 TXSTA_bits.NOT_TX8
862 #define TX8_9 TXSTA_bits.TX8_9
863 #define CSRC TXSTA_bits.CSRC