2 // Register Declarations for Microchip 16F87 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define RCSTA_ADDR 0x0018
50 #define TXREG_ADDR 0x0019
51 #define RCREG_ADDR 0x001A
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define PIE1_ADDR 0x008C
56 #define PIE2_ADDR 0x008D
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define PR2_ADDR 0x0092
61 #define SSPADD_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define TXSTA_ADDR 0x0098
64 #define SPBRG_ADDR 0x0099
65 #define CMCON_ADDR 0x009C
66 #define CVRCON_ADDR 0x009D
67 #define WDTCON_ADDR 0x0105
68 #define EEDATA_ADDR 0x010C
69 #define EEADR_ADDR 0x010D
70 #define EEDATH_ADDR 0x010E
71 #define EEADRH_ADDR 0x010F
72 #define EECON1_ADDR 0x018C
73 #define EECON2_ADDR 0x018D
76 // Memory organization.
79 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
80 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
81 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
82 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
83 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
84 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
85 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
86 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
87 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
88 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
89 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
90 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
91 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
92 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
93 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
94 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
95 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
96 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
97 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
98 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
99 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
100 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
101 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
102 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
103 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
104 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
105 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
106 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
107 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
108 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
109 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
110 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
111 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
112 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
113 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
114 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
115 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
116 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
117 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
118 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
119 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
120 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
121 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
122 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
123 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
124 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
128 // P16F87.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
131 // This header file defines configurations, registers, and other useful bits of
132 // information for the PIC16F87 microcontroller. These names are taken to match
133 // the data sheets as closely as possible.
135 // Note that the processor must be selected before this file is
136 // included. The processor may be selected the following ways:
138 // 1. Command line switch:
139 // C:\ MPASM MYFILE.ASM /PIC16F87
140 // 2. LIST directive in the source file
142 // 3. Processor Type entry in the MPASM full-screen interface
144 //==========================================================================
148 //==========================================================================
152 //1.00 07/29/02 Initial Release
153 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
154 //1.02 01/10/03 Added bit names for TXSTA & RCSTA registers.
155 //1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0
156 //1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1.
157 //1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0.
159 //==========================================================================
163 //==========================================================================
166 // MESSG "Processor-header file mismatch. Verify selected processor."
169 //==========================================================================
171 // Register Definitions
173 //==========================================================================
178 //----- Register Files------------------------------------------------------
180 extern __data __at (INDF_ADDR) volatile char INDF;
181 extern __sfr __at (TMR0_ADDR) TMR0;
182 extern __data __at (PCL_ADDR) volatile char PCL;
183 extern __sfr __at (STATUS_ADDR) STATUS;
184 extern __sfr __at (FSR_ADDR) FSR;
185 extern __sfr __at (PORTA_ADDR) PORTA;
186 extern __sfr __at (PORTB_ADDR) PORTB;
187 extern __sfr __at (PCLATH_ADDR) PCLATH;
188 extern __sfr __at (INTCON_ADDR) INTCON;
189 extern __sfr __at (PIR1_ADDR) PIR1;
190 extern __sfr __at (PIR2_ADDR) PIR2;
191 extern __sfr __at (TMR1L_ADDR) TMR1L;
192 extern __sfr __at (TMR1H_ADDR) TMR1H;
193 extern __sfr __at (T1CON_ADDR) T1CON;
194 extern __sfr __at (TMR2_ADDR) TMR2;
195 extern __sfr __at (T2CON_ADDR) T2CON;
196 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
197 extern __sfr __at (SSPCON_ADDR) SSPCON;
198 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
199 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
200 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
201 extern __sfr __at (RCSTA_ADDR) RCSTA;
202 extern __sfr __at (TXREG_ADDR) TXREG;
203 extern __sfr __at (RCREG_ADDR) RCREG;
205 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
206 extern __sfr __at (TRISA_ADDR) TRISA;
207 extern __sfr __at (TRISB_ADDR) TRISB;
208 extern __sfr __at (PIE1_ADDR) PIE1;
209 extern __sfr __at (PIE2_ADDR) PIE2;
210 extern __sfr __at (PCON_ADDR) PCON;
211 extern __sfr __at (OSCCON_ADDR) OSCCON;
212 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
213 extern __sfr __at (PR2_ADDR) PR2;
214 extern __sfr __at (SSPADD_ADDR) SSPADD;
215 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
216 extern __sfr __at (TXSTA_ADDR) TXSTA;
217 extern __sfr __at (SPBRG_ADDR) SPBRG;
218 extern __sfr __at (CMCON_ADDR) CMCON;
219 extern __sfr __at (CVRCON_ADDR) CVRCON;
221 extern __sfr __at (WDTCON_ADDR) WDTCON;
222 extern __sfr __at (EEDATA_ADDR) EEDATA;
223 extern __sfr __at (EEADR_ADDR) EEADR;
224 extern __sfr __at (EEDATH_ADDR) EEDATH;
225 extern __sfr __at (EEADRH_ADDR) EEADRH;
227 extern __sfr __at (EECON1_ADDR) EECON1;
228 extern __sfr __at (EECON2_ADDR) EECON2;
230 //----- STATUS Bits --------------------------------------------------------
232 //----- INTCON Bits --------------------------------------------------------
234 //----- PIR1 Bits ----------------------------------------------------------
236 //----- PIR2 Bits ----------------------------------------------------------
238 //----- T1CON Bits ---------------------------------------------------------
240 //----- T2CON Bits ---------------------------------------------------------
242 //----- SSPCON Bits --------------------------------------------------------
244 //----- CCP1CON Bits -------------------------------------------------------
246 //----- RCSTA Bits ---------------------------------------------------------
248 //----- OPTION Bits -----------------------------------------------------
250 //----- PIE1 Bits ----------------------------------------------------------
252 //----- PIE2 Bits ----------------------------------------------------------
254 //----- PCON Bits ----------------------------------------------------------
256 //----- OSCCON Bits -------------------------------------------------------
258 //----- OSCTUNE Bits -------------------------------------------------------
260 //----- SSPSTAT Bits -------------------------------------------------------
262 //----- TXSTA Bits ---------------------------------------------------------
264 //----- WDTCON Bits --------------------------------------------------------
266 //----- CMCON Bits ---------------------------------------------------------
268 //----- CVRCON Bits --------------------------------------------------------
270 //----- EECON1 Bits --------------------------------------------------------
272 //==========================================================================
276 //==========================================================================
279 // __BADRAM H'07'-H'09', H'1B'-H'1F'
280 // __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A', H'9E'-H'9F'
281 // __BADRAM H'107'-H'109'
282 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
284 //==========================================================================
286 // Configuration Bits
288 //==========================================================================
290 #define _CONFIG1 0x2007
291 #define _CONFIG2 0x2008
293 //Configuration Byte 1 Options
294 #define _CP_ALL 0x1FFF
295 #define _CP_OFF 0x3FFF
296 #define _CCP1_RB0 0x3FFF
297 #define _CCP1_RB3 0x2FFF
298 #define _DEBUG_OFF 0x3FFF
299 #define _DEBUG_ON 0x37FF
300 #define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection
301 #define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected
302 #define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected
303 #define _WRT_PROTECT_ALL 0x39FF //All of program memory protected
304 #define _CPD_ON 0x3EFF
305 #define _CPD_OFF 0x3FFF
306 #define _LVP_ON 0x3FFF
307 #define _LVP_OFF 0x3F7F
308 #define _BODEN_ON 0x3FFF
309 #define _BODEN_OFF 0x3FBF
310 #define _MCLR_ON 0x3FFF
311 #define _MCLR_OFF 0x3FDF
312 #define _PWRTE_OFF 0x3FFF
313 #define _PWRTE_ON 0x3FF7
314 #define _WDT_ON 0x3FFF
315 #define _WDT_OFF 0x3FFB
316 #define _EXTRC_CLKOUT 0x3FFF
317 #define _EXTRC_IO 0x3FFE
318 #define _INTRC_CLKOUT 0x3FFD
319 #define _INTRC_IO 0x3FFC
320 #define _EXTCLK 0x3FEF
321 #define _HS_OSC 0x3FEE
322 #define _XT_OSC 0x3FED
323 #define _LP_OSC 0x3FEC
325 //Configuration Byte 2 Options
326 #define _IESO_ON 0x3FFF
327 #define _IESO_OFF 0x3FFD
328 #define _FCMEN_ON 0x3FFF
329 #define _FCMEN_OFF 0x3FFE
333 // To use the Configuration Bits, place the following lines in your source code
334 // in the following format, and change the configuration value to the desired
335 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
336 // and each __CONFIG line should have the preceding semicolon removed when
337 // pasted into your source code.
339 //Program Configuration Register 1
340 // __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
342 //Program Configuration Register 2
343 // __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF
352 // ----- CCP1CON bits --------------------
355 unsigned char CCP1M0:1;
356 unsigned char CCP1M1:1;
357 unsigned char CCP1M2:1;
358 unsigned char CCP1M3:1;
359 unsigned char CCP1Y:1;
360 unsigned char CCP1X:1;
365 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
367 #define CCP1M0 CCP1CON_bits.CCP1M0
368 #define CCP1M1 CCP1CON_bits.CCP1M1
369 #define CCP1M2 CCP1CON_bits.CCP1M2
370 #define CCP1M3 CCP1CON_bits.CCP1M3
371 #define CCP1Y CCP1CON_bits.CCP1Y
372 #define CCP1X CCP1CON_bits.CCP1X
374 // ----- CMCON bits --------------------
381 unsigned char C1INV:1;
382 unsigned char C2INV:1;
383 unsigned char C1OUT:1;
384 unsigned char C2OUT:1;
387 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
389 #define CM0 CMCON_bits.CM0
390 #define CM1 CMCON_bits.CM1
391 #define CM2 CMCON_bits.CM2
392 #define CIS CMCON_bits.CIS
393 #define C1INV CMCON_bits.C1INV
394 #define C2INV CMCON_bits.C2INV
395 #define C1OUT CMCON_bits.C1OUT
396 #define C2OUT CMCON_bits.C2OUT
398 // ----- CVRCON bits --------------------
401 unsigned char CVR0:1;
402 unsigned char CVR1:1;
403 unsigned char CVR2:1;
404 unsigned char CVR3:1;
406 unsigned char CVRR:1;
407 unsigned char CVROE:1;
408 unsigned char CVREN:1;
411 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
413 #define CVR0 CVRCON_bits.CVR0
414 #define CVR1 CVRCON_bits.CVR1
415 #define CVR2 CVRCON_bits.CVR2
416 #define CVR3 CVRCON_bits.CVR3
417 #define CVRR CVRCON_bits.CVRR
418 #define CVROE CVRCON_bits.CVROE
419 #define CVREN CVRCON_bits.CVREN
421 // ----- EECON1 bits --------------------
426 unsigned char WREN:1;
427 unsigned char WRERR:1;
428 unsigned char FREE:1;
431 unsigned char EEPGD:1;
434 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
436 #define RD EECON1_bits.RD
437 #define WR EECON1_bits.WR
438 #define WREN EECON1_bits.WREN
439 #define WRERR EECON1_bits.WRERR
440 #define FREE EECON1_bits.FREE
441 #define EEPGD EECON1_bits.EEPGD
443 // ----- INTCON bits --------------------
446 unsigned char RBIF:1;
447 unsigned char INTF:1;
448 unsigned char TMR0IF:1;
449 unsigned char RBIE:1;
450 unsigned char INTE:1;
451 unsigned char TMR0IE:1;
452 unsigned char PEIE:1;
456 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
458 #define RBIF INTCON_bits.RBIF
459 #define INTF INTCON_bits.INTF
460 #define TMR0IF INTCON_bits.TMR0IF
461 #define RBIE INTCON_bits.RBIE
462 #define INTE INTCON_bits.INTE
463 #define TMR0IE INTCON_bits.TMR0IE
464 #define PEIE INTCON_bits.PEIE
465 #define GIE INTCON_bits.GIE
467 // ----- OPTION_REG bits --------------------
474 unsigned char T0SE:1;
475 unsigned char T0CS:1;
476 unsigned char INTEDG:1;
477 unsigned char NOT_RBPU:1;
479 } __OPTION_REG_bits_t;
480 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
482 #define PS0 OPTION_REG_bits.PS0
483 #define PS1 OPTION_REG_bits.PS1
484 #define PS2 OPTION_REG_bits.PS2
485 #define PSA OPTION_REG_bits.PSA
486 #define T0SE OPTION_REG_bits.T0SE
487 #define T0CS OPTION_REG_bits.T0CS
488 #define INTEDG OPTION_REG_bits.INTEDG
489 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
491 // ----- OSCCON bits --------------------
494 unsigned char SCS0:1;
495 unsigned char SCS1:1;
496 unsigned char IOFS:1;
497 unsigned char OSTS:1;
498 unsigned char IRCF0:1;
499 unsigned char IRCF1:1;
500 unsigned char IRCF2:1;
504 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
506 #define SCS0 OSCCON_bits.SCS0
507 #define SCS1 OSCCON_bits.SCS1
508 #define IOFS OSCCON_bits.IOFS
509 #define OSTS OSCCON_bits.OSTS
510 #define IRCF0 OSCCON_bits.IRCF0
511 #define IRCF1 OSCCON_bits.IRCF1
512 #define IRCF2 OSCCON_bits.IRCF2
514 // ----- OSCTUNE bits --------------------
517 unsigned char TUN0:1;
518 unsigned char TUN1:1;
519 unsigned char TUN2:1;
520 unsigned char TUN3:1;
521 unsigned char TUN4:1;
522 unsigned char TUN5:1;
527 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
529 #define TUN0 OSCTUNE_bits.TUN0
530 #define TUN1 OSCTUNE_bits.TUN1
531 #define TUN2 OSCTUNE_bits.TUN2
532 #define TUN3 OSCTUNE_bits.TUN3
533 #define TUN4 OSCTUNE_bits.TUN4
534 #define TUN5 OSCTUNE_bits.TUN5
536 // ----- PCON bits --------------------
539 unsigned char NOT_BO:1;
540 unsigned char NOT_POR:1;
549 unsigned char NOT_BOR:1;
559 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
561 #define NOT_BO PCON_bits.NOT_BO
562 #define NOT_BOR PCON_bits.NOT_BOR
563 #define NOT_POR PCON_bits.NOT_POR
565 // ----- PIE1 bits --------------------
568 unsigned char TMR1IE:1;
569 unsigned char TMR2IE:1;
570 unsigned char CCP1IE:1;
571 unsigned char SSPIE:1;
572 unsigned char TXIE:1;
573 unsigned char RCIE:1;
578 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
580 #define TMR1IE PIE1_bits.TMR1IE
581 #define TMR2IE PIE1_bits.TMR2IE
582 #define CCP1IE PIE1_bits.CCP1IE
583 #define SSPIE PIE1_bits.SSPIE
584 #define TXIE PIE1_bits.TXIE
585 #define RCIE PIE1_bits.RCIE
587 // ----- PIE2 bits --------------------
594 unsigned char EEIE:1;
596 unsigned char CMIE:1;
597 unsigned char OSFIE:1;
600 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
602 #define EEIE PIE2_bits.EEIE
603 #define CMIE PIE2_bits.CMIE
604 #define OSFIE PIE2_bits.OSFIE
606 // ----- PIR1 bits --------------------
609 unsigned char TMR1IF:1;
610 unsigned char TMR2IF:1;
611 unsigned char CCP1IF:1;
612 unsigned char SSPIF:1;
613 unsigned char TXIF:1;
614 unsigned char RCIF:1;
619 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
621 #define TMR1IF PIR1_bits.TMR1IF
622 #define TMR2IF PIR1_bits.TMR2IF
623 #define CCP1IF PIR1_bits.CCP1IF
624 #define SSPIF PIR1_bits.SSPIF
625 #define TXIF PIR1_bits.TXIF
626 #define RCIF PIR1_bits.RCIF
628 // ----- PIR2 bits --------------------
635 unsigned char EEIF:1;
637 unsigned char CMIF:1;
638 unsigned char OSFIF:1;
641 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
643 #define EEIF PIR2_bits.EEIF
644 #define CMIF PIR2_bits.CMIF
645 #define OSFIF PIR2_bits.OSFIF
647 // ----- RCSTA bits --------------------
650 unsigned char RX9D:1;
651 unsigned char OERR:1;
652 unsigned char FERR:1;
653 unsigned char ADDEN:1;
654 unsigned char CREN:1;
655 unsigned char SREN:1;
657 unsigned char SPEN:1;
660 unsigned char RCD8:1;
676 unsigned char NOT_RC8:1;
686 unsigned char RC8_9:1;
690 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
692 #define RX9D RCSTA_bits.RX9D
693 #define RCD8 RCSTA_bits.RCD8
694 #define OERR RCSTA_bits.OERR
695 #define FERR RCSTA_bits.FERR
696 #define ADDEN RCSTA_bits.ADDEN
697 #define CREN RCSTA_bits.CREN
698 #define SREN RCSTA_bits.SREN
699 #define RX9 RCSTA_bits.RX9
700 #define RC9 RCSTA_bits.RC9
701 #define NOT_RC8 RCSTA_bits.NOT_RC8
702 #define RC8_9 RCSTA_bits.RC8_9
703 #define SPEN RCSTA_bits.SPEN
705 // ----- SSPCON bits --------------------
708 unsigned char SSPM0:1;
709 unsigned char SSPM1:1;
710 unsigned char SSPM2:1;
711 unsigned char SSPM3:1;
713 unsigned char SSPEN:1;
714 unsigned char SSPOV:1;
715 unsigned char WCOL:1;
718 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
720 #define SSPM0 SSPCON_bits.SSPM0
721 #define SSPM1 SSPCON_bits.SSPM1
722 #define SSPM2 SSPCON_bits.SSPM2
723 #define SSPM3 SSPCON_bits.SSPM3
724 #define CKP SSPCON_bits.CKP
725 #define SSPEN SSPCON_bits.SSPEN
726 #define SSPOV SSPCON_bits.SSPOV
727 #define WCOL SSPCON_bits.WCOL
729 // ----- SSPSTAT bits --------------------
744 unsigned char I2C_READ:1;
745 unsigned char I2C_START:1;
746 unsigned char I2C_STOP:1;
747 unsigned char I2C_DATA:1;
754 unsigned char NOT_W:1;
757 unsigned char NOT_A:1;
764 unsigned char NOT_WRITE:1;
767 unsigned char NOT_ADDRESS:1;
784 unsigned char READ_WRITE:1;
787 unsigned char DATA_ADDRESS:1;
792 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
794 #define BF SSPSTAT_bits.BF
795 #define UA SSPSTAT_bits.UA
796 #define R SSPSTAT_bits.R
797 #define I2C_READ SSPSTAT_bits.I2C_READ
798 #define NOT_W SSPSTAT_bits.NOT_W
799 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
800 #define R_W SSPSTAT_bits.R_W
801 #define READ_WRITE SSPSTAT_bits.READ_WRITE
802 #define S SSPSTAT_bits.S
803 #define I2C_START SSPSTAT_bits.I2C_START
804 #define P SSPSTAT_bits.P
805 #define I2C_STOP SSPSTAT_bits.I2C_STOP
806 #define D SSPSTAT_bits.D
807 #define I2C_DATA SSPSTAT_bits.I2C_DATA
808 #define NOT_A SSPSTAT_bits.NOT_A
809 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
810 #define D_A SSPSTAT_bits.D_A
811 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
812 #define CKE SSPSTAT_bits.CKE
813 #define SMP SSPSTAT_bits.SMP
815 // ----- STATUS bits --------------------
821 unsigned char NOT_PD:1;
822 unsigned char NOT_TO:1;
828 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
830 #define C STATUS_bits.C
831 #define DC STATUS_bits.DC
832 #define Z STATUS_bits.Z
833 #define NOT_PD STATUS_bits.NOT_PD
834 #define NOT_TO STATUS_bits.NOT_TO
835 #define RP0 STATUS_bits.RP0
836 #define RP1 STATUS_bits.RP1
837 #define IRP STATUS_bits.IRP
839 // ----- T1CON bits --------------------
842 unsigned char TMR1ON:1;
843 unsigned char TMR1CS:1;
844 unsigned char NOT_T1SYNC:1;
845 unsigned char T1OSCEN:1;
846 unsigned char T1CKPS0:1;
847 unsigned char T1CKPS1:1;
848 unsigned char T1RUN:1;
854 unsigned char T1INSYNC:1;
862 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
864 #define TMR1ON T1CON_bits.TMR1ON
865 #define TMR1CS T1CON_bits.TMR1CS
866 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
867 #define T1INSYNC T1CON_bits.T1INSYNC
868 #define T1OSCEN T1CON_bits.T1OSCEN
869 #define T1CKPS0 T1CON_bits.T1CKPS0
870 #define T1CKPS1 T1CON_bits.T1CKPS1
871 #define T1RUN T1CON_bits.T1RUN
873 // ----- T2CON bits --------------------
876 unsigned char T2CKPS0:1;
877 unsigned char T2CKPS1:1;
878 unsigned char TMR2ON:1;
879 unsigned char TOUTPS0:1;
880 unsigned char TOUTPS1:1;
881 unsigned char TOUTPS2:1;
882 unsigned char TOUTPS3:1;
886 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
888 #define T2CKPS0 T2CON_bits.T2CKPS0
889 #define T2CKPS1 T2CON_bits.T2CKPS1
890 #define TMR2ON T2CON_bits.TMR2ON
891 #define TOUTPS0 T2CON_bits.TOUTPS0
892 #define TOUTPS1 T2CON_bits.TOUTPS1
893 #define TOUTPS2 T2CON_bits.TOUTPS2
894 #define TOUTPS3 T2CON_bits.TOUTPS3
896 // ----- TXSTA bits --------------------
899 unsigned char TX9D:1;
900 unsigned char TRMT:1;
901 unsigned char BRGH:1;
903 unsigned char SYNC:1;
904 unsigned char TXEN:1;
906 unsigned char CSRC:1;
909 unsigned char TXD8:1;
915 unsigned char NOT_TX8:1;
925 unsigned char TX8_9:1;
929 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
931 #define TX9D TXSTA_bits.TX9D
932 #define TXD8 TXSTA_bits.TXD8
933 #define TRMT TXSTA_bits.TRMT
934 #define BRGH TXSTA_bits.BRGH
935 #define SYNC TXSTA_bits.SYNC
936 #define TXEN TXSTA_bits.TXEN
937 #define TX9 TXSTA_bits.TX9
938 #define NOT_TX8 TXSTA_bits.NOT_TX8
939 #define TX8_9 TXSTA_bits.TX8_9
940 #define CSRC TXSTA_bits.CSRC
942 // ----- WDTCON bits --------------------
945 unsigned char SWDTEN:1;
946 unsigned char WDTPS0:1;
947 unsigned char WDTPS1:1;
948 unsigned char WDTPS2:1;
949 unsigned char WDTPS3:1;
955 unsigned char SWDTE:1;
965 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
967 #define SWDTEN WDTCON_bits.SWDTEN
968 #define SWDTE WDTCON_bits.SWDTE
969 #define WDTPS0 WDTCON_bits.WDTPS0
970 #define WDTPS1 WDTCON_bits.WDTPS1
971 #define WDTPS2 WDTCON_bits.WDTPS2
972 #define WDTPS3 WDTCON_bits.WDTPS3