2 // Register Declarations for Microchip 16F87 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define RCSTA_ADDR 0x0018
50 #define TXREG_ADDR 0x0019
51 #define RCREG_ADDR 0x001A
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define PIE1_ADDR 0x008C
56 #define PIE2_ADDR 0x008D
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define PR2_ADDR 0x0092
61 #define SSPADD_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define TXSTA_ADDR 0x0098
64 #define SPBRG_ADDR 0x0099
65 #define CMCON_ADDR 0x009C
66 #define CVRCON_ADDR 0x009D
67 #define WDTCON_ADDR 0x0105
68 #define EEDATA_ADDR 0x010C
69 #define EEADR_ADDR 0x010D
70 #define EEDATH_ADDR 0x010E
71 #define EEADRH_ADDR 0x010F
72 #define EECON1_ADDR 0x018C
73 #define EECON2_ADDR 0x018D
76 // Memory organization.
82 // P16F87.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
85 // This header file defines configurations, registers, and other useful bits of
86 // information for the PIC16F87 microcontroller. These names are taken to match
87 // the data sheets as closely as possible.
89 // Note that the processor must be selected before this file is
90 // included. The processor may be selected the following ways:
92 // 1. Command line switch:
93 // C:\ MPASM MYFILE.ASM /PIC16F87
94 // 2. LIST directive in the source file
96 // 3. Processor Type entry in the MPASM full-screen interface
98 //==========================================================================
102 //==========================================================================
106 //1.00 07/29/02 Initial Release
107 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
108 //1.02 01/10/03 Added bit names for TXSTA & RCSTA registers.
109 //1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0
110 //1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1.
111 //1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0.
113 //==========================================================================
117 //==========================================================================
120 // MESSG "Processor-header file mismatch. Verify selected processor."
123 //==========================================================================
125 // Register Definitions
127 //==========================================================================
132 //----- Register Files------------------------------------------------------
134 extern __sfr __at (INDF_ADDR) INDF;
135 extern __sfr __at (TMR0_ADDR) TMR0;
136 extern __sfr __at (PCL_ADDR) PCL;
137 extern __sfr __at (STATUS_ADDR) STATUS;
138 extern __sfr __at (FSR_ADDR) FSR;
139 extern __sfr __at (PORTA_ADDR) PORTA;
140 extern __sfr __at (PORTB_ADDR) PORTB;
141 extern __sfr __at (PCLATH_ADDR) PCLATH;
142 extern __sfr __at (INTCON_ADDR) INTCON;
143 extern __sfr __at (PIR1_ADDR) PIR1;
144 extern __sfr __at (PIR2_ADDR) PIR2;
145 extern __sfr __at (TMR1L_ADDR) TMR1L;
146 extern __sfr __at (TMR1H_ADDR) TMR1H;
147 extern __sfr __at (T1CON_ADDR) T1CON;
148 extern __sfr __at (TMR2_ADDR) TMR2;
149 extern __sfr __at (T2CON_ADDR) T2CON;
150 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
151 extern __sfr __at (SSPCON_ADDR) SSPCON;
152 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
153 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
154 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
155 extern __sfr __at (RCSTA_ADDR) RCSTA;
156 extern __sfr __at (TXREG_ADDR) TXREG;
157 extern __sfr __at (RCREG_ADDR) RCREG;
159 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
160 extern __sfr __at (TRISA_ADDR) TRISA;
161 extern __sfr __at (TRISB_ADDR) TRISB;
162 extern __sfr __at (PIE1_ADDR) PIE1;
163 extern __sfr __at (PIE2_ADDR) PIE2;
164 extern __sfr __at (PCON_ADDR) PCON;
165 extern __sfr __at (OSCCON_ADDR) OSCCON;
166 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
167 extern __sfr __at (PR2_ADDR) PR2;
168 extern __sfr __at (SSPADD_ADDR) SSPADD;
169 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
170 extern __sfr __at (TXSTA_ADDR) TXSTA;
171 extern __sfr __at (SPBRG_ADDR) SPBRG;
172 extern __sfr __at (CMCON_ADDR) CMCON;
173 extern __sfr __at (CVRCON_ADDR) CVRCON;
175 extern __sfr __at (WDTCON_ADDR) WDTCON;
176 extern __sfr __at (EEDATA_ADDR) EEDATA;
177 extern __sfr __at (EEADR_ADDR) EEADR;
178 extern __sfr __at (EEDATH_ADDR) EEDATH;
179 extern __sfr __at (EEADRH_ADDR) EEADRH;
181 extern __sfr __at (EECON1_ADDR) EECON1;
182 extern __sfr __at (EECON2_ADDR) EECON2;
184 //----- STATUS Bits --------------------------------------------------------
186 //----- INTCON Bits --------------------------------------------------------
188 //----- PIR1 Bits ----------------------------------------------------------
190 //----- PIR2 Bits ----------------------------------------------------------
192 //----- T1CON Bits ---------------------------------------------------------
194 //----- T2CON Bits ---------------------------------------------------------
196 //----- SSPCON Bits --------------------------------------------------------
198 //----- CCP1CON Bits -------------------------------------------------------
200 //----- RCSTA Bits ---------------------------------------------------------
202 //----- OPTION_REG Bits -----------------------------------------------------
204 //----- PIE1 Bits ----------------------------------------------------------
206 //----- PIE2 Bits ----------------------------------------------------------
208 //----- PCON Bits ----------------------------------------------------------
210 //----- OSCCON Bits -------------------------------------------------------
212 //----- OSCTUNE Bits -------------------------------------------------------
214 //----- SSPSTAT Bits -------------------------------------------------------
216 //----- TXSTA Bits ---------------------------------------------------------
218 //----- WDTCON Bits --------------------------------------------------------
220 //----- CMCON Bits ---------------------------------------------------------
222 //----- CVRCON Bits --------------------------------------------------------
224 //----- EECON1 Bits --------------------------------------------------------
226 //==========================================================================
230 //==========================================================================
233 // __BADRAM H'07'-H'09', H'1B'-H'1F'
234 // __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A', H'9E'-H'9F'
235 // __BADRAM H'107'-H'109'
236 // __BADRAM H'185', H'187'-H'189', H'18E'-H'18F'
238 //==========================================================================
240 // Configuration Bits
242 //==========================================================================
244 #define _CONFIG1 0x2007
245 #define _CONFIG2 0x2008
247 //Configuration Byte 1 Options
248 #define _CP_ALL 0x1FFF
249 #define _CP_OFF 0x3FFF
250 #define _CCP1_RB0 0x3FFF
251 #define _CCP1_RB3 0x2FFF
252 #define _DEBUG_OFF 0x3FFF
253 #define _DEBUG_ON 0x37FF
254 #define _WRT_PROTECT_OFF 0x3FFF //No program memory write protection
255 #define _WRT_PROTECT_256 0x3DFF //First 256 program memory protected
256 #define _WRT_PROTECT_2048 0x3BFF //First 2048 program memory protected
257 #define _WRT_PROTECT_ALL 0x39FF //All of program memory protected
258 #define _CPD_ON 0x3EFF
259 #define _CPD_OFF 0x3FFF
260 #define _LVP_ON 0x3FFF
261 #define _LVP_OFF 0x3F7F
262 #define _BODEN_ON 0x3FFF
263 #define _BODEN_OFF 0x3FBF
264 #define _MCLR_ON 0x3FFF
265 #define _MCLR_OFF 0x3FDF
266 #define _PWRTE_OFF 0x3FFF
267 #define _PWRTE_ON 0x3FF7
268 #define _WDT_ON 0x3FFF
269 #define _WDT_OFF 0x3FFB
270 #define _EXTRC_CLKOUT 0x3FFF
271 #define _EXTRC_IO 0x3FFE
272 #define _INTRC_CLKOUT 0x3FFD
273 #define _INTRC_IO 0x3FFC
274 #define _EXTCLK 0x3FEF
275 #define _HS_OSC 0x3FEE
276 #define _XT_OSC 0x3FED
277 #define _LP_OSC 0x3FEC
279 //Configuration Byte 2 Options
280 #define _IESO_ON 0x3FFF
281 #define _IESO_OFF 0x3FFD
282 #define _FCMEN_ON 0x3FFF
283 #define _FCMEN_OFF 0x3FFE
287 // To use the Configuration Bits, place the following lines in your source code
288 // in the following format, and change the configuration value to the desired
289 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
290 // and each __CONFIG line should have the preceding semicolon removed when
291 // pasted into your source code.
293 //Program Configuration Register 1
294 // __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
296 //Program Configuration Register 2
297 // __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF
306 // ----- CCP1CON bits --------------------
309 unsigned char CCP1M0:1;
310 unsigned char CCP1M1:1;
311 unsigned char CCP1M2:1;
312 unsigned char CCP1M3:1;
313 unsigned char CCP1Y:1;
314 unsigned char CCP1X:1;
319 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
321 #ifndef NO_BIT_DEFINES
322 #define CCP1M0 CCP1CON_bits.CCP1M0
323 #define CCP1M1 CCP1CON_bits.CCP1M1
324 #define CCP1M2 CCP1CON_bits.CCP1M2
325 #define CCP1M3 CCP1CON_bits.CCP1M3
326 #define CCP1Y CCP1CON_bits.CCP1Y
327 #define CCP1X CCP1CON_bits.CCP1X
328 #endif /* NO_BIT_DEFINES */
330 // ----- CMCON bits --------------------
337 unsigned char C1INV:1;
338 unsigned char C2INV:1;
339 unsigned char C1OUT:1;
340 unsigned char C2OUT:1;
343 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
345 #ifndef NO_BIT_DEFINES
346 #define CM0 CMCON_bits.CM0
347 #define CM1 CMCON_bits.CM1
348 #define CM2 CMCON_bits.CM2
349 #define CIS CMCON_bits.CIS
350 #define C1INV CMCON_bits.C1INV
351 #define C2INV CMCON_bits.C2INV
352 #define C1OUT CMCON_bits.C1OUT
353 #define C2OUT CMCON_bits.C2OUT
354 #endif /* NO_BIT_DEFINES */
356 // ----- CVRCON bits --------------------
359 unsigned char CVR0:1;
360 unsigned char CVR1:1;
361 unsigned char CVR2:1;
362 unsigned char CVR3:1;
364 unsigned char CVRR:1;
365 unsigned char CVROE:1;
366 unsigned char CVREN:1;
369 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
371 #ifndef NO_BIT_DEFINES
372 #define CVR0 CVRCON_bits.CVR0
373 #define CVR1 CVRCON_bits.CVR1
374 #define CVR2 CVRCON_bits.CVR2
375 #define CVR3 CVRCON_bits.CVR3
376 #define CVRR CVRCON_bits.CVRR
377 #define CVROE CVRCON_bits.CVROE
378 #define CVREN CVRCON_bits.CVREN
379 #endif /* NO_BIT_DEFINES */
381 // ----- EECON1 bits --------------------
386 unsigned char WREN:1;
387 unsigned char WRERR:1;
388 unsigned char FREE:1;
391 unsigned char EEPGD:1;
394 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
396 #ifndef NO_BIT_DEFINES
397 #define RD EECON1_bits.RD
398 #define WR EECON1_bits.WR
399 #define WREN EECON1_bits.WREN
400 #define WRERR EECON1_bits.WRERR
401 #define FREE EECON1_bits.FREE
402 #define EEPGD EECON1_bits.EEPGD
403 #endif /* NO_BIT_DEFINES */
405 // ----- INTCON bits --------------------
408 unsigned char RBIF:1;
409 unsigned char INTF:1;
410 unsigned char TMR0IF:1;
411 unsigned char RBIE:1;
412 unsigned char INTE:1;
413 unsigned char TMR0IE:1;
414 unsigned char PEIE:1;
418 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
420 #ifndef NO_BIT_DEFINES
421 #define RBIF INTCON_bits.RBIF
422 #define INTF INTCON_bits.INTF
423 #define TMR0IF INTCON_bits.TMR0IF
424 #define RBIE INTCON_bits.RBIE
425 #define INTE INTCON_bits.INTE
426 #define TMR0IE INTCON_bits.TMR0IE
427 #define PEIE INTCON_bits.PEIE
428 #define GIE INTCON_bits.GIE
429 #endif /* NO_BIT_DEFINES */
431 // ----- OPTION_REG bits --------------------
438 unsigned char T0SE:1;
439 unsigned char T0CS:1;
440 unsigned char INTEDG:1;
441 unsigned char NOT_RBPU:1;
443 } __OPTION_REG_bits_t;
444 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
446 #ifndef NO_BIT_DEFINES
447 #define PS0 OPTION_REG_bits.PS0
448 #define PS1 OPTION_REG_bits.PS1
449 #define PS2 OPTION_REG_bits.PS2
450 #define PSA OPTION_REG_bits.PSA
451 #define T0SE OPTION_REG_bits.T0SE
452 #define T0CS OPTION_REG_bits.T0CS
453 #define INTEDG OPTION_REG_bits.INTEDG
454 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
455 #endif /* NO_BIT_DEFINES */
457 // ----- OSCCON bits --------------------
460 unsigned char SCS0:1;
461 unsigned char SCS1:1;
462 unsigned char IOFS:1;
463 unsigned char OSTS:1;
464 unsigned char IRCF0:1;
465 unsigned char IRCF1:1;
466 unsigned char IRCF2:1;
470 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
472 #ifndef NO_BIT_DEFINES
473 #define SCS0 OSCCON_bits.SCS0
474 #define SCS1 OSCCON_bits.SCS1
475 #define IOFS OSCCON_bits.IOFS
476 #define OSTS OSCCON_bits.OSTS
477 #define IRCF0 OSCCON_bits.IRCF0
478 #define IRCF1 OSCCON_bits.IRCF1
479 #define IRCF2 OSCCON_bits.IRCF2
480 #endif /* NO_BIT_DEFINES */
482 // ----- OSCTUNE bits --------------------
485 unsigned char TUN0:1;
486 unsigned char TUN1:1;
487 unsigned char TUN2:1;
488 unsigned char TUN3:1;
489 unsigned char TUN4:1;
490 unsigned char TUN5:1;
495 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
497 #ifndef NO_BIT_DEFINES
498 #define TUN0 OSCTUNE_bits.TUN0
499 #define TUN1 OSCTUNE_bits.TUN1
500 #define TUN2 OSCTUNE_bits.TUN2
501 #define TUN3 OSCTUNE_bits.TUN3
502 #define TUN4 OSCTUNE_bits.TUN4
503 #define TUN5 OSCTUNE_bits.TUN5
504 #endif /* NO_BIT_DEFINES */
506 // ----- PCON bits --------------------
509 unsigned char NOT_BO:1;
510 unsigned char NOT_POR:1;
519 unsigned char NOT_BOR:1;
529 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
531 #ifndef NO_BIT_DEFINES
532 #define NOT_BO PCON_bits.NOT_BO
533 #define NOT_BOR PCON_bits.NOT_BOR
534 #define NOT_POR PCON_bits.NOT_POR
535 #endif /* NO_BIT_DEFINES */
537 // ----- PIE1 bits --------------------
540 unsigned char TMR1IE:1;
541 unsigned char TMR2IE:1;
542 unsigned char CCP1IE:1;
543 unsigned char SSPIE:1;
544 unsigned char TXIE:1;
545 unsigned char RCIE:1;
550 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
552 #ifndef NO_BIT_DEFINES
553 #define TMR1IE PIE1_bits.TMR1IE
554 #define TMR2IE PIE1_bits.TMR2IE
555 #define CCP1IE PIE1_bits.CCP1IE
556 #define SSPIE PIE1_bits.SSPIE
557 #define TXIE PIE1_bits.TXIE
558 #define RCIE PIE1_bits.RCIE
559 #endif /* NO_BIT_DEFINES */
561 // ----- PIE2 bits --------------------
568 unsigned char EEIE:1;
570 unsigned char CMIE:1;
571 unsigned char OSFIE:1;
574 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
576 #ifndef NO_BIT_DEFINES
577 #define EEIE PIE2_bits.EEIE
578 #define CMIE PIE2_bits.CMIE
579 #define OSFIE PIE2_bits.OSFIE
580 #endif /* NO_BIT_DEFINES */
582 // ----- PIR1 bits --------------------
585 unsigned char TMR1IF:1;
586 unsigned char TMR2IF:1;
587 unsigned char CCP1IF:1;
588 unsigned char SSPIF:1;
589 unsigned char TXIF:1;
590 unsigned char RCIF:1;
595 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
597 #ifndef NO_BIT_DEFINES
598 #define TMR1IF PIR1_bits.TMR1IF
599 #define TMR2IF PIR1_bits.TMR2IF
600 #define CCP1IF PIR1_bits.CCP1IF
601 #define SSPIF PIR1_bits.SSPIF
602 #define TXIF PIR1_bits.TXIF
603 #define RCIF PIR1_bits.RCIF
604 #endif /* NO_BIT_DEFINES */
606 // ----- PIR2 bits --------------------
613 unsigned char EEIF:1;
615 unsigned char CMIF:1;
616 unsigned char OSFIF:1;
619 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
621 #ifndef NO_BIT_DEFINES
622 #define EEIF PIR2_bits.EEIF
623 #define CMIF PIR2_bits.CMIF
624 #define OSFIF PIR2_bits.OSFIF
625 #endif /* NO_BIT_DEFINES */
627 // ----- PORTA bits --------------------
640 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
642 #ifndef NO_BIT_DEFINES
643 #define RA0 PORTA_bits.RA0
644 #define RA1 PORTA_bits.RA1
645 #define RA2 PORTA_bits.RA2
646 #define RA3 PORTA_bits.RA3
647 #define RA4 PORTA_bits.RA4
648 #define RA5 PORTA_bits.RA5
649 #endif /* NO_BIT_DEFINES */
651 // ----- PORTB bits --------------------
664 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
666 #ifndef NO_BIT_DEFINES
667 #define RB0 PORTB_bits.RB0
668 #define RB1 PORTB_bits.RB1
669 #define RB2 PORTB_bits.RB2
670 #define RB3 PORTB_bits.RB3
671 #define RB4 PORTB_bits.RB4
672 #define RB5 PORTB_bits.RB5
673 #define RB6 PORTB_bits.RB6
674 #define RB7 PORTB_bits.RB7
675 #endif /* NO_BIT_DEFINES */
677 // ----- RCSTA bits --------------------
680 unsigned char RX9D:1;
681 unsigned char OERR:1;
682 unsigned char FERR:1;
683 unsigned char ADDEN:1;
684 unsigned char CREN:1;
685 unsigned char SREN:1;
687 unsigned char SPEN:1;
690 unsigned char RCD8:1;
706 unsigned char NOT_RC8:1;
716 unsigned char RC8_9:1;
720 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
722 #ifndef NO_BIT_DEFINES
723 #define RX9D RCSTA_bits.RX9D
724 #define RCD8 RCSTA_bits.RCD8
725 #define OERR RCSTA_bits.OERR
726 #define FERR RCSTA_bits.FERR
727 #define ADDEN RCSTA_bits.ADDEN
728 #define CREN RCSTA_bits.CREN
729 #define SREN RCSTA_bits.SREN
730 #define RX9 RCSTA_bits.RX9
731 #define RC9 RCSTA_bits.RC9
732 #define NOT_RC8 RCSTA_bits.NOT_RC8
733 #define RC8_9 RCSTA_bits.RC8_9
734 #define SPEN RCSTA_bits.SPEN
735 #endif /* NO_BIT_DEFINES */
737 // ----- SSPCON bits --------------------
740 unsigned char SSPM0:1;
741 unsigned char SSPM1:1;
742 unsigned char SSPM2:1;
743 unsigned char SSPM3:1;
745 unsigned char SSPEN:1;
746 unsigned char SSPOV:1;
747 unsigned char WCOL:1;
750 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
752 #ifndef NO_BIT_DEFINES
753 #define SSPM0 SSPCON_bits.SSPM0
754 #define SSPM1 SSPCON_bits.SSPM1
755 #define SSPM2 SSPCON_bits.SSPM2
756 #define SSPM3 SSPCON_bits.SSPM3
757 #define CKP SSPCON_bits.CKP
758 #define SSPEN SSPCON_bits.SSPEN
759 #define SSPOV SSPCON_bits.SSPOV
760 #define WCOL SSPCON_bits.WCOL
761 #endif /* NO_BIT_DEFINES */
763 // ----- SSPSTAT bits --------------------
778 unsigned char I2C_READ:1;
779 unsigned char I2C_START:1;
780 unsigned char I2C_STOP:1;
781 unsigned char I2C_DATA:1;
788 unsigned char NOT_W:1;
791 unsigned char NOT_A:1;
798 unsigned char NOT_WRITE:1;
801 unsigned char NOT_ADDRESS:1;
818 unsigned char READ_WRITE:1;
821 unsigned char DATA_ADDRESS:1;
826 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
828 #ifndef NO_BIT_DEFINES
829 #define BF SSPSTAT_bits.BF
830 #define UA SSPSTAT_bits.UA
831 #define R SSPSTAT_bits.R
832 #define I2C_READ SSPSTAT_bits.I2C_READ
833 #define NOT_W SSPSTAT_bits.NOT_W
834 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
835 #define R_W SSPSTAT_bits.R_W
836 #define READ_WRITE SSPSTAT_bits.READ_WRITE
837 #define S SSPSTAT_bits.S
838 #define I2C_START SSPSTAT_bits.I2C_START
839 #define P SSPSTAT_bits.P
840 #define I2C_STOP SSPSTAT_bits.I2C_STOP
841 #define D SSPSTAT_bits.D
842 #define I2C_DATA SSPSTAT_bits.I2C_DATA
843 #define NOT_A SSPSTAT_bits.NOT_A
844 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
845 #define D_A SSPSTAT_bits.D_A
846 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
847 #define CKE SSPSTAT_bits.CKE
848 #define SMP SSPSTAT_bits.SMP
849 #endif /* NO_BIT_DEFINES */
851 // ----- STATUS bits --------------------
857 unsigned char NOT_PD:1;
858 unsigned char NOT_TO:1;
864 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
866 #ifndef NO_BIT_DEFINES
867 #define C STATUS_bits.C
868 #define DC STATUS_bits.DC
869 #define Z STATUS_bits.Z
870 #define NOT_PD STATUS_bits.NOT_PD
871 #define NOT_TO STATUS_bits.NOT_TO
872 #define RP0 STATUS_bits.RP0
873 #define RP1 STATUS_bits.RP1
874 #define IRP STATUS_bits.IRP
875 #endif /* NO_BIT_DEFINES */
877 // ----- T1CON bits --------------------
880 unsigned char TMR1ON:1;
881 unsigned char TMR1CS:1;
882 unsigned char NOT_T1SYNC:1;
883 unsigned char T1OSCEN:1;
884 unsigned char T1CKPS0:1;
885 unsigned char T1CKPS1:1;
886 unsigned char T1RUN:1;
892 unsigned char T1INSYNC:1;
900 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
902 #ifndef NO_BIT_DEFINES
903 #define TMR1ON T1CON_bits.TMR1ON
904 #define TMR1CS T1CON_bits.TMR1CS
905 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
906 #define T1INSYNC T1CON_bits.T1INSYNC
907 #define T1OSCEN T1CON_bits.T1OSCEN
908 #define T1CKPS0 T1CON_bits.T1CKPS0
909 #define T1CKPS1 T1CON_bits.T1CKPS1
910 #define T1RUN T1CON_bits.T1RUN
911 #endif /* NO_BIT_DEFINES */
913 // ----- T2CON bits --------------------
916 unsigned char T2CKPS0:1;
917 unsigned char T2CKPS1:1;
918 unsigned char TMR2ON:1;
919 unsigned char TOUTPS0:1;
920 unsigned char TOUTPS1:1;
921 unsigned char TOUTPS2:1;
922 unsigned char TOUTPS3:1;
926 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
928 #ifndef NO_BIT_DEFINES
929 #define T2CKPS0 T2CON_bits.T2CKPS0
930 #define T2CKPS1 T2CON_bits.T2CKPS1
931 #define TMR2ON T2CON_bits.TMR2ON
932 #define TOUTPS0 T2CON_bits.TOUTPS0
933 #define TOUTPS1 T2CON_bits.TOUTPS1
934 #define TOUTPS2 T2CON_bits.TOUTPS2
935 #define TOUTPS3 T2CON_bits.TOUTPS3
936 #endif /* NO_BIT_DEFINES */
938 // ----- TRISA bits --------------------
941 unsigned char TRISA0:1;
942 unsigned char TRISA1:1;
943 unsigned char TRISA2:1;
944 unsigned char TRISA3:1;
945 unsigned char TRISA4:1;
946 unsigned char TRISA5:1;
951 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
953 #ifndef NO_BIT_DEFINES
954 #define TRISA0 TRISA_bits.TRISA0
955 #define TRISA1 TRISA_bits.TRISA1
956 #define TRISA2 TRISA_bits.TRISA2
957 #define TRISA3 TRISA_bits.TRISA3
958 #define TRISA4 TRISA_bits.TRISA4
959 #define TRISA5 TRISA_bits.TRISA5
960 #endif /* NO_BIT_DEFINES */
962 // ----- TRISB bits --------------------
965 unsigned char TRISB0:1;
966 unsigned char TRISB1:1;
967 unsigned char TRISB2:1;
968 unsigned char TRISB3:1;
969 unsigned char TRISB4:1;
970 unsigned char TRISB5:1;
971 unsigned char TRISB6:1;
972 unsigned char TRISB7:1;
975 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
977 #ifndef NO_BIT_DEFINES
978 #define TRISB0 TRISB_bits.TRISB0
979 #define TRISB1 TRISB_bits.TRISB1
980 #define TRISB2 TRISB_bits.TRISB2
981 #define TRISB3 TRISB_bits.TRISB3
982 #define TRISB4 TRISB_bits.TRISB4
983 #define TRISB5 TRISB_bits.TRISB5
984 #define TRISB6 TRISB_bits.TRISB6
985 #define TRISB7 TRISB_bits.TRISB7
986 #endif /* NO_BIT_DEFINES */
988 // ----- TXSTA bits --------------------
991 unsigned char TX9D:1;
992 unsigned char TRMT:1;
993 unsigned char BRGH:1;
995 unsigned char SYNC:1;
996 unsigned char TXEN:1;
998 unsigned char CSRC:1;
1001 unsigned char TXD8:1;
1007 unsigned char NOT_TX8:1;
1017 unsigned char TX8_9:1;
1021 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1023 #ifndef NO_BIT_DEFINES
1024 #define TX9D TXSTA_bits.TX9D
1025 #define TXD8 TXSTA_bits.TXD8
1026 #define TRMT TXSTA_bits.TRMT
1027 #define BRGH TXSTA_bits.BRGH
1028 #define SYNC TXSTA_bits.SYNC
1029 #define TXEN TXSTA_bits.TXEN
1030 #define TX9 TXSTA_bits.TX9
1031 #define NOT_TX8 TXSTA_bits.NOT_TX8
1032 #define TX8_9 TXSTA_bits.TX8_9
1033 #define CSRC TXSTA_bits.CSRC
1034 #endif /* NO_BIT_DEFINES */
1036 // ----- WDTCON bits --------------------
1039 unsigned char SWDTEN:1;
1040 unsigned char WDTPS0:1;
1041 unsigned char WDTPS1:1;
1042 unsigned char WDTPS2:1;
1043 unsigned char WDTPS3:1;
1049 unsigned char SWDTE:1;
1059 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1061 #ifndef NO_BIT_DEFINES
1062 #define SWDTEN WDTCON_bits.SWDTEN
1063 #define SWDTE WDTCON_bits.SWDTE
1064 #define WDTPS0 WDTCON_bits.WDTPS0
1065 #define WDTPS1 WDTCON_bits.WDTPS1
1066 #define WDTPS2 WDTCON_bits.WDTPS2
1067 #define WDTPS3 WDTCON_bits.WDTPS3
1068 #endif /* NO_BIT_DEFINES */