2 // Register Declarations for Microchip 16F84A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define EEDATA_ADDR 0x0008
36 #define EEADR_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define EECON1_ADDR 0x0088
43 #define EECON2_ADDR 0x0089
46 // Memory organization.
52 // P16F84A.INC Standard Header File, Version 2.00 Microchip Technology, Inc.
55 // This header file defines configurations, registers, and other useful bits of
56 // information for the PIC16F84 microcontroller. These names are taken to match
57 // the data sheets as closely as possible.
59 // Note that the processor must be selected before this file is
60 // included. The processor may be selected the following ways:
62 // 1. Command line switch:
63 // C:\ MPASM MYFILE.ASM /PIC16F84A
64 // 2. LIST directive in the source file
66 // 3. Processor Type entry in the MPASM full-screen interface
68 //==========================================================================
72 //==========================================================================
76 //1.00 2/15/99 Initial Release
78 //==========================================================================
82 //==========================================================================
85 // MESSG "Processor-header file mismatch. Verify selected processor."
88 //==========================================================================
90 // Register Definitions
92 //==========================================================================
97 //----- Register Files------------------------------------------------------
99 extern __sfr __at (INDF_ADDR) INDF;
100 extern __sfr __at (TMR0_ADDR) TMR0;
101 extern __sfr __at (PCL_ADDR) PCL;
102 extern __sfr __at (STATUS_ADDR) STATUS;
103 extern __sfr __at (FSR_ADDR) FSR;
104 extern __sfr __at (PORTA_ADDR) PORTA;
105 extern __sfr __at (PORTB_ADDR) PORTB;
106 extern __sfr __at (EEDATA_ADDR) EEDATA;
107 extern __sfr __at (EEADR_ADDR) EEADR;
108 extern __sfr __at (PCLATH_ADDR) PCLATH;
109 extern __sfr __at (INTCON_ADDR) INTCON;
111 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
112 extern __sfr __at (TRISA_ADDR) TRISA;
113 extern __sfr __at (TRISB_ADDR) TRISB;
114 extern __sfr __at (EECON1_ADDR) EECON1;
115 extern __sfr __at (EECON2_ADDR) EECON2;
117 //----- STATUS Bits --------------------------------------------------------
120 //----- INTCON Bits --------------------------------------------------------
123 //----- OPTION_REG Bits ----------------------------------------------------
126 //----- EECON1 Bits --------------------------------------------------------
129 //==========================================================================
133 //==========================================================================
136 // __BADRAM H'07', H'50'-H'7F', H'87'
138 //==========================================================================
140 // Configuration Bits
142 //==========================================================================
144 #define _CP_ON 0x000F
145 #define _CP_OFF 0x3FFF
146 #define _PWRTE_ON 0x3FF7
147 #define _PWRTE_OFF 0x3FFF
148 #define _WDT_ON 0x3FFF
149 #define _WDT_OFF 0x3FFB
150 #define _LP_OSC 0x3FFC
151 #define _XT_OSC 0x3FFD
152 #define _HS_OSC 0x3FFE
153 #define _RC_OSC 0x3FFF
157 // ----- EECON1 bits --------------------
162 unsigned char WREN:1;
163 unsigned char WRERR:1;
164 unsigned char EEIF:1;
170 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
172 #ifndef NO_BIT_DEFINES
173 #define RD EECON1_bits.RD
174 #define WR EECON1_bits.WR
175 #define WREN EECON1_bits.WREN
176 #define WRERR EECON1_bits.WRERR
177 #define EEIF EECON1_bits.EEIF
178 #endif /* NO_BIT_DEFINES */
180 // ----- INTCON bits --------------------
183 unsigned char RBIF:1;
184 unsigned char INTF:1;
185 unsigned char T0IF:1;
186 unsigned char RBIE:1;
187 unsigned char INTE:1;
188 unsigned char T0IE:1;
189 unsigned char EEIE:1;
193 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
195 #ifndef NO_BIT_DEFINES
196 #define RBIF INTCON_bits.RBIF
197 #define INTF INTCON_bits.INTF
198 #define T0IF INTCON_bits.T0IF
199 #define RBIE INTCON_bits.RBIE
200 #define INTE INTCON_bits.INTE
201 #define T0IE INTCON_bits.T0IE
202 #define EEIE INTCON_bits.EEIE
203 #define GIE INTCON_bits.GIE
204 #endif /* NO_BIT_DEFINES */
206 // ----- OPTION_REG bits --------------------
213 unsigned char T0SE:1;
214 unsigned char T0CS:1;
215 unsigned char INTEDG:1;
216 unsigned char NOT_RBPU:1;
218 } __OPTION_REG_bits_t;
219 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
221 #ifndef NO_BIT_DEFINES
222 #define PS0 OPTION_REG_bits.PS0
223 #define PS1 OPTION_REG_bits.PS1
224 #define PS2 OPTION_REG_bits.PS2
225 #define PSA OPTION_REG_bits.PSA
226 #define T0SE OPTION_REG_bits.T0SE
227 #define T0CS OPTION_REG_bits.T0CS
228 #define INTEDG OPTION_REG_bits.INTEDG
229 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
230 #endif /* NO_BIT_DEFINES */
232 // ----- PORTA bits --------------------
245 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
247 #ifndef NO_BIT_DEFINES
248 #define RA0 PORTA_bits.RA0
249 #define RA1 PORTA_bits.RA1
250 #define RA2 PORTA_bits.RA2
251 #define RA3 PORTA_bits.RA3
252 #define RA4 PORTA_bits.RA4
253 #define RA5 PORTA_bits.RA5
254 #endif /* NO_BIT_DEFINES */
256 // ----- PORTB bits --------------------
269 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
271 #ifndef NO_BIT_DEFINES
272 #define RB0 PORTB_bits.RB0
273 #define RB1 PORTB_bits.RB1
274 #define RB2 PORTB_bits.RB2
275 #define RB3 PORTB_bits.RB3
276 #define RB4 PORTB_bits.RB4
277 #define RB5 PORTB_bits.RB5
278 #define RB6 PORTB_bits.RB6
279 #define RB7 PORTB_bits.RB7
280 #endif /* NO_BIT_DEFINES */
282 // ----- STATUS bits --------------------
288 unsigned char NOT_PD:1;
289 unsigned char NOT_TO:1;
295 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
297 #ifndef NO_BIT_DEFINES
298 #define C STATUS_bits.C
299 #define DC STATUS_bits.DC
300 #define Z STATUS_bits.Z
301 #define NOT_PD STATUS_bits.NOT_PD
302 #define NOT_TO STATUS_bits.NOT_TO
303 #define RP0 STATUS_bits.RP0
304 #define RP1 STATUS_bits.RP1
305 #define IRP STATUS_bits.IRP
306 #endif /* NO_BIT_DEFINES */
308 // ----- TRISA bits --------------------
311 unsigned char TRISA0:1;
312 unsigned char TRISA1:1;
313 unsigned char TRISA2:1;
314 unsigned char TRISA3:1;
315 unsigned char TRISA4:1;
316 unsigned char TRISA5:1;
321 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
323 #ifndef NO_BIT_DEFINES
324 #define TRISA0 TRISA_bits.TRISA0
325 #define TRISA1 TRISA_bits.TRISA1
326 #define TRISA2 TRISA_bits.TRISA2
327 #define TRISA3 TRISA_bits.TRISA3
328 #define TRISA4 TRISA_bits.TRISA4
329 #define TRISA5 TRISA_bits.TRISA5
330 #endif /* NO_BIT_DEFINES */
332 // ----- TRISB bits --------------------
335 unsigned char TRISB0:1;
336 unsigned char TRISB1:1;
337 unsigned char TRISB2:1;
338 unsigned char TRISB3:1;
339 unsigned char TRISB4:1;
340 unsigned char TRISB5:1;
341 unsigned char TRISB6:1;
342 unsigned char TRISB7:1;
345 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
347 #ifndef NO_BIT_DEFINES
348 #define TRISB0 TRISB_bits.TRISB0
349 #define TRISB1 TRISB_bits.TRISB1
350 #define TRISB2 TRISB_bits.TRISB2
351 #define TRISB3 TRISB_bits.TRISB3
352 #define TRISB4 TRISB_bits.TRISB4
353 #define TRISB5 TRISB_bits.TRISB5
354 #define TRISB6 TRISB_bits.TRISB6
355 #define TRISB7 TRISB_bits.TRISB7
356 #endif /* NO_BIT_DEFINES */