2 // Register Declarations for Microchip 16F84 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define EEDATA_ADDR 0x0008
36 #define EEADR_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define EECON1_ADDR 0x0088
43 #define EECON2_ADDR 0x0089
46 // Memory organization.
52 // P16F84.INC Standard Header File, Version 2.00 Microchip Technology, Inc.
55 // This header file defines configurations, registers, and other useful bits of
56 // information for the PIC16F84 microcontroller. These names are taken to match
57 // the data sheets as closely as possible.
59 // Note that the processor must be selected before this file is
60 // included. The processor may be selected the following ways:
62 // 1. Command line switch:
63 // C:\ MPASM MYFILE.ASM /PIC16F84
64 // 2. LIST directive in the source file
66 // 3. Processor Type entry in the MPASM full-screen interface
68 //==========================================================================
72 //==========================================================================
76 //2.00 07/24/96 Renamed to reflect the name change to PIC16F84.
77 //1.01 05/17/96 Corrected BADRAM map
78 //1.00 10/31/95 Initial Release
80 //==========================================================================
84 //==========================================================================
87 // MESSG "Processor-header file mismatch. Verify selected processor."
90 //==========================================================================
92 // Register Definitions
94 //==========================================================================
99 //----- Register Files------------------------------------------------------
101 extern __data __at (INDF_ADDR) volatile char INDF;
102 extern __sfr __at (TMR0_ADDR) TMR0;
103 extern __data __at (PCL_ADDR) volatile char PCL;
104 extern __sfr __at (STATUS_ADDR) STATUS;
105 extern __sfr __at (FSR_ADDR) FSR;
106 extern __sfr __at (PORTA_ADDR) PORTA;
107 extern __sfr __at (PORTB_ADDR) PORTB;
108 extern __sfr __at (EEDATA_ADDR) EEDATA;
109 extern __sfr __at (EEADR_ADDR) EEADR;
110 extern __sfr __at (PCLATH_ADDR) PCLATH;
111 extern __sfr __at (INTCON_ADDR) INTCON;
113 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
114 extern __sfr __at (TRISA_ADDR) TRISA;
115 extern __sfr __at (TRISB_ADDR) TRISB;
116 extern __sfr __at (EECON1_ADDR) EECON1;
117 extern __sfr __at (EECON2_ADDR) EECON2;
119 //----- STATUS Bits --------------------------------------------------------
122 //----- INTCON Bits --------------------------------------------------------
125 //----- OPTION Bits --------------------------------------------------------
128 //----- EECON1 Bits --------------------------------------------------------
131 //==========================================================================
135 //==========================================================================
138 // __BADRAM H'07', H'50'-H'7F', H'87'
140 //==========================================================================
142 // Configuration Bits
144 //==========================================================================
146 #define _CP_ON 0x000F
147 #define _CP_OFF 0x3FFF
148 #define _PWRTE_ON 0x3FF7
149 #define _PWRTE_OFF 0x3FFF
150 #define _WDT_ON 0x3FFF
151 #define _WDT_OFF 0x3FFB
152 #define _LP_OSC 0x3FFC
153 #define _XT_OSC 0x3FFD
154 #define _HS_OSC 0x3FFE
155 #define _RC_OSC 0x3FFF
159 // ----- EECON1 bits --------------------
164 unsigned char WREN:1;
165 unsigned char WRERR:1;
166 unsigned char EEIF:1;
172 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
174 #define RD EECON1_bits.RD
175 #define WR EECON1_bits.WR
176 #define WREN EECON1_bits.WREN
177 #define WRERR EECON1_bits.WRERR
178 #define EEIF EECON1_bits.EEIF
180 // ----- INTCON bits --------------------
183 unsigned char RBIF:1;
184 unsigned char INTF:1;
185 unsigned char T0IF:1;
186 unsigned char RBIE:1;
187 unsigned char INTE:1;
188 unsigned char T0IE:1;
189 unsigned char EEIE:1;
193 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
195 #define RBIF INTCON_bits.RBIF
196 #define INTF INTCON_bits.INTF
197 #define T0IF INTCON_bits.T0IF
198 #define RBIE INTCON_bits.RBIE
199 #define INTE INTCON_bits.INTE
200 #define T0IE INTCON_bits.T0IE
201 #define EEIE INTCON_bits.EEIE
202 #define GIE INTCON_bits.GIE
204 // ----- OPTION_REG bits --------------------
211 unsigned char T0SE:1;
212 unsigned char T0CS:1;
213 unsigned char INTEDG:1;
214 unsigned char NOT_RBPU:1;
216 } __OPTION_REG_bits_t;
217 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
219 #define PS0 OPTION_REG_bits.PS0
220 #define PS1 OPTION_REG_bits.PS1
221 #define PS2 OPTION_REG_bits.PS2
222 #define PSA OPTION_REG_bits.PSA
223 #define T0SE OPTION_REG_bits.T0SE
224 #define T0CS OPTION_REG_bits.T0CS
225 #define INTEDG OPTION_REG_bits.INTEDG
226 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
228 // ----- PORTA bits --------------------
241 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
243 #define RA0 PORTA_bits.RA0
244 #define RA1 PORTA_bits.RA1
245 #define RA2 PORTA_bits.RA2
246 #define RA3 PORTA_bits.RA3
247 #define RA4 PORTA_bits.RA4
249 // ----- PORTB bits --------------------
262 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
264 #define RB0 PORTB_bits.RB0
265 #define RB1 PORTB_bits.RB1
266 #define RB2 PORTB_bits.RB2
267 #define RB3 PORTB_bits.RB3
268 #define RB4 PORTB_bits.RB4
269 #define RB5 PORTB_bits.RB5
270 #define RB6 PORTB_bits.RB6
271 #define RB7 PORTB_bits.RB7
273 // ----- STATUS bits --------------------
279 unsigned char NOT_PD:1;
280 unsigned char NOT_TO:1;
286 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
288 #define C STATUS_bits.C
289 #define DC STATUS_bits.DC
290 #define Z STATUS_bits.Z
291 #define NOT_PD STATUS_bits.NOT_PD
292 #define NOT_TO STATUS_bits.NOT_TO
293 #define RP0 STATUS_bits.RP0
294 #define RP1 STATUS_bits.RP1
295 #define IRP STATUS_bits.IRP
297 // ----- TRISA bits --------------------
300 unsigned char TRISA0:1;
301 unsigned char TRISA1:1;
302 unsigned char TRISA2:1;
303 unsigned char TRISA3:1;
304 unsigned char TRISA4:1;
310 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
312 #define TRISA0 TRISA_bits.TRISA0
313 #define TRISA1 TRISA_bits.TRISA1
314 #define TRISA2 TRISA_bits.TRISA2
315 #define TRISA3 TRISA_bits.TRISA3
316 #define TRISA4 TRISA_bits.TRISA4
318 // ----- TRISB bits --------------------
321 unsigned char TRISB0:1;
322 unsigned char TRISB1:1;
323 unsigned char TRISB2:1;
324 unsigned char TRISB3:1;
325 unsigned char TRISB4:1;
326 unsigned char TRISB5:1;
327 unsigned char TRISB6:1;
328 unsigned char TRISB7:1;
331 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
333 #define TRISB0 TRISB_bits.TRISB0
334 #define TRISB1 TRISB_bits.TRISB1
335 #define TRISB2 TRISB_bits.TRISB2
336 #define TRISB3 TRISB_bits.TRISB3
337 #define TRISB4 TRISB_bits.TRISB4
338 #define TRISB5 TRISB_bits.TRISB5
339 #define TRISB6 TRISB_bits.TRISB6
340 #define TRISB7 TRISB_bits.TRISB7