2 // Register Declarations for Microchip 16F84 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define EEDATA_ADDR 0x0008
36 #define EEADR_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define EECON1_ADDR 0x0088
43 #define EECON2_ADDR 0x0089
46 // Memory organization.
49 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
50 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
51 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
52 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
53 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
54 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
55 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
56 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
57 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
58 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
59 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
60 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
61 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
62 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
63 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
64 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
68 // P16F84.INC Standard Header File, Version 2.00 Microchip Technology, Inc.
71 // This header file defines configurations, registers, and other useful bits of
72 // information for the PIC16F84 microcontroller. These names are taken to match
73 // the data sheets as closely as possible.
75 // Note that the processor must be selected before this file is
76 // included. The processor may be selected the following ways:
78 // 1. Command line switch:
79 // C:\ MPASM MYFILE.ASM /PIC16F84
80 // 2. LIST directive in the source file
82 // 3. Processor Type entry in the MPASM full-screen interface
84 //==========================================================================
88 //==========================================================================
92 //2.00 07/24/96 Renamed to reflect the name change to PIC16F84.
93 //1.01 05/17/96 Corrected BADRAM map
94 //1.00 10/31/95 Initial Release
96 //==========================================================================
100 //==========================================================================
103 // MESSG "Processor-header file mismatch. Verify selected processor."
106 //==========================================================================
108 // Register Definitions
110 //==========================================================================
115 //----- Register Files------------------------------------------------------
117 extern __data __at (INDF_ADDR) volatile char INDF;
118 extern __sfr __at (TMR0_ADDR) TMR0;
119 extern __data __at (PCL_ADDR) volatile char PCL;
120 extern __sfr __at (STATUS_ADDR) STATUS;
121 extern __sfr __at (FSR_ADDR) FSR;
122 extern __sfr __at (PORTA_ADDR) PORTA;
123 extern __sfr __at (PORTB_ADDR) PORTB;
124 extern __sfr __at (EEDATA_ADDR) EEDATA;
125 extern __sfr __at (EEADR_ADDR) EEADR;
126 extern __sfr __at (PCLATH_ADDR) PCLATH;
127 extern __sfr __at (INTCON_ADDR) INTCON;
129 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
130 extern __sfr __at (TRISA_ADDR) TRISA;
131 extern __sfr __at (TRISB_ADDR) TRISB;
132 extern __sfr __at (EECON1_ADDR) EECON1;
133 extern __sfr __at (EECON2_ADDR) EECON2;
135 //----- STATUS Bits --------------------------------------------------------
138 //----- INTCON Bits --------------------------------------------------------
141 //----- OPTION Bits --------------------------------------------------------
144 //----- EECON1 Bits --------------------------------------------------------
147 //==========================================================================
151 //==========================================================================
154 // __BADRAM H'07', H'50'-H'7F', H'87'
156 //==========================================================================
158 // Configuration Bits
160 //==========================================================================
162 #define _CP_ON 0x000F
163 #define _CP_OFF 0x3FFF
164 #define _PWRTE_ON 0x3FF7
165 #define _PWRTE_OFF 0x3FFF
166 #define _WDT_ON 0x3FFF
167 #define _WDT_OFF 0x3FFB
168 #define _LP_OSC 0x3FFC
169 #define _XT_OSC 0x3FFD
170 #define _HS_OSC 0x3FFE
171 #define _RC_OSC 0x3FFF
175 // ----- EECON1 bits --------------------
180 unsigned char WREN:1;
181 unsigned char WRERR:1;
182 unsigned char EEIF:1;
188 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
190 #define RD EECON1_bits.RD
191 #define WR EECON1_bits.WR
192 #define WREN EECON1_bits.WREN
193 #define WRERR EECON1_bits.WRERR
194 #define EEIF EECON1_bits.EEIF
196 // ----- INTCON bits --------------------
199 unsigned char RBIF:1;
200 unsigned char INTF:1;
201 unsigned char T0IF:1;
202 unsigned char RBIE:1;
203 unsigned char INTE:1;
204 unsigned char T0IE:1;
205 unsigned char EEIE:1;
209 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
211 #define RBIF INTCON_bits.RBIF
212 #define INTF INTCON_bits.INTF
213 #define T0IF INTCON_bits.T0IF
214 #define RBIE INTCON_bits.RBIE
215 #define INTE INTCON_bits.INTE
216 #define T0IE INTCON_bits.T0IE
217 #define EEIE INTCON_bits.EEIE
218 #define GIE INTCON_bits.GIE
220 // ----- OPTION_REG bits --------------------
227 unsigned char T0SE:1;
228 unsigned char T0CS:1;
229 unsigned char INTEDG:1;
230 unsigned char NOT_RBPU:1;
232 } __OPTION_REG_bits_t;
233 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
235 #define PS0 OPTION_REG_bits.PS0
236 #define PS1 OPTION_REG_bits.PS1
237 #define PS2 OPTION_REG_bits.PS2
238 #define PSA OPTION_REG_bits.PSA
239 #define T0SE OPTION_REG_bits.T0SE
240 #define T0CS OPTION_REG_bits.T0CS
241 #define INTEDG OPTION_REG_bits.INTEDG
242 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
244 // ----- STATUS bits --------------------
250 unsigned char NOT_PD:1;
251 unsigned char NOT_TO:1;
257 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
259 #define C STATUS_bits.C
260 #define DC STATUS_bits.DC
261 #define Z STATUS_bits.Z
262 #define NOT_PD STATUS_bits.NOT_PD
263 #define NOT_TO STATUS_bits.NOT_TO
264 #define RP0 STATUS_bits.RP0
265 #define RP1 STATUS_bits.RP1
266 #define IRP STATUS_bits.IRP