2 // Register Declarations for Microchip 16F819 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRESH_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define PR2_ADDR 0x0092
60 #define SSPADD_ADDR 0x0093
61 #define SSPSTAT_ADDR 0x0094
62 #define ADRESL_ADDR 0x009E
63 #define ADCON1_ADDR 0x009F
64 #define EEDATA_ADDR 0x010C
65 #define EEADR_ADDR 0x010D
66 #define EEDATH_ADDR 0x010E
67 #define EEADRH_ADDR 0x010F
68 #define EECON1_ADDR 0x018C
69 #define EECON2_ADDR 0x018D
72 // Memory organization.
75 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
76 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
77 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
78 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
79 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
80 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
81 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
82 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
83 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
84 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
85 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
86 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
87 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
88 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
89 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
90 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
91 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
92 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
93 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
94 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
95 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
96 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
97 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
98 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
99 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
100 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
101 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
102 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
103 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
104 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
105 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
106 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
107 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
108 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
109 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
110 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
111 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
112 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
113 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
114 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
115 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
116 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
120 // P16F819.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
123 // This header file defines configurations, registers, and other useful bits of
124 // information for the PIC16F819 microcontroller. These names are taken to match
125 // the data sheets as closely as possible.
127 // Note that the processor must be selected before this file is
128 // included. The processor may be selected the following ways:
130 // 1. Command line switch:
131 // C:\ MPASM MYFILE.ASM /PIC16F819
132 // 2. LIST directive in the source file
134 // 3. Processor Type entry in the MPASM full-screen interface
136 //==========================================================================
140 //==========================================================================
144 //1.00 06/15/02 Initial Release
145 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
147 //==========================================================================
151 //==========================================================================
154 // MESSG "Processor-header file mismatch. Verify selected processor."
157 //==========================================================================
159 // Register Definitions
161 //==========================================================================
166 //----- Register Files------------------------------------------------------
168 extern __data __at (INDF_ADDR) volatile char INDF;
169 extern __sfr __at (TMR0_ADDR) TMR0;
170 extern __data __at (PCL_ADDR) volatile char PCL;
171 extern __sfr __at (STATUS_ADDR) STATUS;
172 extern __sfr __at (FSR_ADDR) FSR;
173 extern __sfr __at (PORTA_ADDR) PORTA;
174 extern __sfr __at (PORTB_ADDR) PORTB;
175 extern __sfr __at (PCLATH_ADDR) PCLATH;
176 extern __sfr __at (INTCON_ADDR) INTCON;
177 extern __sfr __at (PIR1_ADDR) PIR1;
178 extern __sfr __at (PIR2_ADDR) PIR2;
179 extern __sfr __at (TMR1L_ADDR) TMR1L;
180 extern __sfr __at (TMR1H_ADDR) TMR1H;
181 extern __sfr __at (T1CON_ADDR) T1CON;
182 extern __sfr __at (TMR2_ADDR) TMR2;
183 extern __sfr __at (T2CON_ADDR) T2CON;
184 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
185 extern __sfr __at (SSPCON_ADDR) SSPCON;
186 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
187 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
188 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
189 extern __sfr __at (ADRESH_ADDR) ADRESH;
190 extern __sfr __at (ADCON0_ADDR) ADCON0;
192 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
193 extern __sfr __at (TRISA_ADDR) TRISA;
194 extern __sfr __at (TRISB_ADDR) TRISB;
195 extern __sfr __at (PIE1_ADDR) PIE1;
196 extern __sfr __at (PIE2_ADDR) PIE2;
197 extern __sfr __at (PCON_ADDR) PCON;
198 extern __sfr __at (OSCCON_ADDR) OSCCON;
199 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
200 extern __sfr __at (PR2_ADDR) PR2;
201 extern __sfr __at (SSPADD_ADDR) SSPADD;
202 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
203 extern __sfr __at (ADRESL_ADDR) ADRESL;
204 extern __sfr __at (ADCON1_ADDR) ADCON1;
206 extern __sfr __at (EEDATA_ADDR) EEDATA;
207 extern __sfr __at (EEADR_ADDR) EEADR;
208 extern __sfr __at (EEDATH_ADDR) EEDATH;
209 extern __sfr __at (EEADRH_ADDR) EEADRH;
211 extern __sfr __at (EECON1_ADDR) EECON1;
212 extern __sfr __at (EECON2_ADDR) EECON2;
214 //----- STATUS Bits --------------------------------------------------------
217 //----- INTCON Bits --------------------------------------------------------
220 //----- PIR1 Bits ----------------------------------------------------------
223 //----- PIR2 Bits ----------------------------------------------------------
226 //----- T1CON Bits ---------------------------------------------------------
229 //----- T2CON Bits ---------------------------------------------------------
232 //----- SSPCON Bits --------------------------------------------------------
235 //----- CCP1CON Bits -------------------------------------------------------
238 //----- ADCON0 Bits --------------------------------------------------------
241 //----- OPTION Bits -----------------------------------------------------
244 //----- PIE1 Bits ----------------------------------------------------------
247 //----- PIE2 Bits ----------------------------------------------------------
250 //----- PCON Bits ----------------------------------------------------------
253 //----- OSCCON Bits -------------------------------------------------------
256 //----- OSCTUNE Bits -------------------------------------------------------
259 //----- SSPSTAT Bits -------------------------------------------------------
262 //----- ADCON1 Bits --------------------------------------------------------
265 //----- EECON1 Bits --------------------------------------------------------
268 //==========================================================================
272 //==========================================================================
275 // __BADRAM H'07'-H'09', H'18'-H'1D'
276 // __BADRAM H'87'-H'89', H'91', H'95'-H'9D'
277 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
278 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
280 //==========================================================================
282 // Configuration Bits
284 //==========================================================================
286 #define _CP_ALL 0x1FFF
287 #define _CP_OFF 0x3FFF
288 #define _CCP1_RB2 0x3FFF
289 #define _CCP1_RB3 0x2FFF
290 #define _DEBUG_OFF 0x3FFF
291 #define _DEBUG_ON 0x37FF
292 #define _WRT_ENABLE_OFF 0x3FFF
293 #define _WRT_ENABLE_512 0x3DFF
294 #define _WRT_ENABLE_1024 0x3BFF
295 #define _WRT_ENABLE_1536 0x39FF
296 #define _CPD_ON 0x3EFF
297 #define _CPD_OFF 0x3FFF
298 #define _LVP_ON 0x3FFF
299 #define _LVP_OFF 0x3F7F
300 #define _BODEN_ON 0x3FFF
301 #define _BODEN_OFF 0x3FBF
302 #define _MCLR_ON 0x3FFF
303 #define _MCLR_OFF 0x3FDF
304 #define _PWRTE_OFF 0x3FFF
305 #define _PWRTE_ON 0x3FF7
306 #define _WDT_ON 0x3FFF
307 #define _WDT_OFF 0x3FFB
308 #define _EXTRC_CLKOUT 0x3FFF
309 #define _EXTRC_IO 0x3FFE
310 #define _INTRC_CLKOUT 0x3FFD
311 #define _INTRC_IO 0x3FFC
312 #define _EXTCLK 0x3FEF
313 #define _HS_OSC 0x3FEE
314 #define _XT_OSC 0x3FED
315 #define _LP_OSC 0x3FEC
319 // ----- ADCON0 bits --------------------
322 unsigned char ADON:1;
325 unsigned char CHS0:1;
326 unsigned char CHS1:1;
327 unsigned char CHS2:1;
328 unsigned char ADCS0:1;
329 unsigned char ADCS1:1;
334 unsigned char NOT_DONE:1;
344 unsigned char GO_DONE:1;
352 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
354 #define ADON ADCON0_bits.ADON
355 #define GO ADCON0_bits.GO
356 #define NOT_DONE ADCON0_bits.NOT_DONE
357 #define GO_DONE ADCON0_bits.GO_DONE
358 #define CHS0 ADCON0_bits.CHS0
359 #define CHS1 ADCON0_bits.CHS1
360 #define CHS2 ADCON0_bits.CHS2
361 #define ADCS0 ADCON0_bits.ADCS0
362 #define ADCS1 ADCON0_bits.ADCS1
364 // ----- ADCON1 bits --------------------
367 unsigned char PCFG0:1;
368 unsigned char PCFG1:1;
369 unsigned char PCFG2:1;
370 unsigned char PCFG3:1;
373 unsigned char ADCS2:1;
374 unsigned char ADFM:1;
377 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
379 #define PCFG0 ADCON1_bits.PCFG0
380 #define PCFG1 ADCON1_bits.PCFG1
381 #define PCFG2 ADCON1_bits.PCFG2
382 #define PCFG3 ADCON1_bits.PCFG3
383 #define ADCS2 ADCON1_bits.ADCS2
384 #define ADFM ADCON1_bits.ADFM
386 // ----- CCP1CON bits --------------------
389 unsigned char CCP1M0:1;
390 unsigned char CCP1M1:1;
391 unsigned char CCP1M2:1;
392 unsigned char CCP1M3:1;
393 unsigned char CCP1Y:1;
394 unsigned char CCP1X:1;
399 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
401 #define CCP1M0 CCP1CON_bits.CCP1M0
402 #define CCP1M1 CCP1CON_bits.CCP1M1
403 #define CCP1M2 CCP1CON_bits.CCP1M2
404 #define CCP1M3 CCP1CON_bits.CCP1M3
405 #define CCP1Y CCP1CON_bits.CCP1Y
406 #define CCP1X CCP1CON_bits.CCP1X
408 // ----- EECON1 bits --------------------
413 unsigned char WREN:1;
414 unsigned char WRERR:1;
415 unsigned char FREE:1;
418 unsigned char EEPGD:1;
421 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
423 #define RD EECON1_bits.RD
424 #define WR EECON1_bits.WR
425 #define WREN EECON1_bits.WREN
426 #define WRERR EECON1_bits.WRERR
427 #define FREE EECON1_bits.FREE
428 #define EEPGD EECON1_bits.EEPGD
430 // ----- INTCON bits --------------------
433 unsigned char RBIF:1;
434 unsigned char INTF:1;
435 unsigned char TMR0IF:1;
436 unsigned char RBIE:1;
437 unsigned char INTE:1;
438 unsigned char TMR0IE:1;
439 unsigned char PEIE:1;
443 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
445 #define RBIF INTCON_bits.RBIF
446 #define INTF INTCON_bits.INTF
447 #define TMR0IF INTCON_bits.TMR0IF
448 #define RBIE INTCON_bits.RBIE
449 #define INTE INTCON_bits.INTE
450 #define TMR0IE INTCON_bits.TMR0IE
451 #define PEIE INTCON_bits.PEIE
452 #define GIE INTCON_bits.GIE
454 // ----- OPTION_REG bits --------------------
461 unsigned char T0SE:1;
462 unsigned char T0CS:1;
463 unsigned char INTEDG:1;
464 unsigned char NOT_RBPU:1;
466 } __OPTION_REG_bits_t;
467 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
469 #define PS0 OPTION_REG_bits.PS0
470 #define PS1 OPTION_REG_bits.PS1
471 #define PS2 OPTION_REG_bits.PS2
472 #define PSA OPTION_REG_bits.PSA
473 #define T0SE OPTION_REG_bits.T0SE
474 #define T0CS OPTION_REG_bits.T0CS
475 #define INTEDG OPTION_REG_bits.INTEDG
476 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
478 // ----- OSCCON bits --------------------
483 unsigned char IOFS:1;
485 unsigned char IRCF0:1;
486 unsigned char IRCF1:1;
487 unsigned char IRCF2:1;
491 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
493 #define IOFS OSCCON_bits.IOFS
494 #define IRCF0 OSCCON_bits.IRCF0
495 #define IRCF1 OSCCON_bits.IRCF1
496 #define IRCF2 OSCCON_bits.IRCF2
498 // ----- OSCTUNE bits --------------------
501 unsigned char TUN0:1;
502 unsigned char TUN1:1;
503 unsigned char TUN2:1;
504 unsigned char TUN3:1;
505 unsigned char TUN4:1;
506 unsigned char TUN5:1;
511 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
513 #define TUN0 OSCTUNE_bits.TUN0
514 #define TUN1 OSCTUNE_bits.TUN1
515 #define TUN2 OSCTUNE_bits.TUN2
516 #define TUN3 OSCTUNE_bits.TUN3
517 #define TUN4 OSCTUNE_bits.TUN4
518 #define TUN5 OSCTUNE_bits.TUN5
520 // ----- PCON bits --------------------
523 unsigned char NOT_BO:1;
524 unsigned char NOT_POR:1;
533 unsigned char NOT_BOR:1;
543 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
545 #define NOT_BO PCON_bits.NOT_BO
546 #define NOT_BOR PCON_bits.NOT_BOR
547 #define NOT_POR PCON_bits.NOT_POR
549 // ----- PIE1 bits --------------------
552 unsigned char TMR1IE:1;
553 unsigned char TMR2IE:1;
554 unsigned char CCP1IE:1;
555 unsigned char SSPIE:1;
558 unsigned char ADIE:1;
562 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
564 #define TMR1IE PIE1_bits.TMR1IE
565 #define TMR2IE PIE1_bits.TMR2IE
566 #define CCP1IE PIE1_bits.CCP1IE
567 #define SSPIE PIE1_bits.SSPIE
568 #define ADIE PIE1_bits.ADIE
570 // ----- PIE2 bits --------------------
577 unsigned char EEIE:1;
583 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
585 #define EEIE PIE2_bits.EEIE
587 // ----- PIR1 bits --------------------
590 unsigned char TMR1IF:1;
591 unsigned char TMR2IF:1;
592 unsigned char CCP1IF:1;
593 unsigned char SSPIF:1;
596 unsigned char ADIF:1;
600 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
602 #define TMR1IF PIR1_bits.TMR1IF
603 #define TMR2IF PIR1_bits.TMR2IF
604 #define CCP1IF PIR1_bits.CCP1IF
605 #define SSPIF PIR1_bits.SSPIF
606 #define ADIF PIR1_bits.ADIF
608 // ----- PIR2 bits --------------------
615 unsigned char EEIF:1;
621 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
623 #define EEIF PIR2_bits.EEIF
625 // ----- SSPCON bits --------------------
628 unsigned char SSPM0:1;
629 unsigned char SSPM1:1;
630 unsigned char SSPM2:1;
631 unsigned char SSPM3:1;
633 unsigned char SSPEN:1;
634 unsigned char SSPOV:1;
635 unsigned char WCOL:1;
638 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
640 #define SSPM0 SSPCON_bits.SSPM0
641 #define SSPM1 SSPCON_bits.SSPM1
642 #define SSPM2 SSPCON_bits.SSPM2
643 #define SSPM3 SSPCON_bits.SSPM3
644 #define CKP SSPCON_bits.CKP
645 #define SSPEN SSPCON_bits.SSPEN
646 #define SSPOV SSPCON_bits.SSPOV
647 #define WCOL SSPCON_bits.WCOL
649 // ----- SSPSTAT bits --------------------
664 unsigned char I2C_READ:1;
665 unsigned char I2C_START:1;
666 unsigned char I2C_STOP:1;
667 unsigned char I2C_DATA:1;
674 unsigned char NOT_W:1;
677 unsigned char NOT_A:1;
684 unsigned char NOT_WRITE:1;
687 unsigned char NOT_ADDRESS:1;
704 unsigned char READ_WRITE:1;
707 unsigned char DATA_ADDRESS:1;
712 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
714 #define BF SSPSTAT_bits.BF
715 #define UA SSPSTAT_bits.UA
716 #define R SSPSTAT_bits.R
717 #define I2C_READ SSPSTAT_bits.I2C_READ
718 #define NOT_W SSPSTAT_bits.NOT_W
719 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
720 #define R_W SSPSTAT_bits.R_W
721 #define READ_WRITE SSPSTAT_bits.READ_WRITE
722 #define S SSPSTAT_bits.S
723 #define I2C_START SSPSTAT_bits.I2C_START
724 #define P SSPSTAT_bits.P
725 #define I2C_STOP SSPSTAT_bits.I2C_STOP
726 #define D SSPSTAT_bits.D
727 #define I2C_DATA SSPSTAT_bits.I2C_DATA
728 #define NOT_A SSPSTAT_bits.NOT_A
729 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
730 #define D_A SSPSTAT_bits.D_A
731 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
732 #define CKE SSPSTAT_bits.CKE
733 #define SMP SSPSTAT_bits.SMP
735 // ----- STATUS bits --------------------
741 unsigned char NOT_PD:1;
742 unsigned char NOT_TO:1;
748 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
750 #define C STATUS_bits.C
751 #define DC STATUS_bits.DC
752 #define Z STATUS_bits.Z
753 #define NOT_PD STATUS_bits.NOT_PD
754 #define NOT_TO STATUS_bits.NOT_TO
755 #define RP0 STATUS_bits.RP0
756 #define RP1 STATUS_bits.RP1
757 #define IRP STATUS_bits.IRP
759 // ----- T1CON bits --------------------
762 unsigned char TMR1ON:1;
763 unsigned char TMR1CS:1;
764 unsigned char NOT_T1SYNC:1;
765 unsigned char T1OSCEN:1;
766 unsigned char T1CKPS0:1;
767 unsigned char T1CKPS1:1;
774 unsigned char T1INSYNC:1;
782 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
784 #define TMR1ON T1CON_bits.TMR1ON
785 #define TMR1CS T1CON_bits.TMR1CS
786 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
787 #define T1INSYNC T1CON_bits.T1INSYNC
788 #define T1OSCEN T1CON_bits.T1OSCEN
789 #define T1CKPS0 T1CON_bits.T1CKPS0
790 #define T1CKPS1 T1CON_bits.T1CKPS1
792 // ----- T2CON bits --------------------
795 unsigned char T2CKPS0:1;
796 unsigned char T2CKPS1:1;
797 unsigned char TMR2ON:1;
798 unsigned char TOUTPS0:1;
799 unsigned char TOUTPS1:1;
800 unsigned char TOUTPS2:1;
801 unsigned char TOUTPS3:1;
805 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
807 #define T2CKPS0 T2CON_bits.T2CKPS0
808 #define T2CKPS1 T2CON_bits.T2CKPS1
809 #define TMR2ON T2CON_bits.TMR2ON
810 #define TOUTPS0 T2CON_bits.TOUTPS0
811 #define TOUTPS1 T2CON_bits.TOUTPS1
812 #define TOUTPS2 T2CON_bits.TOUTPS2
813 #define TOUTPS3 T2CON_bits.TOUTPS3