2 // Register Declarations for Microchip 16F818 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRESH_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define PR2_ADDR 0x0092
60 #define SSPADD_ADDR 0x0093
61 #define SSPSTAT_ADDR 0x0094
62 #define ADRESL_ADDR 0x009E
63 #define ADCON1_ADDR 0x009F
64 #define EEDATA_ADDR 0x010C
65 #define EEADR_ADDR 0x010D
66 #define EEDATH_ADDR 0x010E
67 #define EEADRH_ADDR 0x010F
68 #define EECON1_ADDR 0x018C
69 #define EECON2_ADDR 0x018D
72 // Memory organization.
78 // P16F818.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
81 // This header file defines configurations, registers, and other useful bits of
82 // information for the PIC16F818 microcontroller. These names are taken to match
83 // the data sheets as closely as possible.
85 // Note that the processor must be selected before this file is
86 // included. The processor may be selected the following ways:
88 // 1. Command line switch:
89 // C:\ MPASM MYFILE.ASM /PIC16F818
90 // 2. LIST directive in the source file
92 // 3. Processor Type entry in the MPASM full-screen interface
94 //==========================================================================
98 //==========================================================================
102 //1.00 06/15/02 Initial Release
103 //1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS
105 //==========================================================================
109 //==========================================================================
112 // MESSG "Processor-header file mismatch. Verify selected processor."
115 //==========================================================================
117 // Register Definitions
119 //==========================================================================
124 //----- Register Files------------------------------------------------------
126 extern __data __at (INDF_ADDR) volatile char INDF;
127 extern __sfr __at (TMR0_ADDR) TMR0;
128 extern __data __at (PCL_ADDR) volatile char PCL;
129 extern __sfr __at (STATUS_ADDR) STATUS;
130 extern __sfr __at (FSR_ADDR) FSR;
131 extern __sfr __at (PORTA_ADDR) PORTA;
132 extern __sfr __at (PORTB_ADDR) PORTB;
133 extern __sfr __at (PCLATH_ADDR) PCLATH;
134 extern __sfr __at (INTCON_ADDR) INTCON;
135 extern __sfr __at (PIR1_ADDR) PIR1;
136 extern __sfr __at (PIR2_ADDR) PIR2;
137 extern __sfr __at (TMR1L_ADDR) TMR1L;
138 extern __sfr __at (TMR1H_ADDR) TMR1H;
139 extern __sfr __at (T1CON_ADDR) T1CON;
140 extern __sfr __at (TMR2_ADDR) TMR2;
141 extern __sfr __at (T2CON_ADDR) T2CON;
142 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
143 extern __sfr __at (SSPCON_ADDR) SSPCON;
144 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
145 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
146 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
147 extern __sfr __at (ADRESH_ADDR) ADRESH;
148 extern __sfr __at (ADCON0_ADDR) ADCON0;
150 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
151 extern __sfr __at (TRISA_ADDR) TRISA;
152 extern __sfr __at (TRISB_ADDR) TRISB;
153 extern __sfr __at (PIE1_ADDR) PIE1;
154 extern __sfr __at (PIE2_ADDR) PIE2;
155 extern __sfr __at (PCON_ADDR) PCON;
156 extern __sfr __at (OSCCON_ADDR) OSCCON;
157 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
158 extern __sfr __at (PR2_ADDR) PR2;
159 extern __sfr __at (SSPADD_ADDR) SSPADD;
160 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
161 extern __sfr __at (ADRESL_ADDR) ADRESL;
162 extern __sfr __at (ADCON1_ADDR) ADCON1;
164 extern __sfr __at (EEDATA_ADDR) EEDATA;
165 extern __sfr __at (EEADR_ADDR) EEADR;
166 extern __sfr __at (EEDATH_ADDR) EEDATH;
167 extern __sfr __at (EEADRH_ADDR) EEADRH;
169 extern __sfr __at (EECON1_ADDR) EECON1;
170 extern __sfr __at (EECON2_ADDR) EECON2;
172 //----- STATUS Bits --------------------------------------------------------
175 //----- INTCON Bits --------------------------------------------------------
178 //----- PIR1 Bits ----------------------------------------------------------
181 //----- PIR2 Bits ----------------------------------------------------------
184 //----- T1CON Bits ---------------------------------------------------------
187 //----- T2CON Bits ---------------------------------------------------------
190 //----- SSPCON Bits --------------------------------------------------------
193 //----- CCP1CON Bits -------------------------------------------------------
196 //----- ADCON0 Bits --------------------------------------------------------
199 //----- OPTION Bits -----------------------------------------------------
202 //----- PIE1 Bits ----------------------------------------------------------
205 //----- PIE2 Bits ----------------------------------------------------------
208 //----- PCON Bits ----------------------------------------------------------
211 //----- OSCCON Bits -------------------------------------------------------
214 //----- OSCTUNE Bits -------------------------------------------------------
217 //----- SSPSTAT Bits -------------------------------------------------------
220 //----- ADCON1 Bits --------------------------------------------------------
223 //----- EECON1 Bits --------------------------------------------------------
226 //==========================================================================
230 //==========================================================================
233 // __BADRAM H'07'-H'09', H'18'-H'1D'
234 // __BADRAM H'87'-H'89', H'91', H'95'-H'9D'
235 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
236 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
238 //==========================================================================
240 // Configuration Bits
242 //==========================================================================
244 #define _CP_ALL 0x1FFF
245 #define _CP_OFF 0x3FFF
246 #define _CCP1_RB2 0x3FFF
247 #define _CCP1_RB3 0x2FFF
248 #define _DEBUG_OFF 0x3FFF
249 #define _DEBUG_ON 0x37FF
250 #define _WRT_ENABLE_OFF 0x3FFF
251 #define _WRT_ENABLE_512 0x3DFF
252 #define _WRT_ENABLE_1024 0x3BFF
253 #define _CPD_ON 0x3EFF
254 #define _CPD_OFF 0x3FFF
255 #define _LVP_ON 0x3FFF
256 #define _LVP_OFF 0x3F7F
257 #define _BODEN_ON 0x3FFF
258 #define _BODEN_OFF 0x3FBF
259 #define _MCLR_ON 0x3FFF
260 #define _MCLR_OFF 0x3FDF
261 #define _PWRTE_OFF 0x3FFF
262 #define _PWRTE_ON 0x3FF7
263 #define _WDT_ON 0x3FFF
264 #define _WDT_OFF 0x3FFB
265 #define _EXTRC_CLKOUT 0x3FFF
266 #define _EXTRC_IO 0x3FFE
267 #define _INTRC_CLKOUT 0x3FFD
268 #define _INTRC_IO 0x3FFC
269 #define _EXTCLK 0x3FEF
270 #define _HS_OSC 0x3FEE
271 #define _XT_OSC 0x3FED
272 #define _LP_OSC 0x3FEC
276 // ----- ADCON0 bits --------------------
279 unsigned char ADON:1;
282 unsigned char CHS0:1;
283 unsigned char CHS1:1;
284 unsigned char CHS2:1;
285 unsigned char ADCS0:1;
286 unsigned char ADCS1:1;
291 unsigned char NOT_DONE:1;
301 unsigned char GO_DONE:1;
309 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
311 #define ADON ADCON0_bits.ADON
312 #define GO ADCON0_bits.GO
313 #define NOT_DONE ADCON0_bits.NOT_DONE
314 #define GO_DONE ADCON0_bits.GO_DONE
315 #define CHS0 ADCON0_bits.CHS0
316 #define CHS1 ADCON0_bits.CHS1
317 #define CHS2 ADCON0_bits.CHS2
318 #define ADCS0 ADCON0_bits.ADCS0
319 #define ADCS1 ADCON0_bits.ADCS1
321 // ----- ADCON1 bits --------------------
324 unsigned char PCFG0:1;
325 unsigned char PCFG1:1;
326 unsigned char PCFG2:1;
327 unsigned char PCFG3:1;
330 unsigned char ADCS2:1;
331 unsigned char ADFM:1;
334 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
336 #define PCFG0 ADCON1_bits.PCFG0
337 #define PCFG1 ADCON1_bits.PCFG1
338 #define PCFG2 ADCON1_bits.PCFG2
339 #define PCFG3 ADCON1_bits.PCFG3
340 #define ADCS2 ADCON1_bits.ADCS2
341 #define ADFM ADCON1_bits.ADFM
343 // ----- CCP1CON bits --------------------
346 unsigned char CCP1M0:1;
347 unsigned char CCP1M1:1;
348 unsigned char CCP1M2:1;
349 unsigned char CCP1M3:1;
350 unsigned char CCP1Y:1;
351 unsigned char CCP1X:1;
356 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
358 #define CCP1M0 CCP1CON_bits.CCP1M0
359 #define CCP1M1 CCP1CON_bits.CCP1M1
360 #define CCP1M2 CCP1CON_bits.CCP1M2
361 #define CCP1M3 CCP1CON_bits.CCP1M3
362 #define CCP1Y CCP1CON_bits.CCP1Y
363 #define CCP1X CCP1CON_bits.CCP1X
365 // ----- EECON1 bits --------------------
370 unsigned char WREN:1;
371 unsigned char WRERR:1;
372 unsigned char FREE:1;
375 unsigned char EEPGD:1;
378 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
380 #define RD EECON1_bits.RD
381 #define WR EECON1_bits.WR
382 #define WREN EECON1_bits.WREN
383 #define WRERR EECON1_bits.WRERR
384 #define FREE EECON1_bits.FREE
385 #define EEPGD EECON1_bits.EEPGD
387 // ----- INTCON bits --------------------
390 unsigned char RBIF:1;
391 unsigned char INTF:1;
392 unsigned char TMR0IF:1;
393 unsigned char RBIE:1;
394 unsigned char INTE:1;
395 unsigned char TMR0IE:1;
396 unsigned char PEIE:1;
400 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
402 #define RBIF INTCON_bits.RBIF
403 #define INTF INTCON_bits.INTF
404 #define TMR0IF INTCON_bits.TMR0IF
405 #define RBIE INTCON_bits.RBIE
406 #define INTE INTCON_bits.INTE
407 #define TMR0IE INTCON_bits.TMR0IE
408 #define PEIE INTCON_bits.PEIE
409 #define GIE INTCON_bits.GIE
411 // ----- OPTION_REG bits --------------------
418 unsigned char T0SE:1;
419 unsigned char T0CS:1;
420 unsigned char INTEDG:1;
421 unsigned char NOT_RBPU:1;
423 } __OPTION_REG_bits_t;
424 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
426 #define PS0 OPTION_REG_bits.PS0
427 #define PS1 OPTION_REG_bits.PS1
428 #define PS2 OPTION_REG_bits.PS2
429 #define PSA OPTION_REG_bits.PSA
430 #define T0SE OPTION_REG_bits.T0SE
431 #define T0CS OPTION_REG_bits.T0CS
432 #define INTEDG OPTION_REG_bits.INTEDG
433 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
435 // ----- OSCCON bits --------------------
440 unsigned char IOFS:1;
442 unsigned char IRCF0:1;
443 unsigned char IRCF1:1;
444 unsigned char IRCF2:1;
448 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
450 #define IOFS OSCCON_bits.IOFS
451 #define IRCF0 OSCCON_bits.IRCF0
452 #define IRCF1 OSCCON_bits.IRCF1
453 #define IRCF2 OSCCON_bits.IRCF2
455 // ----- OSCTUNE bits --------------------
458 unsigned char TUN0:1;
459 unsigned char TUN1:1;
460 unsigned char TUN2:1;
461 unsigned char TUN3:1;
462 unsigned char TUN4:1;
463 unsigned char TUN5:1;
468 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
470 #define TUN0 OSCTUNE_bits.TUN0
471 #define TUN1 OSCTUNE_bits.TUN1
472 #define TUN2 OSCTUNE_bits.TUN2
473 #define TUN3 OSCTUNE_bits.TUN3
474 #define TUN4 OSCTUNE_bits.TUN4
475 #define TUN5 OSCTUNE_bits.TUN5
477 // ----- PCON bits --------------------
480 unsigned char NOT_BO:1;
481 unsigned char NOT_POR:1;
490 unsigned char NOT_BOR:1;
500 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
502 #define NOT_BO PCON_bits.NOT_BO
503 #define NOT_BOR PCON_bits.NOT_BOR
504 #define NOT_POR PCON_bits.NOT_POR
506 // ----- PIE1 bits --------------------
509 unsigned char TMR1IE:1;
510 unsigned char TMR2IE:1;
511 unsigned char CCP1IE:1;
512 unsigned char SSPIE:1;
515 unsigned char ADIE:1;
519 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
521 #define TMR1IE PIE1_bits.TMR1IE
522 #define TMR2IE PIE1_bits.TMR2IE
523 #define CCP1IE PIE1_bits.CCP1IE
524 #define SSPIE PIE1_bits.SSPIE
525 #define ADIE PIE1_bits.ADIE
527 // ----- PIE2 bits --------------------
534 unsigned char EEIE:1;
540 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
542 #define EEIE PIE2_bits.EEIE
544 // ----- PIR1 bits --------------------
547 unsigned char TMR1IF:1;
548 unsigned char TMR2IF:1;
549 unsigned char CCP1IF:1;
550 unsigned char SSPIF:1;
553 unsigned char ADIF:1;
557 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
559 #define TMR1IF PIR1_bits.TMR1IF
560 #define TMR2IF PIR1_bits.TMR2IF
561 #define CCP1IF PIR1_bits.CCP1IF
562 #define SSPIF PIR1_bits.SSPIF
563 #define ADIF PIR1_bits.ADIF
565 // ----- PIR2 bits --------------------
572 unsigned char EEIF:1;
578 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
580 #define EEIF PIR2_bits.EEIF
582 // ----- SSPCON bits --------------------
585 unsigned char SSPM0:1;
586 unsigned char SSPM1:1;
587 unsigned char SSPM2:1;
588 unsigned char SSPM3:1;
590 unsigned char SSPEN:1;
591 unsigned char SSPOV:1;
592 unsigned char WCOL:1;
595 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
597 #define SSPM0 SSPCON_bits.SSPM0
598 #define SSPM1 SSPCON_bits.SSPM1
599 #define SSPM2 SSPCON_bits.SSPM2
600 #define SSPM3 SSPCON_bits.SSPM3
601 #define CKP SSPCON_bits.CKP
602 #define SSPEN SSPCON_bits.SSPEN
603 #define SSPOV SSPCON_bits.SSPOV
604 #define WCOL SSPCON_bits.WCOL
606 // ----- SSPSTAT bits --------------------
621 unsigned char I2C_READ:1;
622 unsigned char I2C_START:1;
623 unsigned char I2C_STOP:1;
624 unsigned char I2C_DATA:1;
631 unsigned char NOT_W:1;
634 unsigned char NOT_A:1;
641 unsigned char NOT_WRITE:1;
644 unsigned char NOT_ADDRESS:1;
661 unsigned char READ_WRITE:1;
664 unsigned char DATA_ADDRESS:1;
669 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
671 #define BF SSPSTAT_bits.BF
672 #define UA SSPSTAT_bits.UA
673 #define R SSPSTAT_bits.R
674 #define I2C_READ SSPSTAT_bits.I2C_READ
675 #define NOT_W SSPSTAT_bits.NOT_W
676 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
677 #define R_W SSPSTAT_bits.R_W
678 #define READ_WRITE SSPSTAT_bits.READ_WRITE
679 #define S SSPSTAT_bits.S
680 #define I2C_START SSPSTAT_bits.I2C_START
681 #define P SSPSTAT_bits.P
682 #define I2C_STOP SSPSTAT_bits.I2C_STOP
683 #define D SSPSTAT_bits.D
684 #define I2C_DATA SSPSTAT_bits.I2C_DATA
685 #define NOT_A SSPSTAT_bits.NOT_A
686 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
687 #define D_A SSPSTAT_bits.D_A
688 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
689 #define CKE SSPSTAT_bits.CKE
690 #define SMP SSPSTAT_bits.SMP
692 // ----- STATUS bits --------------------
698 unsigned char NOT_PD:1;
699 unsigned char NOT_TO:1;
705 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
707 #define C STATUS_bits.C
708 #define DC STATUS_bits.DC
709 #define Z STATUS_bits.Z
710 #define NOT_PD STATUS_bits.NOT_PD
711 #define NOT_TO STATUS_bits.NOT_TO
712 #define RP0 STATUS_bits.RP0
713 #define RP1 STATUS_bits.RP1
714 #define IRP STATUS_bits.IRP
716 // ----- T1CON bits --------------------
719 unsigned char TMR1ON:1;
720 unsigned char TMR1CS:1;
721 unsigned char NOT_T1SYNC:1;
722 unsigned char T1OSCEN:1;
723 unsigned char T1CKPS0:1;
724 unsigned char T1CKPS1:1;
731 unsigned char T1INSYNC:1;
739 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
741 #define TMR1ON T1CON_bits.TMR1ON
742 #define TMR1CS T1CON_bits.TMR1CS
743 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
744 #define T1INSYNC T1CON_bits.T1INSYNC
745 #define T1OSCEN T1CON_bits.T1OSCEN
746 #define T1CKPS0 T1CON_bits.T1CKPS0
747 #define T1CKPS1 T1CON_bits.T1CKPS1
749 // ----- T2CON bits --------------------
752 unsigned char T2CKPS0:1;
753 unsigned char T2CKPS1:1;
754 unsigned char TMR2ON:1;
755 unsigned char TOUTPS0:1;
756 unsigned char TOUTPS1:1;
757 unsigned char TOUTPS2:1;
758 unsigned char TOUTPS3:1;
762 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
764 #define T2CKPS0 T2CON_bits.T2CKPS0
765 #define T2CKPS1 T2CON_bits.T2CKPS1
766 #define TMR2ON T2CON_bits.TMR2ON
767 #define TOUTPS0 T2CON_bits.TOUTPS0
768 #define TOUTPS1 T2CON_bits.TOUTPS1
769 #define TOUTPS2 T2CON_bits.TOUTPS2
770 #define TOUTPS3 T2CON_bits.TOUTPS3