2 // Register Declarations for Microchip 16F785 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0013
45 #define CCPR1H_ADDR 0x0014
46 #define CCP1CON_ADDR 0x0015
47 #define WDTCON_ADDR 0x0018
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PCON_ADDR 0x008E
56 #define OSCCON_ADDR 0x008F
57 #define OSCTUNE_ADDR 0x0090
58 #define ANSEL_ADDR 0x0091
59 #define ANSEL0_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define ANSEL1_ADDR 0x0093
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define REFCON_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define PWMCON1_ADDR 0x0110
76 #define PWMCON0_ADDR 0x0111
77 #define PWMCLK_ADDR 0x0112
78 #define PWMPH1_ADDR 0x0113
79 #define PWMPH2_ADDR 0x0114
80 #define CM1CON0_ADDR 0x0119
81 #define CM2CON0_ADDR 0x011A
82 #define CM2CON1_ADDR 0x011B
83 #define OPA1CON_ADDR 0x011C
84 #define OPA2CON_ADDR 0x011D
87 // Memory organization.
93 // P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F785 microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F785
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
114 //1.00 03/26/04 Original
115 //1.10 07/12/04 Updated for changes to REFCON and VRCON
116 //1.20 08/26/04 Updated for changes from BOD to BOR
117 //1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON
118 //1.40 10/25/04 Added WPUA3 bit to WPUA register
119 // Deleted OVRLP bit from PWMCON1 register
120 //==========================================================================
124 //==========================================================================
127 // MESSG "Processor-header file mismatch. Verify selected processor."
130 //==========================================================================
132 // Register Definitions
134 //==========================================================================
139 //----- Register Files------------------------------------------------------
141 extern __data __at (INDF_ADDR) volatile char INDF;
142 extern __sfr __at (TMR0_ADDR) TMR0;
143 extern __data __at (PCL_ADDR) volatile char PCL;
144 extern __sfr __at (STATUS_ADDR) STATUS;
145 extern __sfr __at (FSR_ADDR) FSR;
146 extern __sfr __at (PORTA_ADDR) PORTA;
147 extern __sfr __at (PORTB_ADDR) PORTB;
148 extern __sfr __at (PORTC_ADDR) PORTC;
150 extern __sfr __at (PCLATH_ADDR) PCLATH;
151 extern __sfr __at (INTCON_ADDR) INTCON;
152 extern __sfr __at (PIR1_ADDR) PIR1;
154 extern __sfr __at (TMR1L_ADDR) TMR1L;
155 extern __sfr __at (TMR1H_ADDR) TMR1H;
156 extern __sfr __at (T1CON_ADDR) T1CON;
157 extern __sfr __at (TMR2_ADDR) TMR2;
158 extern __sfr __at (T2CON_ADDR) T2CON;
159 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
160 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
161 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
163 extern __sfr __at (WDTCON_ADDR) WDTCON;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
171 extern __sfr __at (TRISA_ADDR) TRISA;
172 extern __sfr __at (TRISB_ADDR) TRISB;
173 extern __sfr __at (TRISC_ADDR) TRISC;
175 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (OSCCON_ADDR) OSCCON;
179 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
180 extern __sfr __at (ANSEL_ADDR) ANSEL;
181 extern __sfr __at (ANSEL0_ADDR) ANSEL0;
182 extern __sfr __at (PR2_ADDR) PR2;
183 extern __sfr __at (ANSEL1_ADDR) ANSEL1;
185 extern __sfr __at (WPU_ADDR) WPU;
186 extern __sfr __at (WPUA_ADDR) WPUA;
187 extern __sfr __at (IOC_ADDR) IOC;
188 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (REFCON_ADDR) REFCON;
191 extern __sfr __at (VRCON_ADDR) VRCON;
192 extern __sfr __at (EEDAT_ADDR) EEDAT;
193 extern __sfr __at (EEDATA_ADDR) EEDATA;
194 extern __sfr __at (EEADR_ADDR) EEADR;
195 extern __sfr __at (EECON1_ADDR) EECON1;
196 extern __sfr __at (EECON2_ADDR) EECON2;
197 extern __sfr __at (ADRESL_ADDR) ADRESL;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
201 extern __sfr __at (PWMCON1_ADDR) PWMCON1;
202 extern __sfr __at (PWMCON0_ADDR) PWMCON0;
203 extern __sfr __at (PWMCLK_ADDR) PWMCLK;
204 extern __sfr __at (PWMPH1_ADDR) PWMPH1;
205 extern __sfr __at (PWMPH2_ADDR) PWMPH2;
207 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
208 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
209 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
210 extern __sfr __at (OPA1CON_ADDR) OPA1CON;
211 extern __sfr __at (OPA2CON_ADDR) OPA2CON;
213 //----- STATUS Bits --------------------------------------------------------
216 //----- INTCON Bits --------------------------------------------------------
219 //----- PIR1 Bits ----------------------------------------------------------
222 //----- T1CON Bits ---------------------------------------------------------
225 //----- T2CON Bits ---------------------------------------------------------
228 //----- CCP1CON Bits -------------------------------------------------------
231 //----- WDTCON Bits --------------------------------------------------------
234 //----- ADCON0 Bits --------------------------------------------------------
237 //----- OPTION Bits --------------------------------------------------------
240 //----- PIE1 Bits ----------------------------------------------------------
243 //----- PCON Bits ----------------------------------------------------------
246 //----- OSCCON Bits --------------------------------------------------------
249 //----- OSCTUNE Bits -------------------------------------------------------
252 //----- ANSEL or ANSEL0 ----------------------------------------------------
255 //----- ANSEL1 -------------------------------------------------------------
258 //----- WPUA --------------------------------------------------------------
261 //----- IOC --------------------------------------------------------------
264 //----- IOCA --------------------------------------------------------------
267 //----- REFCON -------------------------------------------------------------
270 //----- VRCON Bits ---------------------------------------------------------
273 //----- EECON1 -------------------------------------------------------------
276 //----- ADCON1 -------------------------------------------------------------
279 //----- PWMCON1 -------------------------------------------------------------
282 //----- PWMCON0 -------------------------------------------------------------
285 //----- PWMCLK -------------------------------------------------------------
288 //----- PWMPH1 & PWMPH2 ----------------------------------------------------
291 //----- CM1CON0 -------------------------------------------------------------
294 //----- CM2CON0 -------------------------------------------------------------
297 //----- CM2CON1 -------------------------------------------------------------
300 //----- OPA1CON & OPA2CON ---------------------------------------------------
303 //==========================================================================
307 //==========================================================================
310 // __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D'
311 // __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF'
312 // __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F'
313 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
315 //==========================================================================
317 // Configuration Bits
319 //==========================================================================
321 #define _FCMEN_ON 0x3FFF
322 #define _FCMEN_OFF 0x37FF
323 #define _IESO_ON 0x3FFF
324 #define _IESO_OFF 0x3BFF
325 #define _BOD_ON 0x3FFF
326 #define _BOD_NSLEEP 0x3EFF
327 #define _BOD_SBODEN 0x3DFF
328 #define _BOD_OFF 0x3CFF
329 #define _BOR_ON 0x3FFF
330 #define _BOR_NSLEEP 0x3EFF
331 #define _BOR_SBOREN 0x3DFF
332 #define _BOR_OFF 0x3CFF
333 #define _CPD_ON 0x3F7F
334 #define _CPD_OFF 0x3FFF
335 #define _CP_ON 0x3FBF
336 #define _CP_OFF 0x3FFF
337 #define _MCLRE_ON 0x3FFF
338 #define _MCLRE_OFF 0x3FDF
339 #define _PWRTE_OFF 0x3FFF
340 #define _PWRTE_ON 0x3FEF
341 #define _WDT_ON 0x3FFF
342 #define _WDT_OFF 0x3FF7
343 #define _LP_OSC 0x3FF8
344 #define _XT_OSC 0x3FF9
345 #define _HS_OSC 0x3FFA
346 #define _EC_OSC 0x3FFB
347 #define _INTRC_OSC_NOCLKOUT 0x3FFC
348 #define _INTRC_OSC_CLKOUT 0x3FFD
349 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
350 #define _EXTRC_OSC_CLKOUT 0x3FFF
351 #define _INTOSCIO 0x3FFC
352 #define _INTOSC 0x3FFD
353 #define _EXTRCIO 0x3FFE
354 #define _EXTRC 0x3FFF
358 // ----- ADCON0 bits --------------------
361 unsigned char ADON:1;
363 unsigned char CHS0:1;
364 unsigned char CHS1:1;
365 unsigned char CHS2:1;
366 unsigned char CHS3:1;
367 unsigned char VCFG:1;
368 unsigned char ADFM:1;
372 unsigned char NOT_DONE:1;
382 unsigned char GO_DONE:1;
391 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
393 #define ADON ADCON0_bits.ADON
394 #define GO ADCON0_bits.GO
395 #define NOT_DONE ADCON0_bits.NOT_DONE
396 #define GO_DONE ADCON0_bits.GO_DONE
397 #define CHS0 ADCON0_bits.CHS0
398 #define CHS1 ADCON0_bits.CHS1
399 #define CHS2 ADCON0_bits.CHS2
400 #define CHS3 ADCON0_bits.CHS3
401 #define VCFG ADCON0_bits.VCFG
402 #define ADFM ADCON0_bits.ADFM
404 // ----- CCP1CON bits --------------------
407 unsigned char CCP1M0:1;
408 unsigned char CCP1M1:1;
409 unsigned char CCP1M2:1;
410 unsigned char CCP1M3:1;
411 unsigned char DC1B0:1;
412 unsigned char DC1B1:1;
417 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
419 #define CCP1M0 CCP1CON_bits.CCP1M0
420 #define CCP1M1 CCP1CON_bits.CCP1M1
421 #define CCP1M2 CCP1CON_bits.CCP1M2
422 #define CCP1M3 CCP1CON_bits.CCP1M3
423 #define DC1B0 CCP1CON_bits.DC1B0
424 #define DC1B1 CCP1CON_bits.DC1B1
426 // ----- INTCON bits --------------------
429 unsigned char RAIF:1;
430 unsigned char INTF:1;
431 unsigned char T0IF:1;
432 unsigned char RAIE:1;
433 unsigned char INTE:1;
434 unsigned char T0IE:1;
435 unsigned char PEIE:1;
439 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
441 #define RAIF INTCON_bits.RAIF
442 #define INTF INTCON_bits.INTF
443 #define T0IF INTCON_bits.T0IF
444 #define RAIE INTCON_bits.RAIE
445 #define INTE INTCON_bits.INTE
446 #define T0IE INTCON_bits.T0IE
447 #define PEIE INTCON_bits.PEIE
448 #define GIE INTCON_bits.GIE
450 // ----- OPTION_REG bits --------------------
457 unsigned char T0SE:1;
458 unsigned char T0CS:1;
459 unsigned char INTEDG:1;
460 unsigned char NOT_RAPU:1;
462 } __OPTION_REG_bits_t;
463 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
465 #define PS0 OPTION_REG_bits.PS0
466 #define PS1 OPTION_REG_bits.PS1
467 #define PS2 OPTION_REG_bits.PS2
468 #define PSA OPTION_REG_bits.PSA
469 #define T0SE OPTION_REG_bits.T0SE
470 #define T0CS OPTION_REG_bits.T0CS
471 #define INTEDG OPTION_REG_bits.INTEDG
472 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
474 // ----- OSCCON bits --------------------
480 unsigned char OSTS:1;
481 unsigned char IRCF0:1;
482 unsigned char IRCF1:1;
483 unsigned char IRCF2:1;
487 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
489 #define SCS OSCCON_bits.SCS
490 #define LTS OSCCON_bits.LTS
491 #define HTS OSCCON_bits.HTS
492 #define OSTS OSCCON_bits.OSTS
493 #define IRCF0 OSCCON_bits.IRCF0
494 #define IRCF1 OSCCON_bits.IRCF1
495 #define IRCF2 OSCCON_bits.IRCF2
497 // ----- OSCTUNE bits --------------------
500 unsigned char TUN0:1;
501 unsigned char TUN1:1;
502 unsigned char TUN2:1;
503 unsigned char TUN3:1;
504 unsigned char TUN4:1;
505 unsigned char ANS5:1;
506 unsigned char ANS6:1;
507 unsigned char ANS7:1;
510 unsigned char ANS0:1;
511 unsigned char ANS1:1;
512 unsigned char ANS2:1;
513 unsigned char ANS3:1;
514 unsigned char ANS4:1;
515 unsigned char WPUA5:1;
520 unsigned char ANS8:1;
521 unsigned char ANS9:1;
522 unsigned char ANS10:1;
523 unsigned char ANS11:1;
524 unsigned char WPUA4:1;
525 unsigned char IOC5:1;
530 unsigned char WPUA0:1;
531 unsigned char WPUA1:1;
532 unsigned char WPUA2:1;
533 unsigned char WPUA3:1;
534 unsigned char IOC4:1;
535 unsigned char IOCA5:1;
540 unsigned char IOC0:1;
541 unsigned char IOC1:1;
542 unsigned char IOC2:1;
543 unsigned char IOC3:1;
544 unsigned char IOCA4:1;
545 unsigned char BGST:1;
550 unsigned char IOCA0:1;
551 unsigned char IOCA1:1;
552 unsigned char IOCA2:1;
553 unsigned char IOCA3:1;
554 unsigned char VRBB:1;
561 unsigned char CVROE:1;
562 unsigned char VROE:1;
563 unsigned char VREN:1;
570 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
572 #define TUN0 OSCTUNE_bits.TUN0
573 #define ANS0 OSCTUNE_bits.ANS0
574 #define ANS8 OSCTUNE_bits.ANS8
575 #define WPUA0 OSCTUNE_bits.WPUA0
576 #define IOC0 OSCTUNE_bits.IOC0
577 #define IOCA0 OSCTUNE_bits.IOCA0
578 #define TUN1 OSCTUNE_bits.TUN1
579 #define ANS1 OSCTUNE_bits.ANS1
580 #define ANS9 OSCTUNE_bits.ANS9
581 #define WPUA1 OSCTUNE_bits.WPUA1
582 #define IOC1 OSCTUNE_bits.IOC1
583 #define IOCA1 OSCTUNE_bits.IOCA1
584 #define CVROE OSCTUNE_bits.CVROE
585 #define TUN2 OSCTUNE_bits.TUN2
586 #define ANS2 OSCTUNE_bits.ANS2
587 #define ANS10 OSCTUNE_bits.ANS10
588 #define WPUA2 OSCTUNE_bits.WPUA2
589 #define IOC2 OSCTUNE_bits.IOC2
590 #define IOCA2 OSCTUNE_bits.IOCA2
591 #define VROE OSCTUNE_bits.VROE
592 #define TUN3 OSCTUNE_bits.TUN3
593 #define ANS3 OSCTUNE_bits.ANS3
594 #define ANS11 OSCTUNE_bits.ANS11
595 #define WPUA3 OSCTUNE_bits.WPUA3
596 #define IOC3 OSCTUNE_bits.IOC3
597 #define IOCA3 OSCTUNE_bits.IOCA3
598 #define VREN OSCTUNE_bits.VREN
599 #define TUN4 OSCTUNE_bits.TUN4
600 #define ANS4 OSCTUNE_bits.ANS4
601 #define WPUA4 OSCTUNE_bits.WPUA4
602 #define IOC4 OSCTUNE_bits.IOC4
603 #define IOCA4 OSCTUNE_bits.IOCA4
604 #define VRBB OSCTUNE_bits.VRBB
605 #define ANS5 OSCTUNE_bits.ANS5
606 #define WPUA5 OSCTUNE_bits.WPUA5
607 #define IOC5 OSCTUNE_bits.IOC5
608 #define IOCA5 OSCTUNE_bits.IOCA5
609 #define BGST OSCTUNE_bits.BGST
610 #define ANS6 OSCTUNE_bits.ANS6
611 #define ANS7 OSCTUNE_bits.ANS7
613 // ----- PCON bits --------------------
616 unsigned char NOT_BOD:1;
617 unsigned char NOT_POR:1;
620 unsigned char SBODEN:1;
626 unsigned char NOT_BOR:1;
630 unsigned char SBOREN:1;
636 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
638 #define NOT_BOD PCON_bits.NOT_BOD
639 #define NOT_BOR PCON_bits.NOT_BOR
640 #define NOT_POR PCON_bits.NOT_POR
641 #define SBODEN PCON_bits.SBODEN
642 #define SBOREN PCON_bits.SBOREN
644 // ----- PIE1 bits --------------------
647 unsigned char T1IE:1;
648 unsigned char T2IE:1;
649 unsigned char OSFIE:1;
650 unsigned char C1IE:1;
651 unsigned char C2IE:1;
652 unsigned char CCP1IE:1;
653 unsigned char ADIE:1;
654 unsigned char EEIE:1;
657 unsigned char TMR1IE:1;
658 unsigned char TMR2IE:1;
667 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
669 #define T1IE PIE1_bits.T1IE
670 #define TMR1IE PIE1_bits.TMR1IE
671 #define T2IE PIE1_bits.T2IE
672 #define TMR2IE PIE1_bits.TMR2IE
673 #define OSFIE PIE1_bits.OSFIE
674 #define C1IE PIE1_bits.C1IE
675 #define C2IE PIE1_bits.C2IE
676 #define CCP1IE PIE1_bits.CCP1IE
677 #define ADIE PIE1_bits.ADIE
678 #define EEIE PIE1_bits.EEIE
680 // ----- PIR1 bits --------------------
683 unsigned char T1IF:1;
684 unsigned char T2IF:1;
685 unsigned char OSFIF:1;
686 unsigned char C1IF:1;
687 unsigned char C2IF:1;
688 unsigned char CCP1IF:1;
689 unsigned char ADIF:1;
690 unsigned char EEIF:1;
693 unsigned char TMR1IF:1;
694 unsigned char TMR2IF:1;
703 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
705 #define T1IF PIR1_bits.T1IF
706 #define TMR1IF PIR1_bits.TMR1IF
707 #define T2IF PIR1_bits.T2IF
708 #define TMR2IF PIR1_bits.TMR2IF
709 #define OSFIF PIR1_bits.OSFIF
710 #define C1IF PIR1_bits.C1IF
711 #define C2IF PIR1_bits.C2IF
712 #define CCP1IF PIR1_bits.CCP1IF
713 #define ADIF PIR1_bits.ADIF
714 #define EEIF PIR1_bits.EEIF
716 // ----- STATUS bits --------------------
722 unsigned char NOT_PD:1;
723 unsigned char NOT_TO:1;
729 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
731 #define C STATUS_bits.C
732 #define DC STATUS_bits.DC
733 #define Z STATUS_bits.Z
734 #define NOT_PD STATUS_bits.NOT_PD
735 #define NOT_TO STATUS_bits.NOT_TO
736 #define RP0 STATUS_bits.RP0
737 #define RP1 STATUS_bits.RP1
738 #define IRP STATUS_bits.IRP
740 // ----- T1CON bits --------------------
743 unsigned char TMR1ON:1;
744 unsigned char TMR1CS:1;
745 unsigned char NOT_T1SYNC:1;
746 unsigned char T1OSCEN:1;
747 unsigned char T1CKPS0:1;
748 unsigned char T1CKPS1:1;
749 unsigned char TMR1GE:1;
750 unsigned char T1GINV:1;
759 unsigned char T1GE:1;
763 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
765 #define TMR1ON T1CON_bits.TMR1ON
766 #define TMR1CS T1CON_bits.TMR1CS
767 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
768 #define T1OSCEN T1CON_bits.T1OSCEN
769 #define T1CKPS0 T1CON_bits.T1CKPS0
770 #define T1CKPS1 T1CON_bits.T1CKPS1
771 #define TMR1GE T1CON_bits.TMR1GE
772 #define T1GE T1CON_bits.T1GE
773 #define T1GINV T1CON_bits.T1GINV
775 // ----- T2CON bits --------------------
778 unsigned char T2CKPS0:1;
779 unsigned char T2CKPS1:1;
780 unsigned char TMR2ON:1;
781 unsigned char TOUTPS0:1;
782 unsigned char TOUTPS1:1;
783 unsigned char TOUTPS2:1;
784 unsigned char TOUTPS3:1;
788 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
790 #define T2CKPS0 T2CON_bits.T2CKPS0
791 #define T2CKPS1 T2CON_bits.T2CKPS1
792 #define TMR2ON T2CON_bits.TMR2ON
793 #define TOUTPS0 T2CON_bits.TOUTPS0
794 #define TOUTPS1 T2CON_bits.TOUTPS1
795 #define TOUTPS2 T2CON_bits.TOUTPS2
796 #define TOUTPS3 T2CON_bits.TOUTPS3
798 // ----- VRCON bits --------------------
805 unsigned char ADCS0:1;
807 unsigned char C2VREN:1;
808 unsigned char C1VREN:1;
813 unsigned char WREN:1;
814 unsigned char WRERR:1;
815 unsigned char CMDLY4:1;
816 unsigned char ADCS1:1;
817 unsigned char ADCS2:1;
818 unsigned char PRSEN:1;
821 unsigned char CMDLY0:1;
822 unsigned char CMDLY1:1;
823 unsigned char CMDLY2:1;
824 unsigned char CMDLY3:1;
825 unsigned char BLANK1:1;
826 unsigned char COMOD0:1;
827 unsigned char COMOD1:1;
828 unsigned char PWMASE:1;
831 unsigned char PH1EN:1;
832 unsigned char PH2EN:1;
833 unsigned char SYNC0:1;
834 unsigned char SYNC1:1;
835 unsigned char PER4:1;
836 unsigned char BLANK2:1;
837 unsigned char PASEN:1;
841 unsigned char PER0:1;
842 unsigned char PER1:1;
843 unsigned char PER2:1;
844 unsigned char PER3:1;
846 unsigned char PWMP0:1;
847 unsigned char PWMP1:1;
848 unsigned char C1ON:1;
855 unsigned char C1POL:1;
856 unsigned char C1EN:1;
857 unsigned char C2EN:1;
858 unsigned char C2ON:1;
861 unsigned char C1CH0:1;
862 unsigned char C1CH1:1;
864 unsigned char C1SP:1;
865 unsigned char C2POL:1;
866 unsigned char C1OE:1;
867 unsigned char C1OUT:1;
868 unsigned char MC1OUT:1;
871 unsigned char C2CH0:1;
872 unsigned char C2CH1:1;
874 unsigned char C2SP:1;
876 unsigned char C2OE:1;
877 unsigned char C2OUT:1;
878 unsigned char OPAON:1;
881 unsigned char C2SYNC:1;
882 unsigned char T1GSS:1;
887 unsigned char MC2OUT:1;
891 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
893 #define VR0 VRCON_bits.VR0
894 #define RD VRCON_bits.RD
895 #define CMDLY0 VRCON_bits.CMDLY0
896 #define PH1EN VRCON_bits.PH1EN
897 #define PER0 VRCON_bits.PER0
898 #define PH0 VRCON_bits.PH0
899 #define C1CH0 VRCON_bits.C1CH0
900 #define C2CH0 VRCON_bits.C2CH0
901 #define C2SYNC VRCON_bits.C2SYNC
902 #define VR1 VRCON_bits.VR1
903 #define WR VRCON_bits.WR
904 #define CMDLY1 VRCON_bits.CMDLY1
905 #define PH2EN VRCON_bits.PH2EN
906 #define PER1 VRCON_bits.PER1
907 #define PH1 VRCON_bits.PH1
908 #define C1CH1 VRCON_bits.C1CH1
909 #define C2CH1 VRCON_bits.C2CH1
910 #define T1GSS VRCON_bits.T1GSS
911 #define VR2 VRCON_bits.VR2
912 #define WREN VRCON_bits.WREN
913 #define CMDLY2 VRCON_bits.CMDLY2
914 #define SYNC0 VRCON_bits.SYNC0
915 #define PER2 VRCON_bits.PER2
916 #define PH2 VRCON_bits.PH2
917 #define C1R VRCON_bits.C1R
918 #define C2R VRCON_bits.C2R
919 #define VR3 VRCON_bits.VR3
920 #define WRERR VRCON_bits.WRERR
921 #define CMDLY3 VRCON_bits.CMDLY3
922 #define SYNC1 VRCON_bits.SYNC1
923 #define PER3 VRCON_bits.PER3
924 #define PH3 VRCON_bits.PH3
925 #define C1SP VRCON_bits.C1SP
926 #define C2SP VRCON_bits.C2SP
927 #define ADCS0 VRCON_bits.ADCS0
928 #define CMDLY4 VRCON_bits.CMDLY4
929 #define BLANK1 VRCON_bits.BLANK1
930 #define PER4 VRCON_bits.PER4
931 #define PH4 VRCON_bits.PH4
932 #define C1POL VRCON_bits.C1POL
933 #define C2POL VRCON_bits.C2POL
934 #define VRR VRCON_bits.VRR
935 #define ADCS1 VRCON_bits.ADCS1
936 #define COMOD0 VRCON_bits.COMOD0
937 #define BLANK2 VRCON_bits.BLANK2
938 #define PWMP0 VRCON_bits.PWMP0
939 #define C1EN VRCON_bits.C1EN
940 #define C1OE VRCON_bits.C1OE
941 #define C2OE VRCON_bits.C2OE
942 #define C2VREN VRCON_bits.C2VREN
943 #define ADCS2 VRCON_bits.ADCS2
944 #define COMOD1 VRCON_bits.COMOD1
945 #define PASEN VRCON_bits.PASEN
946 #define PWMP1 VRCON_bits.PWMP1
947 #define C2EN VRCON_bits.C2EN
948 #define C1OUT VRCON_bits.C1OUT
949 #define C2OUT VRCON_bits.C2OUT
950 #define MC2OUT VRCON_bits.MC2OUT
951 #define C1VREN VRCON_bits.C1VREN
952 #define PRSEN VRCON_bits.PRSEN
953 #define PWMASE VRCON_bits.PWMASE
954 #define POL VRCON_bits.POL
955 #define C1ON VRCON_bits.C1ON
956 #define C2ON VRCON_bits.C2ON
957 #define MC1OUT VRCON_bits.MC1OUT
958 #define OPAON VRCON_bits.OPAON
960 // ----- WDTCON bits --------------------
963 unsigned char SWDTEN:1;
964 unsigned char WDTPS0:1;
965 unsigned char WDTPS1:1;
966 unsigned char WDTPS2:1;
967 unsigned char WDTPS3:1;
973 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
975 #define SWDTEN WDTCON_bits.SWDTEN
976 #define WDTPS0 WDTCON_bits.WDTPS0
977 #define WDTPS1 WDTCON_bits.WDTPS1
978 #define WDTPS2 WDTCON_bits.WDTPS2
979 #define WDTPS3 WDTCON_bits.WDTPS3