2 // Register Declarations for Microchip 16F785 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0013
45 #define CCPR1H_ADDR 0x0014
46 #define CCP1CON_ADDR 0x0015
47 #define WDTCON_ADDR 0x0018
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PCON_ADDR 0x008E
56 #define OSCCON_ADDR 0x008F
57 #define OSCTUNE_ADDR 0x0090
58 #define ANSEL_ADDR 0x0091
59 #define ANSEL0_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define ANSEL1_ADDR 0x0093
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define REFCON_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define PWMCON1_ADDR 0x0110
76 #define PWMCON0_ADDR 0x0111
77 #define PWMCLK_ADDR 0x0112
78 #define PWMPH1_ADDR 0x0113
79 #define PWMPH2_ADDR 0x0114
80 #define CM1CON0_ADDR 0x0119
81 #define CM2CON0_ADDR 0x011A
82 #define CM2CON1_ADDR 0x011B
83 #define OPA1CON_ADDR 0x011C
84 #define OPA2CON_ADDR 0x011D
87 // Memory organization.
90 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
91 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
92 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
93 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
94 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
95 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
96 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
97 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
98 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
99 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
100 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
101 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
102 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
103 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
104 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
105 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
106 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
107 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
108 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
109 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
110 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
111 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
112 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
113 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
114 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
115 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
116 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
117 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
118 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
119 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
120 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
121 #pragma memmap ANSEL0_ADDR ANSEL0_ADDR SFR 0x000 // ANSEL0
122 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
123 #pragma memmap ANSEL1_ADDR ANSEL1_ADDR SFR 0x000 // ANSEL1
124 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
125 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
126 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
127 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
128 #pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON
129 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
130 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
131 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
132 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
133 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
134 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
135 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
136 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
137 #pragma memmap PWMCON1_ADDR PWMCON1_ADDR SFR 0x000 // PWMCON1
138 #pragma memmap PWMCON0_ADDR PWMCON0_ADDR SFR 0x000 // PWMCON0
139 #pragma memmap PWMCLK_ADDR PWMCLK_ADDR SFR 0x000 // PWMCLK
140 #pragma memmap PWMPH1_ADDR PWMPH1_ADDR SFR 0x000 // PWMPH1
141 #pragma memmap PWMPH2_ADDR PWMPH2_ADDR SFR 0x000 // PWMPH2
142 #pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
143 #pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
144 #pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
145 #pragma memmap OPA1CON_ADDR OPA1CON_ADDR SFR 0x000 // OPA1CON
146 #pragma memmap OPA2CON_ADDR OPA2CON_ADDR SFR 0x000 // OPA2CON
150 // P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
153 // This header file defines configurations, registers, and other useful bits of
154 // information for the PIC16F785 microcontroller. These names are taken to match
155 // the data sheets as closely as possible.
157 // Note that the processor must be selected before this file is
158 // included. The processor may be selected the following ways:
160 // 1. Command line switch:
161 // C:\ MPASM MYFILE.ASM /PIC16F785
162 // 2. LIST directive in the source file
164 // 3. Processor Type entry in the MPASM full-screen interface
166 //==========================================================================
170 //==========================================================================
171 //1.00 03/26/04 Original
172 //1.10 07/12/04 Updated for changes to REFCON and VRCON
173 //1.20 08/26/04 Updated for changes from BOD to BOR
174 //1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON
175 //1.40 10/25/04 Added WPUA3 bit to WPUA register
176 // Deleted OVRLP bit from PWMCON1 register
177 //==========================================================================
181 //==========================================================================
184 // MESSG "Processor-header file mismatch. Verify selected processor."
187 //==========================================================================
189 // Register Definitions
191 //==========================================================================
196 //----- Register Files------------------------------------------------------
198 extern __data __at (INDF_ADDR) volatile char INDF;
199 extern __sfr __at (TMR0_ADDR) TMR0;
200 extern __data __at (PCL_ADDR) volatile char PCL;
201 extern __sfr __at (STATUS_ADDR) STATUS;
202 extern __sfr __at (FSR_ADDR) FSR;
203 extern __sfr __at (PORTA_ADDR) PORTA;
204 extern __sfr __at (PORTB_ADDR) PORTB;
205 extern __sfr __at (PORTC_ADDR) PORTC;
207 extern __sfr __at (PCLATH_ADDR) PCLATH;
208 extern __sfr __at (INTCON_ADDR) INTCON;
209 extern __sfr __at (PIR1_ADDR) PIR1;
211 extern __sfr __at (TMR1L_ADDR) TMR1L;
212 extern __sfr __at (TMR1H_ADDR) TMR1H;
213 extern __sfr __at (T1CON_ADDR) T1CON;
214 extern __sfr __at (TMR2_ADDR) TMR2;
215 extern __sfr __at (T2CON_ADDR) T2CON;
216 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
217 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
218 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
220 extern __sfr __at (WDTCON_ADDR) WDTCON;
222 extern __sfr __at (ADRESH_ADDR) ADRESH;
223 extern __sfr __at (ADCON0_ADDR) ADCON0;
226 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
228 extern __sfr __at (TRISA_ADDR) TRISA;
229 extern __sfr __at (TRISB_ADDR) TRISB;
230 extern __sfr __at (TRISC_ADDR) TRISC;
232 extern __sfr __at (PIE1_ADDR) PIE1;
234 extern __sfr __at (PCON_ADDR) PCON;
235 extern __sfr __at (OSCCON_ADDR) OSCCON;
236 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
237 extern __sfr __at (ANSEL_ADDR) ANSEL;
238 extern __sfr __at (ANSEL0_ADDR) ANSEL0;
239 extern __sfr __at (PR2_ADDR) PR2;
240 extern __sfr __at (ANSEL1_ADDR) ANSEL1;
242 extern __sfr __at (WPU_ADDR) WPU;
243 extern __sfr __at (WPUA_ADDR) WPUA;
244 extern __sfr __at (IOC_ADDR) IOC;
245 extern __sfr __at (IOCA_ADDR) IOCA;
247 extern __sfr __at (REFCON_ADDR) REFCON;
248 extern __sfr __at (VRCON_ADDR) VRCON;
249 extern __sfr __at (EEDAT_ADDR) EEDAT;
250 extern __sfr __at (EEDATA_ADDR) EEDATA;
251 extern __sfr __at (EEADR_ADDR) EEADR;
252 extern __sfr __at (EECON1_ADDR) EECON1;
253 extern __sfr __at (EECON2_ADDR) EECON2;
254 extern __sfr __at (ADRESL_ADDR) ADRESL;
255 extern __sfr __at (ADCON1_ADDR) ADCON1;
258 extern __sfr __at (PWMCON1_ADDR) PWMCON1;
259 extern __sfr __at (PWMCON0_ADDR) PWMCON0;
260 extern __sfr __at (PWMCLK_ADDR) PWMCLK;
261 extern __sfr __at (PWMPH1_ADDR) PWMPH1;
262 extern __sfr __at (PWMPH2_ADDR) PWMPH2;
264 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
265 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
266 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
267 extern __sfr __at (OPA1CON_ADDR) OPA1CON;
268 extern __sfr __at (OPA2CON_ADDR) OPA2CON;
270 //----- STATUS Bits --------------------------------------------------------
273 //----- INTCON Bits --------------------------------------------------------
276 //----- PIR1 Bits ----------------------------------------------------------
279 //----- T1CON Bits ---------------------------------------------------------
282 //----- T2CON Bits ---------------------------------------------------------
285 //----- CCP1CON Bits -------------------------------------------------------
288 //----- WDTCON Bits --------------------------------------------------------
291 //----- ADCON0 Bits --------------------------------------------------------
294 //----- OPTION Bits --------------------------------------------------------
297 //----- PIE1 Bits ----------------------------------------------------------
300 //----- PCON Bits ----------------------------------------------------------
303 //----- OSCCON Bits --------------------------------------------------------
306 //----- OSCTUNE Bits -------------------------------------------------------
309 //----- ANSEL or ANSEL0 ----------------------------------------------------
312 //----- ANSEL1 -------------------------------------------------------------
315 //----- WPUA --------------------------------------------------------------
318 //----- IOC --------------------------------------------------------------
321 //----- IOCA --------------------------------------------------------------
324 //----- REFCON -------------------------------------------------------------
327 //----- VRCON Bits ---------------------------------------------------------
330 //----- EECON1 -------------------------------------------------------------
333 //----- ADCON1 -------------------------------------------------------------
336 //----- PWMCON1 -------------------------------------------------------------
339 //----- PWMCON0 -------------------------------------------------------------
342 //----- PWMCLK -------------------------------------------------------------
345 //----- PWMPH1 & PWMPH2 ----------------------------------------------------
348 //----- CM1CON0 -------------------------------------------------------------
351 //----- CM2CON0 -------------------------------------------------------------
354 //----- CM2CON1 -------------------------------------------------------------
357 //----- OPA1CON & OPA2CON ---------------------------------------------------
360 //==========================================================================
364 //==========================================================================
367 // __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D'
368 // __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF'
369 // __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F'
370 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
372 //==========================================================================
374 // Configuration Bits
376 //==========================================================================
378 #define _FCMEN_ON 0x3FFF
379 #define _FCMEN_OFF 0x37FF
380 #define _IESO_ON 0x3FFF
381 #define _IESO_OFF 0x3BFF
382 #define _BOD_ON 0x3FFF
383 #define _BOD_NSLEEP 0x3EFF
384 #define _BOD_SBODEN 0x3DFF
385 #define _BOD_OFF 0x3CFF
386 #define _BOR_ON 0x3FFF
387 #define _BOR_NSLEEP 0x3EFF
388 #define _BOR_SBOREN 0x3DFF
389 #define _BOR_OFF 0x3CFF
390 #define _CPD_ON 0x3F7F
391 #define _CPD_OFF 0x3FFF
392 #define _CP_ON 0x3FBF
393 #define _CP_OFF 0x3FFF
394 #define _MCLRE_ON 0x3FFF
395 #define _MCLRE_OFF 0x3FDF
396 #define _PWRTE_OFF 0x3FFF
397 #define _PWRTE_ON 0x3FEF
398 #define _WDT_ON 0x3FFF
399 #define _WDT_OFF 0x3FF7
400 #define _LP_OSC 0x3FF8
401 #define _XT_OSC 0x3FF9
402 #define _HS_OSC 0x3FFA
403 #define _EC_OSC 0x3FFB
404 #define _INTRC_OSC_NOCLKOUT 0x3FFC
405 #define _INTRC_OSC_CLKOUT 0x3FFD
406 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
407 #define _EXTRC_OSC_CLKOUT 0x3FFF
408 #define _INTOSCIO 0x3FFC
409 #define _INTOSC 0x3FFD
410 #define _EXTRCIO 0x3FFE
411 #define _EXTRC 0x3FFF
415 // ----- ADCON0 bits --------------------
418 unsigned char ADON:1;
420 unsigned char CHS0:1;
421 unsigned char CHS1:1;
422 unsigned char CHS2:1;
423 unsigned char CHS3:1;
424 unsigned char VCFG:1;
425 unsigned char ADFM:1;
429 unsigned char NOT_DONE:1;
439 unsigned char GO_DONE:1;
448 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
450 #define ADON ADCON0_bits.ADON
451 #define GO ADCON0_bits.GO
452 #define NOT_DONE ADCON0_bits.NOT_DONE
453 #define GO_DONE ADCON0_bits.GO_DONE
454 #define CHS0 ADCON0_bits.CHS0
455 #define CHS1 ADCON0_bits.CHS1
456 #define CHS2 ADCON0_bits.CHS2
457 #define CHS3 ADCON0_bits.CHS3
458 #define VCFG ADCON0_bits.VCFG
459 #define ADFM ADCON0_bits.ADFM
461 // ----- CCP1CON bits --------------------
464 unsigned char CCP1M0:1;
465 unsigned char CCP1M1:1;
466 unsigned char CCP1M2:1;
467 unsigned char CCP1M3:1;
468 unsigned char DC1B0:1;
469 unsigned char DC1B1:1;
474 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
476 #define CCP1M0 CCP1CON_bits.CCP1M0
477 #define CCP1M1 CCP1CON_bits.CCP1M1
478 #define CCP1M2 CCP1CON_bits.CCP1M2
479 #define CCP1M3 CCP1CON_bits.CCP1M3
480 #define DC1B0 CCP1CON_bits.DC1B0
481 #define DC1B1 CCP1CON_bits.DC1B1
483 // ----- INTCON bits --------------------
486 unsigned char RAIF:1;
487 unsigned char INTF:1;
488 unsigned char T0IF:1;
489 unsigned char RAIE:1;
490 unsigned char INTE:1;
491 unsigned char T0IE:1;
492 unsigned char PEIE:1;
496 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
498 #define RAIF INTCON_bits.RAIF
499 #define INTF INTCON_bits.INTF
500 #define T0IF INTCON_bits.T0IF
501 #define RAIE INTCON_bits.RAIE
502 #define INTE INTCON_bits.INTE
503 #define T0IE INTCON_bits.T0IE
504 #define PEIE INTCON_bits.PEIE
505 #define GIE INTCON_bits.GIE
507 // ----- OPTION_REG bits --------------------
514 unsigned char T0SE:1;
515 unsigned char T0CS:1;
516 unsigned char INTEDG:1;
517 unsigned char NOT_RAPU:1;
519 } __OPTION_REG_bits_t;
520 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
522 #define PS0 OPTION_REG_bits.PS0
523 #define PS1 OPTION_REG_bits.PS1
524 #define PS2 OPTION_REG_bits.PS2
525 #define PSA OPTION_REG_bits.PSA
526 #define T0SE OPTION_REG_bits.T0SE
527 #define T0CS OPTION_REG_bits.T0CS
528 #define INTEDG OPTION_REG_bits.INTEDG
529 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
531 // ----- OSCCON bits --------------------
537 unsigned char OSTS:1;
538 unsigned char IRCF0:1;
539 unsigned char IRCF1:1;
540 unsigned char IRCF2:1;
544 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
546 #define SCS OSCCON_bits.SCS
547 #define LTS OSCCON_bits.LTS
548 #define HTS OSCCON_bits.HTS
549 #define OSTS OSCCON_bits.OSTS
550 #define IRCF0 OSCCON_bits.IRCF0
551 #define IRCF1 OSCCON_bits.IRCF1
552 #define IRCF2 OSCCON_bits.IRCF2
554 // ----- OSCTUNE bits --------------------
557 unsigned char TUN0:1;
558 unsigned char TUN1:1;
559 unsigned char TUN2:1;
560 unsigned char TUN3:1;
561 unsigned char TUN4:1;
562 unsigned char ANS5:1;
563 unsigned char ANS6:1;
564 unsigned char ANS7:1;
567 unsigned char ANS0:1;
568 unsigned char ANS1:1;
569 unsigned char ANS2:1;
570 unsigned char ANS3:1;
571 unsigned char ANS4:1;
572 unsigned char WPUA5:1;
577 unsigned char ANS8:1;
578 unsigned char ANS9:1;
579 unsigned char ANS10:1;
580 unsigned char ANS11:1;
581 unsigned char WPUA4:1;
582 unsigned char IOC5:1;
587 unsigned char WPUA0:1;
588 unsigned char WPUA1:1;
589 unsigned char WPUA2:1;
590 unsigned char WPUA3:1;
591 unsigned char IOC4:1;
592 unsigned char IOCA5:1;
597 unsigned char IOC0:1;
598 unsigned char IOC1:1;
599 unsigned char IOC2:1;
600 unsigned char IOC3:1;
601 unsigned char IOCA4:1;
602 unsigned char BGST:1;
607 unsigned char IOCA0:1;
608 unsigned char IOCA1:1;
609 unsigned char IOCA2:1;
610 unsigned char IOCA3:1;
611 unsigned char VRBB:1;
618 unsigned char CVROE:1;
619 unsigned char VROE:1;
620 unsigned char VREN:1;
627 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
629 #define TUN0 OSCTUNE_bits.TUN0
630 #define ANS0 OSCTUNE_bits.ANS0
631 #define ANS8 OSCTUNE_bits.ANS8
632 #define WPUA0 OSCTUNE_bits.WPUA0
633 #define IOC0 OSCTUNE_bits.IOC0
634 #define IOCA0 OSCTUNE_bits.IOCA0
635 #define TUN1 OSCTUNE_bits.TUN1
636 #define ANS1 OSCTUNE_bits.ANS1
637 #define ANS9 OSCTUNE_bits.ANS9
638 #define WPUA1 OSCTUNE_bits.WPUA1
639 #define IOC1 OSCTUNE_bits.IOC1
640 #define IOCA1 OSCTUNE_bits.IOCA1
641 #define CVROE OSCTUNE_bits.CVROE
642 #define TUN2 OSCTUNE_bits.TUN2
643 #define ANS2 OSCTUNE_bits.ANS2
644 #define ANS10 OSCTUNE_bits.ANS10
645 #define WPUA2 OSCTUNE_bits.WPUA2
646 #define IOC2 OSCTUNE_bits.IOC2
647 #define IOCA2 OSCTUNE_bits.IOCA2
648 #define VROE OSCTUNE_bits.VROE
649 #define TUN3 OSCTUNE_bits.TUN3
650 #define ANS3 OSCTUNE_bits.ANS3
651 #define ANS11 OSCTUNE_bits.ANS11
652 #define WPUA3 OSCTUNE_bits.WPUA3
653 #define IOC3 OSCTUNE_bits.IOC3
654 #define IOCA3 OSCTUNE_bits.IOCA3
655 #define VREN OSCTUNE_bits.VREN
656 #define TUN4 OSCTUNE_bits.TUN4
657 #define ANS4 OSCTUNE_bits.ANS4
658 #define WPUA4 OSCTUNE_bits.WPUA4
659 #define IOC4 OSCTUNE_bits.IOC4
660 #define IOCA4 OSCTUNE_bits.IOCA4
661 #define VRBB OSCTUNE_bits.VRBB
662 #define ANS5 OSCTUNE_bits.ANS5
663 #define WPUA5 OSCTUNE_bits.WPUA5
664 #define IOC5 OSCTUNE_bits.IOC5
665 #define IOCA5 OSCTUNE_bits.IOCA5
666 #define BGST OSCTUNE_bits.BGST
667 #define ANS6 OSCTUNE_bits.ANS6
668 #define ANS7 OSCTUNE_bits.ANS7
670 // ----- PCON bits --------------------
673 unsigned char NOT_BOD:1;
674 unsigned char NOT_POR:1;
677 unsigned char SBODEN:1;
683 unsigned char NOT_BOR:1;
687 unsigned char SBOREN:1;
693 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
695 #define NOT_BOD PCON_bits.NOT_BOD
696 #define NOT_BOR PCON_bits.NOT_BOR
697 #define NOT_POR PCON_bits.NOT_POR
698 #define SBODEN PCON_bits.SBODEN
699 #define SBOREN PCON_bits.SBOREN
701 // ----- PIE1 bits --------------------
704 unsigned char T1IE:1;
705 unsigned char T2IE:1;
706 unsigned char OSFIE:1;
707 unsigned char C1IE:1;
708 unsigned char C2IE:1;
709 unsigned char CCP1IE:1;
710 unsigned char ADIE:1;
711 unsigned char EEIE:1;
714 unsigned char TMR1IE:1;
715 unsigned char TMR2IE:1;
724 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
726 #define T1IE PIE1_bits.T1IE
727 #define TMR1IE PIE1_bits.TMR1IE
728 #define T2IE PIE1_bits.T2IE
729 #define TMR2IE PIE1_bits.TMR2IE
730 #define OSFIE PIE1_bits.OSFIE
731 #define C1IE PIE1_bits.C1IE
732 #define C2IE PIE1_bits.C2IE
733 #define CCP1IE PIE1_bits.CCP1IE
734 #define ADIE PIE1_bits.ADIE
735 #define EEIE PIE1_bits.EEIE
737 // ----- PIR1 bits --------------------
740 unsigned char T1IF:1;
741 unsigned char T2IF:1;
742 unsigned char OSFIF:1;
743 unsigned char C1IF:1;
744 unsigned char C2IF:1;
745 unsigned char CCP1IF:1;
746 unsigned char ADIF:1;
747 unsigned char EEIF:1;
750 unsigned char TMR1IF:1;
751 unsigned char TMR2IF:1;
760 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
762 #define T1IF PIR1_bits.T1IF
763 #define TMR1IF PIR1_bits.TMR1IF
764 #define T2IF PIR1_bits.T2IF
765 #define TMR2IF PIR1_bits.TMR2IF
766 #define OSFIF PIR1_bits.OSFIF
767 #define C1IF PIR1_bits.C1IF
768 #define C2IF PIR1_bits.C2IF
769 #define CCP1IF PIR1_bits.CCP1IF
770 #define ADIF PIR1_bits.ADIF
771 #define EEIF PIR1_bits.EEIF
773 // ----- STATUS bits --------------------
779 unsigned char NOT_PD:1;
780 unsigned char NOT_TO:1;
786 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
788 #define C STATUS_bits.C
789 #define DC STATUS_bits.DC
790 #define Z STATUS_bits.Z
791 #define NOT_PD STATUS_bits.NOT_PD
792 #define NOT_TO STATUS_bits.NOT_TO
793 #define RP0 STATUS_bits.RP0
794 #define RP1 STATUS_bits.RP1
795 #define IRP STATUS_bits.IRP
797 // ----- T1CON bits --------------------
800 unsigned char TMR1ON:1;
801 unsigned char TMR1CS:1;
802 unsigned char NOT_T1SYNC:1;
803 unsigned char T1OSCEN:1;
804 unsigned char T1CKPS0:1;
805 unsigned char T1CKPS1:1;
806 unsigned char TMR1GE:1;
807 unsigned char T1GINV:1;
816 unsigned char T1GE:1;
820 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
822 #define TMR1ON T1CON_bits.TMR1ON
823 #define TMR1CS T1CON_bits.TMR1CS
824 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
825 #define T1OSCEN T1CON_bits.T1OSCEN
826 #define T1CKPS0 T1CON_bits.T1CKPS0
827 #define T1CKPS1 T1CON_bits.T1CKPS1
828 #define TMR1GE T1CON_bits.TMR1GE
829 #define T1GE T1CON_bits.T1GE
830 #define T1GINV T1CON_bits.T1GINV
832 // ----- T2CON bits --------------------
835 unsigned char T2CKPS0:1;
836 unsigned char T2CKPS1:1;
837 unsigned char TMR2ON:1;
838 unsigned char TOUTPS0:1;
839 unsigned char TOUTPS1:1;
840 unsigned char TOUTPS2:1;
841 unsigned char TOUTPS3:1;
845 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
847 #define T2CKPS0 T2CON_bits.T2CKPS0
848 #define T2CKPS1 T2CON_bits.T2CKPS1
849 #define TMR2ON T2CON_bits.TMR2ON
850 #define TOUTPS0 T2CON_bits.TOUTPS0
851 #define TOUTPS1 T2CON_bits.TOUTPS1
852 #define TOUTPS2 T2CON_bits.TOUTPS2
853 #define TOUTPS3 T2CON_bits.TOUTPS3
855 // ----- VRCON bits --------------------
862 unsigned char ADCS0:1;
864 unsigned char C2VREN:1;
865 unsigned char C1VREN:1;
870 unsigned char WREN:1;
871 unsigned char WRERR:1;
872 unsigned char CMDLY4:1;
873 unsigned char ADCS1:1;
874 unsigned char ADCS2:1;
875 unsigned char PRSEN:1;
878 unsigned char CMDLY0:1;
879 unsigned char CMDLY1:1;
880 unsigned char CMDLY2:1;
881 unsigned char CMDLY3:1;
882 unsigned char BLANK1:1;
883 unsigned char COMOD0:1;
884 unsigned char COMOD1:1;
885 unsigned char PWMASE:1;
888 unsigned char PH1EN:1;
889 unsigned char PH2EN:1;
890 unsigned char SYNC0:1;
891 unsigned char SYNC1:1;
892 unsigned char PER4:1;
893 unsigned char BLANK2:1;
894 unsigned char PASEN:1;
898 unsigned char PER0:1;
899 unsigned char PER1:1;
900 unsigned char PER2:1;
901 unsigned char PER3:1;
903 unsigned char PWMP0:1;
904 unsigned char PWMP1:1;
905 unsigned char C1ON:1;
912 unsigned char C1POL:1;
913 unsigned char C1EN:1;
914 unsigned char C2EN:1;
915 unsigned char C2ON:1;
918 unsigned char C1CH0:1;
919 unsigned char C1CH1:1;
921 unsigned char C1SP:1;
922 unsigned char C2POL:1;
923 unsigned char C1OE:1;
924 unsigned char C1OUT:1;
925 unsigned char MC1OUT:1;
928 unsigned char C2CH0:1;
929 unsigned char C2CH1:1;
931 unsigned char C2SP:1;
933 unsigned char C2OE:1;
934 unsigned char C2OUT:1;
935 unsigned char OPAON:1;
938 unsigned char C2SYNC:1;
939 unsigned char T1GSS:1;
944 unsigned char MC2OUT:1;
948 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
950 #define VR0 VRCON_bits.VR0
951 #define RD VRCON_bits.RD
952 #define CMDLY0 VRCON_bits.CMDLY0
953 #define PH1EN VRCON_bits.PH1EN
954 #define PER0 VRCON_bits.PER0
955 #define PH0 VRCON_bits.PH0
956 #define C1CH0 VRCON_bits.C1CH0
957 #define C2CH0 VRCON_bits.C2CH0
958 #define C2SYNC VRCON_bits.C2SYNC
959 #define VR1 VRCON_bits.VR1
960 #define WR VRCON_bits.WR
961 #define CMDLY1 VRCON_bits.CMDLY1
962 #define PH2EN VRCON_bits.PH2EN
963 #define PER1 VRCON_bits.PER1
964 #define PH1 VRCON_bits.PH1
965 #define C1CH1 VRCON_bits.C1CH1
966 #define C2CH1 VRCON_bits.C2CH1
967 #define T1GSS VRCON_bits.T1GSS
968 #define VR2 VRCON_bits.VR2
969 #define WREN VRCON_bits.WREN
970 #define CMDLY2 VRCON_bits.CMDLY2
971 #define SYNC0 VRCON_bits.SYNC0
972 #define PER2 VRCON_bits.PER2
973 #define PH2 VRCON_bits.PH2
974 #define C1R VRCON_bits.C1R
975 #define C2R VRCON_bits.C2R
976 #define VR3 VRCON_bits.VR3
977 #define WRERR VRCON_bits.WRERR
978 #define CMDLY3 VRCON_bits.CMDLY3
979 #define SYNC1 VRCON_bits.SYNC1
980 #define PER3 VRCON_bits.PER3
981 #define PH3 VRCON_bits.PH3
982 #define C1SP VRCON_bits.C1SP
983 #define C2SP VRCON_bits.C2SP
984 #define ADCS0 VRCON_bits.ADCS0
985 #define CMDLY4 VRCON_bits.CMDLY4
986 #define BLANK1 VRCON_bits.BLANK1
987 #define PER4 VRCON_bits.PER4
988 #define PH4 VRCON_bits.PH4
989 #define C1POL VRCON_bits.C1POL
990 #define C2POL VRCON_bits.C2POL
991 #define VRR VRCON_bits.VRR
992 #define ADCS1 VRCON_bits.ADCS1
993 #define COMOD0 VRCON_bits.COMOD0
994 #define BLANK2 VRCON_bits.BLANK2
995 #define PWMP0 VRCON_bits.PWMP0
996 #define C1EN VRCON_bits.C1EN
997 #define C1OE VRCON_bits.C1OE
998 #define C2OE VRCON_bits.C2OE
999 #define C2VREN VRCON_bits.C2VREN
1000 #define ADCS2 VRCON_bits.ADCS2
1001 #define COMOD1 VRCON_bits.COMOD1
1002 #define PASEN VRCON_bits.PASEN
1003 #define PWMP1 VRCON_bits.PWMP1
1004 #define C2EN VRCON_bits.C2EN
1005 #define C1OUT VRCON_bits.C1OUT
1006 #define C2OUT VRCON_bits.C2OUT
1007 #define MC2OUT VRCON_bits.MC2OUT
1008 #define C1VREN VRCON_bits.C1VREN
1009 #define PRSEN VRCON_bits.PRSEN
1010 #define PWMASE VRCON_bits.PWMASE
1011 #define POL VRCON_bits.POL
1012 #define C1ON VRCON_bits.C1ON
1013 #define C2ON VRCON_bits.C2ON
1014 #define MC1OUT VRCON_bits.MC1OUT
1015 #define OPAON VRCON_bits.OPAON
1017 // ----- WDTCON bits --------------------
1020 unsigned char SWDTEN:1;
1021 unsigned char WDTPS0:1;
1022 unsigned char WDTPS1:1;
1023 unsigned char WDTPS2:1;
1024 unsigned char WDTPS3:1;
1030 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1032 #define SWDTEN WDTCON_bits.SWDTEN
1033 #define WDTPS0 WDTCON_bits.WDTPS0
1034 #define WDTPS1 WDTCON_bits.WDTPS1
1035 #define WDTPS2 WDTCON_bits.WDTPS2
1036 #define WDTPS3 WDTCON_bits.WDTPS3