2 // Register Declarations for Microchip 16F785 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0013
45 #define CCPR1H_ADDR 0x0014
46 #define CCP1CON_ADDR 0x0015
47 #define WDTCON_ADDR 0x0018
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PCON_ADDR 0x008E
56 #define OSCCON_ADDR 0x008F
57 #define OSCTUNE_ADDR 0x0090
58 #define ANSEL_ADDR 0x0091
59 #define ANSEL0_ADDR 0x0091
60 #define PR2_ADDR 0x0092
61 #define ANSEL1_ADDR 0x0093
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define REFCON_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
75 #define PWMCON1_ADDR 0x0110
76 #define PWMCON0_ADDR 0x0111
77 #define PWMCLK_ADDR 0x0112
78 #define PWMPH1_ADDR 0x0113
79 #define PWMPH2_ADDR 0x0114
80 #define CM1CON0_ADDR 0x0119
81 #define CM2CON0_ADDR 0x011A
82 #define CM2CON1_ADDR 0x011B
83 #define OPA1CON_ADDR 0x011C
84 #define OPA2CON_ADDR 0x011D
87 // Memory organization.
93 // P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F785 microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F785
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
114 //1.00 03/26/04 Original
115 //1.10 07/12/04 Updated for changes to REFCON and VRCON
116 //1.20 08/26/04 Updated for changes from BOD to BOR
117 //1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON
118 //1.40 10/25/04 Added WPUA3 bit to WPUA register
119 // Deleted OVRLP bit from PWMCON1 register
120 //==========================================================================
124 //==========================================================================
127 // MESSG "Processor-header file mismatch. Verify selected processor."
130 //==========================================================================
132 // Register Definitions
134 //==========================================================================
139 //----- Register Files------------------------------------------------------
141 extern __sfr __at (INDF_ADDR) INDF;
142 extern __sfr __at (TMR0_ADDR) TMR0;
143 extern __sfr __at (PCL_ADDR) PCL;
144 extern __sfr __at (STATUS_ADDR) STATUS;
145 extern __sfr __at (FSR_ADDR) FSR;
146 extern __sfr __at (PORTA_ADDR) PORTA;
147 extern __sfr __at (PORTB_ADDR) PORTB;
148 extern __sfr __at (PORTC_ADDR) PORTC;
150 extern __sfr __at (PCLATH_ADDR) PCLATH;
151 extern __sfr __at (INTCON_ADDR) INTCON;
152 extern __sfr __at (PIR1_ADDR) PIR1;
154 extern __sfr __at (TMR1L_ADDR) TMR1L;
155 extern __sfr __at (TMR1H_ADDR) TMR1H;
156 extern __sfr __at (T1CON_ADDR) T1CON;
157 extern __sfr __at (TMR2_ADDR) TMR2;
158 extern __sfr __at (T2CON_ADDR) T2CON;
159 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
160 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
161 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
163 extern __sfr __at (WDTCON_ADDR) WDTCON;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
171 extern __sfr __at (TRISA_ADDR) TRISA;
172 extern __sfr __at (TRISB_ADDR) TRISB;
173 extern __sfr __at (TRISC_ADDR) TRISC;
175 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (OSCCON_ADDR) OSCCON;
179 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
180 extern __sfr __at (ANSEL_ADDR) ANSEL;
181 extern __sfr __at (ANSEL0_ADDR) ANSEL0;
182 extern __sfr __at (PR2_ADDR) PR2;
183 extern __sfr __at (ANSEL1_ADDR) ANSEL1;
185 extern __sfr __at (WPU_ADDR) WPU;
186 extern __sfr __at (WPUA_ADDR) WPUA;
187 extern __sfr __at (IOC_ADDR) IOC;
188 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (REFCON_ADDR) REFCON;
191 extern __sfr __at (VRCON_ADDR) VRCON;
192 extern __sfr __at (EEDAT_ADDR) EEDAT;
193 extern __sfr __at (EEDATA_ADDR) EEDATA;
194 extern __sfr __at (EEADR_ADDR) EEADR;
195 extern __sfr __at (EECON1_ADDR) EECON1;
196 extern __sfr __at (EECON2_ADDR) EECON2;
197 extern __sfr __at (ADRESL_ADDR) ADRESL;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
201 extern __sfr __at (PWMCON1_ADDR) PWMCON1;
202 extern __sfr __at (PWMCON0_ADDR) PWMCON0;
203 extern __sfr __at (PWMCLK_ADDR) PWMCLK;
204 extern __sfr __at (PWMPH1_ADDR) PWMPH1;
205 extern __sfr __at (PWMPH2_ADDR) PWMPH2;
207 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
208 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
209 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
210 extern __sfr __at (OPA1CON_ADDR) OPA1CON;
211 extern __sfr __at (OPA2CON_ADDR) OPA2CON;
213 //----- STATUS Bits --------------------------------------------------------
216 //----- INTCON Bits --------------------------------------------------------
219 //----- PIR1 Bits ----------------------------------------------------------
222 //----- T1CON Bits ---------------------------------------------------------
225 //----- T2CON Bits ---------------------------------------------------------
228 //----- CCP1CON Bits -------------------------------------------------------
231 //----- WDTCON Bits --------------------------------------------------------
234 //----- ADCON0 Bits --------------------------------------------------------
237 //----- OPTION Bits --------------------------------------------------------
240 //----- PIE1 Bits ----------------------------------------------------------
243 //----- PCON Bits ----------------------------------------------------------
246 //----- OSCCON Bits --------------------------------------------------------
249 //----- OSCTUNE Bits -------------------------------------------------------
252 //----- ANSEL or ANSEL0 ----------------------------------------------------
255 //----- ANSEL1 -------------------------------------------------------------
258 //----- WPUA --------------------------------------------------------------
261 //----- IOC --------------------------------------------------------------
264 //----- IOCA --------------------------------------------------------------
267 //----- REFCON -------------------------------------------------------------
270 //----- VRCON Bits ---------------------------------------------------------
273 //----- EECON1 -------------------------------------------------------------
276 //----- ADCON1 -------------------------------------------------------------
279 //----- PWMCON1 -------------------------------------------------------------
282 //----- PWMCON0 -------------------------------------------------------------
285 //----- PWMCLK -------------------------------------------------------------
288 //----- PWMPH1 & PWMPH2 ----------------------------------------------------
291 //----- CM1CON0 -------------------------------------------------------------
294 //----- CM2CON0 -------------------------------------------------------------
297 //----- CM2CON1 -------------------------------------------------------------
300 //----- OPA1CON & OPA2CON ---------------------------------------------------
303 //==========================================================================
307 //==========================================================================
310 // __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D'
311 // __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF'
312 // __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F'
313 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
315 //==========================================================================
317 // Configuration Bits
319 //==========================================================================
321 #define _FCMEN_ON 0x3FFF
322 #define _FCMEN_OFF 0x37FF
323 #define _IESO_ON 0x3FFF
324 #define _IESO_OFF 0x3BFF
325 #define _BOD_ON 0x3FFF
326 #define _BOD_NSLEEP 0x3EFF
327 #define _BOD_SBODEN 0x3DFF
328 #define _BOD_OFF 0x3CFF
329 #define _BOR_ON 0x3FFF
330 #define _BOR_NSLEEP 0x3EFF
331 #define _BOR_SBOREN 0x3DFF
332 #define _BOR_OFF 0x3CFF
333 #define _CPD_ON 0x3F7F
334 #define _CPD_OFF 0x3FFF
335 #define _CP_ON 0x3FBF
336 #define _CP_OFF 0x3FFF
337 #define _MCLRE_ON 0x3FFF
338 #define _MCLRE_OFF 0x3FDF
339 #define _PWRTE_OFF 0x3FFF
340 #define _PWRTE_ON 0x3FEF
341 #define _WDT_ON 0x3FFF
342 #define _WDT_OFF 0x3FF7
343 #define _LP_OSC 0x3FF8
344 #define _XT_OSC 0x3FF9
345 #define _HS_OSC 0x3FFA
346 #define _EC_OSC 0x3FFB
347 #define _INTRC_OSC_NOCLKOUT 0x3FFC
348 #define _INTRC_OSC_CLKOUT 0x3FFD
349 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
350 #define _EXTRC_OSC_CLKOUT 0x3FFF
351 #define _INTOSCIO 0x3FFC
352 #define _INTOSC 0x3FFD
353 #define _EXTRCIO 0x3FFE
354 #define _EXTRC 0x3FFF
358 // ----- ADCON0 bits --------------------
361 unsigned char ADON:1;
363 unsigned char CHS0:1;
364 unsigned char CHS1:1;
365 unsigned char CHS2:1;
366 unsigned char CHS3:1;
367 unsigned char VCFG:1;
368 unsigned char ADFM:1;
372 unsigned char NOT_DONE:1;
382 unsigned char GO_DONE:1;
391 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
393 #ifndef NO_BIT_DEFINES
394 #define ADON ADCON0_bits.ADON
395 #define GO ADCON0_bits.GO
396 #define NOT_DONE ADCON0_bits.NOT_DONE
397 #define GO_DONE ADCON0_bits.GO_DONE
398 #define CHS0 ADCON0_bits.CHS0
399 #define CHS1 ADCON0_bits.CHS1
400 #define CHS2 ADCON0_bits.CHS2
401 #define CHS3 ADCON0_bits.CHS3
402 #define VCFG ADCON0_bits.VCFG
403 #define ADFM ADCON0_bits.ADFM
404 #endif /* NO_BIT_DEFINES */
406 // ----- ADCON1 bits --------------------
413 unsigned char ADCS0:1;
414 unsigned char ADCS1:1;
415 unsigned char ADCS2:1;
419 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
421 #ifndef NO_BIT_DEFINES
422 #define ADCS0 ADCON1_bits.ADCS0
423 #define ADCS1 ADCON1_bits.ADCS1
424 #define ADCS2 ADCON1_bits.ADCS2
425 #endif /* NO_BIT_DEFINES */
427 // ----- ANSEL1 bits --------------------
430 unsigned char ANS8:1;
431 unsigned char ANS9:1;
432 unsigned char ANS10:1;
433 unsigned char ANS11:1;
440 extern volatile __ANSEL1_bits_t __at(ANSEL1_ADDR) ANSEL1_bits;
442 #ifndef NO_BIT_DEFINES
443 #define ANS8 ANSEL1_bits.ANS8
444 #define ANS9 ANSEL1_bits.ANS9
445 #define ANS10 ANSEL1_bits.ANS10
446 #define ANS11 ANSEL1_bits.ANS11
447 #endif /* NO_BIT_DEFINES */
449 // ----- CCP1CON bits --------------------
452 unsigned char CCP1M0:1;
453 unsigned char CCP1M1:1;
454 unsigned char CCP1M2:1;
455 unsigned char CCP1M3:1;
456 unsigned char DC1B0:1;
457 unsigned char DC1B1:1;
462 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
464 #ifndef NO_BIT_DEFINES
465 #define CCP1M0 CCP1CON_bits.CCP1M0
466 #define CCP1M1 CCP1CON_bits.CCP1M1
467 #define CCP1M2 CCP1CON_bits.CCP1M2
468 #define CCP1M3 CCP1CON_bits.CCP1M3
469 #define DC1B0 CCP1CON_bits.DC1B0
470 #define DC1B1 CCP1CON_bits.DC1B1
471 #endif /* NO_BIT_DEFINES */
473 // ----- CM1CON0 bits --------------------
476 unsigned char C1CH0:1;
477 unsigned char C1CH1:1;
479 unsigned char C1SP:1;
480 unsigned char C1POL:1;
481 unsigned char C1OE:1;
482 unsigned char C1OUT:1;
483 unsigned char C1ON:1;
486 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
488 #ifndef NO_BIT_DEFINES
489 #define C1CH0 CM1CON0_bits.C1CH0
490 #define C1CH1 CM1CON0_bits.C1CH1
491 #define C1R CM1CON0_bits.C1R
492 #define C1SP CM1CON0_bits.C1SP
493 #define C1POL CM1CON0_bits.C1POL
494 #define C1OE CM1CON0_bits.C1OE
495 #define C1OUT CM1CON0_bits.C1OUT
496 #define C1ON CM1CON0_bits.C1ON
497 #endif /* NO_BIT_DEFINES */
499 // ----- CM2CON0 bits --------------------
502 unsigned char C2CH0:1;
503 unsigned char C2CH1:1;
505 unsigned char C2SP:1;
506 unsigned char C2POL:1;
507 unsigned char C2OE:1;
508 unsigned char C2OUT:1;
509 unsigned char C2ON:1;
512 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
514 #ifndef NO_BIT_DEFINES
515 #define C2CH0 CM2CON0_bits.C2CH0
516 #define C2CH1 CM2CON0_bits.C2CH1
517 #define C2R CM2CON0_bits.C2R
518 #define C2SP CM2CON0_bits.C2SP
519 #define C2POL CM2CON0_bits.C2POL
520 #define C2OE CM2CON0_bits.C2OE
521 #define C2OUT CM2CON0_bits.C2OUT
522 #define C2ON CM2CON0_bits.C2ON
523 #endif /* NO_BIT_DEFINES */
525 // ----- CM2CON1 bits --------------------
528 unsigned char C2SYNC:1;
529 unsigned char T1GSS:1;
534 unsigned char MC2OUT:1;
535 unsigned char MC1OUT:1;
545 unsigned char OPAON:1;
548 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
550 #ifndef NO_BIT_DEFINES
551 #define C2SYNC CM2CON1_bits.C2SYNC
552 #define T1GSS CM2CON1_bits.T1GSS
553 #define MC2OUT CM2CON1_bits.MC2OUT
554 #define MC1OUT CM2CON1_bits.MC1OUT
555 #define OPAON CM2CON1_bits.OPAON
556 #endif /* NO_BIT_DEFINES */
558 // ----- EECON1 bits --------------------
563 unsigned char WREN:1;
564 unsigned char WRERR:1;
571 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
573 #ifndef NO_BIT_DEFINES
574 #define RD EECON1_bits.RD
575 #define WR EECON1_bits.WR
576 #define WREN EECON1_bits.WREN
577 #define WRERR EECON1_bits.WRERR
578 #endif /* NO_BIT_DEFINES */
580 // ----- INTCON bits --------------------
583 unsigned char RAIF:1;
584 unsigned char INTF:1;
585 unsigned char T0IF:1;
586 unsigned char RAIE:1;
587 unsigned char INTE:1;
588 unsigned char T0IE:1;
589 unsigned char PEIE:1;
593 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
595 #ifndef NO_BIT_DEFINES
596 #define RAIF INTCON_bits.RAIF
597 #define INTF INTCON_bits.INTF
598 #define T0IF INTCON_bits.T0IF
599 #define RAIE INTCON_bits.RAIE
600 #define INTE INTCON_bits.INTE
601 #define T0IE INTCON_bits.T0IE
602 #define PEIE INTCON_bits.PEIE
603 #define GIE INTCON_bits.GIE
604 #endif /* NO_BIT_DEFINES */
606 // ----- IOC bits --------------------
609 unsigned char IOC0:1;
610 unsigned char IOC1:1;
611 unsigned char IOC2:1;
612 unsigned char IOC3:1;
613 unsigned char IOC4:1;
614 unsigned char IOC5:1;
619 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
621 #ifndef NO_BIT_DEFINES
622 #define IOC0 IOC_bits.IOC0
623 #define IOC1 IOC_bits.IOC1
624 #define IOC2 IOC_bits.IOC2
625 #define IOC3 IOC_bits.IOC3
626 #define IOC4 IOC_bits.IOC4
627 #define IOC5 IOC_bits.IOC5
628 #endif /* NO_BIT_DEFINES */
630 // ----- IOCA bits --------------------
633 unsigned char IOCA0:1;
634 unsigned char IOCA1:1;
635 unsigned char IOCA2:1;
636 unsigned char IOCA3:1;
637 unsigned char IOCA4:1;
638 unsigned char IOCA5:1;
643 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
645 #ifndef NO_BIT_DEFINES
646 #define IOCA0 IOCA_bits.IOCA0
647 #define IOCA1 IOCA_bits.IOCA1
648 #define IOCA2 IOCA_bits.IOCA2
649 #define IOCA3 IOCA_bits.IOCA3
650 #define IOCA4 IOCA_bits.IOCA4
651 #define IOCA5 IOCA_bits.IOCA5
652 #endif /* NO_BIT_DEFINES */
654 // ----- OPTION_REG bits --------------------
661 unsigned char T0SE:1;
662 unsigned char T0CS:1;
663 unsigned char INTEDG:1;
664 unsigned char NOT_RAPU:1;
666 } __OPTION_REG_bits_t;
667 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
669 #ifndef NO_BIT_DEFINES
670 #define PS0 OPTION_REG_bits.PS0
671 #define PS1 OPTION_REG_bits.PS1
672 #define PS2 OPTION_REG_bits.PS2
673 #define PSA OPTION_REG_bits.PSA
674 #define T0SE OPTION_REG_bits.T0SE
675 #define T0CS OPTION_REG_bits.T0CS
676 #define INTEDG OPTION_REG_bits.INTEDG
677 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
678 #endif /* NO_BIT_DEFINES */
680 // ----- OSCCON bits --------------------
686 unsigned char OSTS:1;
687 unsigned char IRCF0:1;
688 unsigned char IRCF1:1;
689 unsigned char IRCF2:1;
693 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
695 #ifndef NO_BIT_DEFINES
696 #define SCS OSCCON_bits.SCS
697 #define LTS OSCCON_bits.LTS
698 #define HTS OSCCON_bits.HTS
699 #define OSTS OSCCON_bits.OSTS
700 #define IRCF0 OSCCON_bits.IRCF0
701 #define IRCF1 OSCCON_bits.IRCF1
702 #define IRCF2 OSCCON_bits.IRCF2
703 #endif /* NO_BIT_DEFINES */
705 // ----- OSCTUNE bits --------------------
708 unsigned char TUN0:1;
709 unsigned char TUN1:1;
710 unsigned char TUN2:1;
711 unsigned char TUN3:1;
712 unsigned char TUN4:1;
713 unsigned char ANS5:1;
714 unsigned char ANS6:1;
715 unsigned char ANS7:1;
718 unsigned char ANS0:1;
719 unsigned char ANS1:1;
720 unsigned char ANS2:1;
721 unsigned char ANS3:1;
722 unsigned char ANS4:1;
728 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
730 #ifndef NO_BIT_DEFINES
731 #define TUN0 OSCTUNE_bits.TUN0
732 #define ANS0 OSCTUNE_bits.ANS0
733 #define TUN1 OSCTUNE_bits.TUN1
734 #define ANS1 OSCTUNE_bits.ANS1
735 #define TUN2 OSCTUNE_bits.TUN2
736 #define ANS2 OSCTUNE_bits.ANS2
737 #define TUN3 OSCTUNE_bits.TUN3
738 #define ANS3 OSCTUNE_bits.ANS3
739 #define TUN4 OSCTUNE_bits.TUN4
740 #define ANS4 OSCTUNE_bits.ANS4
741 #define ANS5 OSCTUNE_bits.ANS5
742 #define ANS6 OSCTUNE_bits.ANS6
743 #define ANS7 OSCTUNE_bits.ANS7
744 #endif /* NO_BIT_DEFINES */
746 // ----- PCON bits --------------------
749 unsigned char NOT_BOD:1;
750 unsigned char NOT_POR:1;
753 unsigned char SBODEN:1;
759 unsigned char NOT_BOR:1;
763 unsigned char SBOREN:1;
769 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
771 #ifndef NO_BIT_DEFINES
772 #define NOT_BOD PCON_bits.NOT_BOD
773 #define NOT_BOR PCON_bits.NOT_BOR
774 #define NOT_POR PCON_bits.NOT_POR
775 #define SBODEN PCON_bits.SBODEN
776 #define SBOREN PCON_bits.SBOREN
777 #endif /* NO_BIT_DEFINES */
779 // ----- PIE1 bits --------------------
782 unsigned char T1IE:1;
783 unsigned char T2IE:1;
784 unsigned char OSFIE:1;
785 unsigned char C1IE:1;
786 unsigned char C2IE:1;
787 unsigned char CCP1IE:1;
788 unsigned char ADIE:1;
789 unsigned char EEIE:1;
792 unsigned char TMR1IE:1;
793 unsigned char TMR2IE:1;
802 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
804 #ifndef NO_BIT_DEFINES
805 #define T1IE PIE1_bits.T1IE
806 #define TMR1IE PIE1_bits.TMR1IE
807 #define T2IE PIE1_bits.T2IE
808 #define TMR2IE PIE1_bits.TMR2IE
809 #define OSFIE PIE1_bits.OSFIE
810 #define C1IE PIE1_bits.C1IE
811 #define C2IE PIE1_bits.C2IE
812 #define CCP1IE PIE1_bits.CCP1IE
813 #define ADIE PIE1_bits.ADIE
814 #define EEIE PIE1_bits.EEIE
815 #endif /* NO_BIT_DEFINES */
817 // ----- PIR1 bits --------------------
820 unsigned char T1IF:1;
821 unsigned char T2IF:1;
822 unsigned char OSFIF:1;
823 unsigned char C1IF:1;
824 unsigned char C2IF:1;
825 unsigned char CCP1IF:1;
826 unsigned char ADIF:1;
827 unsigned char EEIF:1;
830 unsigned char TMR1IF:1;
831 unsigned char TMR2IF:1;
840 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
842 #ifndef NO_BIT_DEFINES
843 #define T1IF PIR1_bits.T1IF
844 #define TMR1IF PIR1_bits.TMR1IF
845 #define T2IF PIR1_bits.T2IF
846 #define TMR2IF PIR1_bits.TMR2IF
847 #define OSFIF PIR1_bits.OSFIF
848 #define C1IF PIR1_bits.C1IF
849 #define C2IF PIR1_bits.C2IF
850 #define CCP1IF PIR1_bits.CCP1IF
851 #define ADIF PIR1_bits.ADIF
852 #define EEIF PIR1_bits.EEIF
853 #endif /* NO_BIT_DEFINES */
855 // ----- PORTA bits --------------------
868 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
870 #ifndef NO_BIT_DEFINES
871 #define RA0 PORTA_bits.RA0
872 #define RA1 PORTA_bits.RA1
873 #define RA2 PORTA_bits.RA2
874 #define RA3 PORTA_bits.RA3
875 #define RA4 PORTA_bits.RA4
876 #define RA5 PORTA_bits.RA5
877 #endif /* NO_BIT_DEFINES */
879 // ----- PORTB bits --------------------
892 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
894 #ifndef NO_BIT_DEFINES
895 #define RB0 PORTB_bits.RB0
896 #define RB1 PORTB_bits.RB1
897 #define RB2 PORTB_bits.RB2
898 #define RB3 PORTB_bits.RB3
899 #define RB4 PORTB_bits.RB4
900 #define RB5 PORTB_bits.RB5
901 #define RB6 PORTB_bits.RB6
902 #define RB7 PORTB_bits.RB7
903 #endif /* NO_BIT_DEFINES */
905 // ----- PORTC bits --------------------
918 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
920 #ifndef NO_BIT_DEFINES
921 #define RC0 PORTC_bits.RC0
922 #define RC1 PORTC_bits.RC1
923 #define RC2 PORTC_bits.RC2
924 #define RC3 PORTC_bits.RC3
925 #define RC4 PORTC_bits.RC4
926 #define RC5 PORTC_bits.RC5
927 #define RC6 PORTC_bits.RC6
928 #define RC7 PORTC_bits.RC7
929 #endif /* NO_BIT_DEFINES */
931 // ----- PWMCLK bits --------------------
934 unsigned char PER0:1;
935 unsigned char PER1:1;
936 unsigned char PER2:1;
937 unsigned char PER3:1;
938 unsigned char PER4:1;
939 unsigned char PWMP0:1;
940 unsigned char PWMP1:1;
941 unsigned char PWMASE:1;
949 unsigned char C1EN:1;
950 unsigned char C2EN:1;
954 extern volatile __PWMCLK_bits_t __at(PWMCLK_ADDR) PWMCLK_bits;
956 #ifndef NO_BIT_DEFINES
957 #define PER0 PWMCLK_bits.PER0
958 #define PH0 PWMCLK_bits.PH0
959 #define PER1 PWMCLK_bits.PER1
960 #define PH1 PWMCLK_bits.PH1
961 #define PER2 PWMCLK_bits.PER2
962 #define PH2 PWMCLK_bits.PH2
963 #define PER3 PWMCLK_bits.PER3
964 #define PH3 PWMCLK_bits.PH3
965 #define PER4 PWMCLK_bits.PER4
966 #define PH4 PWMCLK_bits.PH4
967 #define PWMP0 PWMCLK_bits.PWMP0
968 #define C1EN PWMCLK_bits.C1EN
969 #define PWMP1 PWMCLK_bits.PWMP1
970 #define C2EN PWMCLK_bits.C2EN
971 #define PWMASE PWMCLK_bits.PWMASE
972 #define POL PWMCLK_bits.POL
973 #endif /* NO_BIT_DEFINES */
975 // ----- PWMCON0 bits --------------------
978 unsigned char PH1EN:1;
979 unsigned char PH2EN:1;
980 unsigned char SYNC0:1;
981 unsigned char SYNC1:1;
982 unsigned char BLANK1:1;
983 unsigned char BLANK2:1;
984 unsigned char PASEN:1;
985 unsigned char PRSEN:1;
988 extern volatile __PWMCON0_bits_t __at(PWMCON0_ADDR) PWMCON0_bits;
990 #ifndef NO_BIT_DEFINES
991 #define PH1EN PWMCON0_bits.PH1EN
992 #define PH2EN PWMCON0_bits.PH2EN
993 #define SYNC0 PWMCON0_bits.SYNC0
994 #define SYNC1 PWMCON0_bits.SYNC1
995 #define BLANK1 PWMCON0_bits.BLANK1
996 #define BLANK2 PWMCON0_bits.BLANK2
997 #define PASEN PWMCON0_bits.PASEN
998 #define PRSEN PWMCON0_bits.PRSEN
999 #endif /* NO_BIT_DEFINES */
1001 // ----- PWMCON1 bits --------------------
1004 unsigned char CMDLY0:1;
1005 unsigned char CMDLY1:1;
1006 unsigned char CMDLY2:1;
1007 unsigned char CMDLY3:1;
1008 unsigned char CMDLY4:1;
1009 unsigned char COMOD0:1;
1010 unsigned char COMOD1:1;
1014 extern volatile __PWMCON1_bits_t __at(PWMCON1_ADDR) PWMCON1_bits;
1016 #ifndef NO_BIT_DEFINES
1017 #define CMDLY0 PWMCON1_bits.CMDLY0
1018 #define CMDLY1 PWMCON1_bits.CMDLY1
1019 #define CMDLY2 PWMCON1_bits.CMDLY2
1020 #define CMDLY3 PWMCON1_bits.CMDLY3
1021 #define CMDLY4 PWMCON1_bits.CMDLY4
1022 #define COMOD0 PWMCON1_bits.COMOD0
1023 #define COMOD1 PWMCON1_bits.COMOD1
1024 #endif /* NO_BIT_DEFINES */
1026 // ----- REFCON bits --------------------
1030 unsigned char CVROE:1;
1031 unsigned char VROE:1;
1032 unsigned char VREN:1;
1033 unsigned char VRBB:1;
1034 unsigned char BGST:1;
1039 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
1041 #ifndef NO_BIT_DEFINES
1042 #define CVROE REFCON_bits.CVROE
1043 #define VROE REFCON_bits.VROE
1044 #define VREN REFCON_bits.VREN
1045 #define VRBB REFCON_bits.VRBB
1046 #define BGST REFCON_bits.BGST
1047 #endif /* NO_BIT_DEFINES */
1049 // ----- STATUS bits --------------------
1055 unsigned char NOT_PD:1;
1056 unsigned char NOT_TO:1;
1057 unsigned char RP0:1;
1058 unsigned char RP1:1;
1059 unsigned char IRP:1;
1062 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1064 #ifndef NO_BIT_DEFINES
1065 #define C STATUS_bits.C
1066 #define DC STATUS_bits.DC
1067 #define Z STATUS_bits.Z
1068 #define NOT_PD STATUS_bits.NOT_PD
1069 #define NOT_TO STATUS_bits.NOT_TO
1070 #define RP0 STATUS_bits.RP0
1071 #define RP1 STATUS_bits.RP1
1072 #define IRP STATUS_bits.IRP
1073 #endif /* NO_BIT_DEFINES */
1075 // ----- T1CON bits --------------------
1078 unsigned char TMR1ON:1;
1079 unsigned char TMR1CS:1;
1080 unsigned char NOT_T1SYNC:1;
1081 unsigned char T1OSCEN:1;
1082 unsigned char T1CKPS0:1;
1083 unsigned char T1CKPS1:1;
1084 unsigned char TMR1GE:1;
1085 unsigned char T1GINV:1;
1094 unsigned char T1GE:1;
1098 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1100 #ifndef NO_BIT_DEFINES
1101 #define TMR1ON T1CON_bits.TMR1ON
1102 #define TMR1CS T1CON_bits.TMR1CS
1103 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1104 #define T1OSCEN T1CON_bits.T1OSCEN
1105 #define T1CKPS0 T1CON_bits.T1CKPS0
1106 #define T1CKPS1 T1CON_bits.T1CKPS1
1107 #define TMR1GE T1CON_bits.TMR1GE
1108 #define T1GE T1CON_bits.T1GE
1109 #define T1GINV T1CON_bits.T1GINV
1110 #endif /* NO_BIT_DEFINES */
1112 // ----- T2CON bits --------------------
1115 unsigned char T2CKPS0:1;
1116 unsigned char T2CKPS1:1;
1117 unsigned char TMR2ON:1;
1118 unsigned char TOUTPS0:1;
1119 unsigned char TOUTPS1:1;
1120 unsigned char TOUTPS2:1;
1121 unsigned char TOUTPS3:1;
1125 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1127 #ifndef NO_BIT_DEFINES
1128 #define T2CKPS0 T2CON_bits.T2CKPS0
1129 #define T2CKPS1 T2CON_bits.T2CKPS1
1130 #define TMR2ON T2CON_bits.TMR2ON
1131 #define TOUTPS0 T2CON_bits.TOUTPS0
1132 #define TOUTPS1 T2CON_bits.TOUTPS1
1133 #define TOUTPS2 T2CON_bits.TOUTPS2
1134 #define TOUTPS3 T2CON_bits.TOUTPS3
1135 #endif /* NO_BIT_DEFINES */
1137 // ----- TRISA bits --------------------
1140 unsigned char TRISA0:1;
1141 unsigned char TRISA1:1;
1142 unsigned char TRISA2:1;
1143 unsigned char TRISA3:1;
1144 unsigned char TRISA4:1;
1145 unsigned char TRISA5:1;
1150 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1152 #ifndef NO_BIT_DEFINES
1153 #define TRISA0 TRISA_bits.TRISA0
1154 #define TRISA1 TRISA_bits.TRISA1
1155 #define TRISA2 TRISA_bits.TRISA2
1156 #define TRISA3 TRISA_bits.TRISA3
1157 #define TRISA4 TRISA_bits.TRISA4
1158 #define TRISA5 TRISA_bits.TRISA5
1159 #endif /* NO_BIT_DEFINES */
1161 // ----- TRISB bits --------------------
1164 unsigned char TRISB0:1;
1165 unsigned char TRISB1:1;
1166 unsigned char TRISB2:1;
1167 unsigned char TRISB3:1;
1168 unsigned char TRISB4:1;
1169 unsigned char TRISB5:1;
1170 unsigned char TRISB6:1;
1171 unsigned char TRISB7:1;
1174 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1176 #ifndef NO_BIT_DEFINES
1177 #define TRISB0 TRISB_bits.TRISB0
1178 #define TRISB1 TRISB_bits.TRISB1
1179 #define TRISB2 TRISB_bits.TRISB2
1180 #define TRISB3 TRISB_bits.TRISB3
1181 #define TRISB4 TRISB_bits.TRISB4
1182 #define TRISB5 TRISB_bits.TRISB5
1183 #define TRISB6 TRISB_bits.TRISB6
1184 #define TRISB7 TRISB_bits.TRISB7
1185 #endif /* NO_BIT_DEFINES */
1187 // ----- TRISC bits --------------------
1190 unsigned char TRISC0:1;
1191 unsigned char TRISC1:1;
1192 unsigned char TRISC2:1;
1193 unsigned char TRISC3:1;
1194 unsigned char TRISC4:1;
1195 unsigned char TRISC5:1;
1196 unsigned char TRISC6:1;
1197 unsigned char TRISC7:1;
1200 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1202 #ifndef NO_BIT_DEFINES
1203 #define TRISC0 TRISC_bits.TRISC0
1204 #define TRISC1 TRISC_bits.TRISC1
1205 #define TRISC2 TRISC_bits.TRISC2
1206 #define TRISC3 TRISC_bits.TRISC3
1207 #define TRISC4 TRISC_bits.TRISC4
1208 #define TRISC5 TRISC_bits.TRISC5
1209 #define TRISC6 TRISC_bits.TRISC6
1210 #define TRISC7 TRISC_bits.TRISC7
1211 #endif /* NO_BIT_DEFINES */
1213 // ----- VRCON bits --------------------
1216 unsigned char VR0:1;
1217 unsigned char VR1:1;
1218 unsigned char VR2:1;
1219 unsigned char VR3:1;
1221 unsigned char VRR:1;
1222 unsigned char C2VREN:1;
1223 unsigned char C1VREN:1;
1226 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1228 #ifndef NO_BIT_DEFINES
1229 #define VR0 VRCON_bits.VR0
1230 #define VR1 VRCON_bits.VR1
1231 #define VR2 VRCON_bits.VR2
1232 #define VR3 VRCON_bits.VR3
1233 #define VRR VRCON_bits.VRR
1234 #define C2VREN VRCON_bits.C2VREN
1235 #define C1VREN VRCON_bits.C1VREN
1236 #endif /* NO_BIT_DEFINES */
1238 // ----- WDTCON bits --------------------
1241 unsigned char SWDTEN:1;
1242 unsigned char WDTPS0:1;
1243 unsigned char WDTPS1:1;
1244 unsigned char WDTPS2:1;
1245 unsigned char WDTPS3:1;
1251 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1253 #ifndef NO_BIT_DEFINES
1254 #define SWDTEN WDTCON_bits.SWDTEN
1255 #define WDTPS0 WDTCON_bits.WDTPS0
1256 #define WDTPS1 WDTCON_bits.WDTPS1
1257 #define WDTPS2 WDTCON_bits.WDTPS2
1258 #define WDTPS3 WDTCON_bits.WDTPS3
1259 #endif /* NO_BIT_DEFINES */
1261 // ----- WPUA bits --------------------
1264 unsigned char WPUA0:1;
1265 unsigned char WPUA1:1;
1266 unsigned char WPUA2:1;
1267 unsigned char WPUA3:1;
1268 unsigned char WPUA4:1;
1269 unsigned char WPUA5:1;
1274 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1276 #ifndef NO_BIT_DEFINES
1277 #define WPUA0 WPUA_bits.WPUA0
1278 #define WPUA1 WPUA_bits.WPUA1
1279 #define WPUA2 WPUA_bits.WPUA2
1280 #define WPUA3 WPUA_bits.WPUA3
1281 #define WPUA4 WPUA_bits.WPUA4
1282 #define WPUA5 WPUA_bits.WPUA5
1283 #endif /* NO_BIT_DEFINES */