2 // Register Declarations for Microchip 16F767 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTE_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define PIR1_ADDR 0x000C
40 #define PIR2_ADDR 0x000D
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define RCSTA_ADDR 0x0018
52 #define TXREG_ADDR 0x0019
53 #define RCREG_ADDR 0x001A
54 #define CCPR2L_ADDR 0x001B
55 #define CCPR2H_ADDR 0x001C
56 #define CCP2CON_ADDR 0x001D
57 #define ADRESH_ADDR 0x001E
58 #define ADCON0_ADDR 0x001F
59 #define OPTION_REG_ADDR 0x0081
60 #define TRISA_ADDR 0x0085
61 #define TRISB_ADDR 0x0086
62 #define TRISC_ADDR 0x0087
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define OSCCON_ADDR 0x008F
68 #define OSCTUNE_ADDR 0x0090
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define CCPR3L_ADDR 0x0095
74 #define CCPR3H_ADDR 0x0096
75 #define CCP3CON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define ADCON2_ADDR 0x009B
79 #define CMCON_ADDR 0x009C
80 #define CVRCON_ADDR 0x009D
81 #define ADRESL_ADDR 0x009E
82 #define ADCON1_ADDR 0x009F
83 #define WDTCON_ADDR 0x0105
84 #define LVDCON_ADDR 0x0109
85 #define PMDATA_ADDR 0x010C
86 #define PMADR_ADDR 0x010D
87 #define PMDATH_ADDR 0x010E
88 #define PMADRH_ADDR 0x010F
89 #define PMCON1_ADDR 0x018C
92 // Memory organization.
98 // P16F767.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
101 // This header file defines configurations, registers, and other useful bits of
102 // information for the PIC16F767 microcontroller. These names are taken to match
103 // the data sheets as closely as possible.
105 // Note that the processor must be selected before this file is
106 // included. The processor may be selected the following ways:
108 // 1. Command line switch:
109 // C:\ MPASM MYFILE.ASM /PIC16F767
110 // 2. LIST directive in the source file
112 // 3. Processor Type entry in the MPASM full-screen interface
114 //==========================================================================
118 //==========================================================================
121 //1.00 05/05/03 Initial Release
122 //1.01 10/21/03 Made changes to Program Memory register names.
123 //1.02 04/07/04 Added INT0IE & INT0IF bit names.
125 //==========================================================================
129 //==========================================================================
132 // MESSG "Processor-header file mismatch. Verify selected processor."
135 //==========================================================================
137 // Register Definitions
139 //==========================================================================
144 //----- Register Files------------------------------------------------------
146 extern __data __at (INDF_ADDR) volatile char INDF;
147 extern __sfr __at (TMR0_ADDR) TMR0;
148 extern __data __at (PCL_ADDR) volatile char PCL;
149 extern __sfr __at (STATUS_ADDR) STATUS;
150 extern __sfr __at (FSR_ADDR) FSR;
151 extern __sfr __at (PORTA_ADDR) PORTA;
152 extern __sfr __at (PORTB_ADDR) PORTB;
153 extern __sfr __at (PORTC_ADDR) PORTC;
154 extern __sfr __at (PORTE_ADDR) PORTE;
155 extern __sfr __at (PCLATH_ADDR) PCLATH;
156 extern __sfr __at (INTCON_ADDR) INTCON;
157 extern __sfr __at (PIR1_ADDR) PIR1;
158 extern __sfr __at (PIR2_ADDR) PIR2;
159 extern __sfr __at (TMR1L_ADDR) TMR1L;
160 extern __sfr __at (TMR1H_ADDR) TMR1H;
161 extern __sfr __at (T1CON_ADDR) T1CON;
162 extern __sfr __at (TMR2_ADDR) TMR2;
163 extern __sfr __at (T2CON_ADDR) T2CON;
164 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
165 extern __sfr __at (SSPCON_ADDR) SSPCON;
166 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
167 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
168 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
169 extern __sfr __at (RCSTA_ADDR) RCSTA;
170 extern __sfr __at (TXREG_ADDR) TXREG;
171 extern __sfr __at (RCREG_ADDR) RCREG;
172 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
173 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
174 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
175 extern __sfr __at (ADRESH_ADDR) ADRESH;
176 extern __sfr __at (ADCON0_ADDR) ADCON0;
178 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
179 extern __sfr __at (TRISA_ADDR) TRISA;
180 extern __sfr __at (TRISB_ADDR) TRISB;
181 extern __sfr __at (TRISC_ADDR) TRISC;
182 extern __sfr __at (TRISE_ADDR) TRISE;
183 extern __sfr __at (PIE1_ADDR) PIE1;
184 extern __sfr __at (PIE2_ADDR) PIE2;
185 extern __sfr __at (PCON_ADDR) PCON;
186 extern __sfr __at (OSCCON_ADDR) OSCCON;
187 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
188 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
189 extern __sfr __at (PR2_ADDR) PR2;
190 extern __sfr __at (SSPADD_ADDR) SSPADD;
191 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
192 extern __sfr __at (CCPR3L_ADDR) CCPR3L;
193 extern __sfr __at (CCPR3H_ADDR) CCPR3H;
194 extern __sfr __at (CCP3CON_ADDR) CCP3CON;
195 extern __sfr __at (TXSTA_ADDR) TXSTA;
196 extern __sfr __at (SPBRG_ADDR) SPBRG;
197 extern __sfr __at (ADCON2_ADDR) ADCON2;
198 extern __sfr __at (CMCON_ADDR) CMCON;
199 extern __sfr __at (CVRCON_ADDR) CVRCON;
200 extern __sfr __at (ADRESL_ADDR) ADRESL;
201 extern __sfr __at (ADCON1_ADDR) ADCON1;
203 extern __sfr __at (WDTCON_ADDR) WDTCON;
204 extern __sfr __at (LVDCON_ADDR) LVDCON;
205 extern __sfr __at (PMDATA_ADDR) PMDATA;
206 extern __sfr __at (PMADR_ADDR) PMADR;
207 extern __sfr __at (PMDATH_ADDR) PMDATH;
208 extern __sfr __at (PMADRH_ADDR) PMADRH;
210 extern __sfr __at (PMCON1_ADDR) PMCON1;
212 //----- STATUS Bits --------------------------------------------------------
215 //----- INTCON Bits --------------------------------------------------------
218 //----- PIR1 Bits ----------------------------------------------------------
221 //----- PIR2 Bits ----------------------------------------------------------
224 //----- T1CON Bits ---------------------------------------------------------
227 //----- T2CON Bits ---------------------------------------------------------
230 //----- SSPCON Bits --------------------------------------------------------
233 //----- CCP1CON Bits -------------------------------------------------------
236 //----- RCSTA Bits ---------------------------------------------------------
239 //----- CCP2CON Bits -------------------------------------------------------
242 //----- ADCON0 Bits --------------------------------------------------------
245 //----- OPTION_REG Bits -----------------------------------------------------
248 //----- TRISE Bits ---------------------------------------------------------
251 //----- PIE1 Bits ----------------------------------------------------------
254 //----- PIE2 Bits ----------------------------------------------------------
257 //----- PCON Bits ----------------------------------------------------------
260 //----- OSCCON Bits -------------------------------------------------------
262 //----- OSCTUNE Bits -------------------------------------------------------
264 //----- SSPCON2 Bits --------------------------------------------------------
267 //----- SSPSTAT Bits -------------------------------------------------------
270 //----- CCP3CON Bits -------------------------------------------------------
273 //----- TXSTA Bits ---------------------------------------------------------
276 //----- ADCON2 Bits ---------------------------------------------------------
279 //----- CMCON Bits ---------------------------------------------------------
282 //----- CVRCON Bits --------------------------------------------------------
285 //----- ADCON1 Bits --------------------------------------------------------
288 //----- WDTCON Bits --------------------------------------------------------
291 //----- LVDCON Bits --------------------------------------------------------
294 //----- PMCON1 Bits --------------------------------------------------------
298 //==========================================================================
302 //==========================================================================
306 // __BADRAM H'88', H'9A'
307 // __BADRAM H'107'-H'108'
308 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
310 //==========================================================================
312 // Configuration Bits
314 //==========================================================================
316 #define _CONFIG1 0x2007
317 #define _CONFIG2 0x2008
319 //Configuration Byte 1 Options
320 #define _CP_ALL 0x1FFF
321 #define _CP_OFF 0x3FFF
322 #define _CCP2_RC1 0x3FFF
323 #define _CCP2_RB3 0x2FFF
324 #define _DEBUG_OFF 0x3FFF
325 #define _DEBUG_ON 0x37FF
326 #define _VBOR_2_0 0x3FFF
327 #define _VBOR_2_7 0x3F7F
328 #define _VBOR_4_2 0x3EFF
329 #define _VBOR_4_5 0x3E7F
330 #define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
331 #define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
332 #define _MCLR_ON 0x3FFF
333 #define _MCLR_OFF 0x3FDF
334 #define _PWRTE_OFF 0x3FFF
335 #define _PWRTE_ON 0x3FF7
336 #define _WDT_ON 0x3FFF
337 #define _WDT_OFF 0x3FFB
338 #define _EXTRC_CLKOUT 0x3FFF
339 #define _EXTRC_IO 0x3FFE
340 #define _INTRC_CLKOUT 0x3FFD
341 #define _INTRC_IO 0x3FFC
342 #define _EXTCLK 0x3FEF
343 #define _HS_OSC 0x3FEE
344 #define _XT_OSC 0x3FED
345 #define _LP_OSC 0x3FEC
347 //Configuration Byte 2 Options
348 #define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
349 #define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
350 #define _IESO_ON 0x3FFF
351 #define _IESO_OFF 0x3FFD
352 #define _FCMEN_ON 0x3FFF
353 #define _FCMEN_OFF 0x3FFE
356 //**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details)
357 //BOREN_1 & BORSEN_1 = BOR enabled and always on
358 //BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware
359 //BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2)
360 //BOREN_0 & BORSEN_0 = BOR disabled
363 // To use the Configuration Bits, place the following lines in your source code
364 // in the following format, and change the configuration value to the desired
365 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
366 // and each __CONFIG line should have the preceding semicolon removed when
367 // pasted into your source code.
369 //Program Configuration Register 1
370 // __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
372 //Program Configuration Register 2
373 // __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF
378 // ----- ADCON0 bits --------------------
381 unsigned char ADON:1;
382 unsigned char CHS3:1;
384 unsigned char CHS0:1;
385 unsigned char CHS1:1;
386 unsigned char CHS2:1;
387 unsigned char ADCS0:1;
388 unsigned char ADCS1:1;
393 unsigned char NOT_DONE:1;
403 unsigned char GO_DONE:1;
411 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
413 #define ADON ADCON0_bits.ADON
414 #define CHS3 ADCON0_bits.CHS3
415 #define GO ADCON0_bits.GO
416 #define NOT_DONE ADCON0_bits.NOT_DONE
417 #define GO_DONE ADCON0_bits.GO_DONE
418 #define CHS0 ADCON0_bits.CHS0
419 #define CHS1 ADCON0_bits.CHS1
420 #define CHS2 ADCON0_bits.CHS2
421 #define ADCS0 ADCON0_bits.ADCS0
422 #define ADCS1 ADCON0_bits.ADCS1
424 // ----- ADCON1 bits --------------------
427 unsigned char PCFG0:1;
428 unsigned char PCFG1:1;
429 unsigned char PCFG2:1;
430 unsigned char PCFG3:1;
431 unsigned char VCFG0:1;
432 unsigned char VCFG1:1;
433 unsigned char ADCS2:1;
434 unsigned char ADFM:1;
437 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
439 #define PCFG0 ADCON1_bits.PCFG0
440 #define PCFG1 ADCON1_bits.PCFG1
441 #define PCFG2 ADCON1_bits.PCFG2
442 #define PCFG3 ADCON1_bits.PCFG3
443 #define VCFG0 ADCON1_bits.VCFG0
444 #define VCFG1 ADCON1_bits.VCFG1
445 #define ADCS2 ADCON1_bits.ADCS2
446 #define ADFM ADCON1_bits.ADFM
448 // ----- ADCON2 bits --------------------
454 unsigned char ACQT0:1;
455 unsigned char ACQT1:1;
456 unsigned char ACQT2:1;
461 extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits;
463 #define ACQT0 ADCON2_bits.ACQT0
464 #define ACQT1 ADCON2_bits.ACQT1
465 #define ACQT2 ADCON2_bits.ACQT2
467 // ----- CCP1CON bits --------------------
470 unsigned char CCP1M0:1;
471 unsigned char CCP1M1:1;
472 unsigned char CCP1M2:1;
473 unsigned char CCP1M3:1;
474 unsigned char CCP1Y:1;
475 unsigned char CCP1X:1;
480 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
482 #define CCP1M0 CCP1CON_bits.CCP1M0
483 #define CCP1M1 CCP1CON_bits.CCP1M1
484 #define CCP1M2 CCP1CON_bits.CCP1M2
485 #define CCP1M3 CCP1CON_bits.CCP1M3
486 #define CCP1Y CCP1CON_bits.CCP1Y
487 #define CCP1X CCP1CON_bits.CCP1X
489 // ----- CCP2CON bits --------------------
492 unsigned char CCP2M0:1;
493 unsigned char CCP2M1:1;
494 unsigned char CCP2M2:1;
495 unsigned char CCP2M3:1;
496 unsigned char CCP2Y:1;
497 unsigned char CCP2X:1;
502 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
504 #define CCP2M0 CCP2CON_bits.CCP2M0
505 #define CCP2M1 CCP2CON_bits.CCP2M1
506 #define CCP2M2 CCP2CON_bits.CCP2M2
507 #define CCP2M3 CCP2CON_bits.CCP2M3
508 #define CCP2Y CCP2CON_bits.CCP2Y
509 #define CCP2X CCP2CON_bits.CCP2X
511 // ----- CCP3CON bits --------------------
514 unsigned char CCP3M0:1;
515 unsigned char CCP3M1:1;
516 unsigned char CCP3M2:1;
517 unsigned char CCP3M3:1;
518 unsigned char CCP3Y:1;
519 unsigned char CCP3X:1;
524 extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits;
526 #define CCP3M0 CCP3CON_bits.CCP3M0
527 #define CCP3M1 CCP3CON_bits.CCP3M1
528 #define CCP3M2 CCP3CON_bits.CCP3M2
529 #define CCP3M3 CCP3CON_bits.CCP3M3
530 #define CCP3Y CCP3CON_bits.CCP3Y
531 #define CCP3X CCP3CON_bits.CCP3X
533 // ----- CMCON bits --------------------
540 unsigned char C1INV:1;
541 unsigned char C2INV:1;
542 unsigned char C1OUT:1;
543 unsigned char C2OUT:1;
546 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
548 #define CM0 CMCON_bits.CM0
549 #define CM1 CMCON_bits.CM1
550 #define CM2 CMCON_bits.CM2
551 #define CIS CMCON_bits.CIS
552 #define C1INV CMCON_bits.C1INV
553 #define C2INV CMCON_bits.C2INV
554 #define C1OUT CMCON_bits.C1OUT
555 #define C2OUT CMCON_bits.C2OUT
557 // ----- CVRCON bits --------------------
560 unsigned char CVR0:1;
561 unsigned char CVR1:1;
562 unsigned char CVR2:1;
563 unsigned char CVR3:1;
565 unsigned char CVRR:1;
566 unsigned char CVROE:1;
567 unsigned char CVREN:1;
570 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
572 #define CVR0 CVRCON_bits.CVR0
573 #define CVR1 CVRCON_bits.CVR1
574 #define CVR2 CVRCON_bits.CVR2
575 #define CVR3 CVRCON_bits.CVR3
576 #define CVRR CVRCON_bits.CVRR
577 #define CVROE CVRCON_bits.CVROE
578 #define CVREN CVRCON_bits.CVREN
580 // ----- INTCON bits --------------------
583 unsigned char RBIF:1;
584 unsigned char INTF:1;
585 unsigned char T0IF:1;
586 unsigned char RBIE:1;
587 unsigned char INTE:1;
588 unsigned char T0IE:1;
589 unsigned char PEIE:1;
594 unsigned char INT0IF:1;
595 unsigned char TMR0IF:1;
597 unsigned char INT0IE:1;
598 unsigned char TMR0IE:1;
603 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
605 #define RBIF INTCON_bits.RBIF
606 #define INTF INTCON_bits.INTF
607 #define INT0IF INTCON_bits.INT0IF
608 #define T0IF INTCON_bits.T0IF
609 #define TMR0IF INTCON_bits.TMR0IF
610 #define RBIE INTCON_bits.RBIE
611 #define INTE INTCON_bits.INTE
612 #define INT0IE INTCON_bits.INT0IE
613 #define T0IE INTCON_bits.T0IE
614 #define TMR0IE INTCON_bits.TMR0IE
615 #define PEIE INTCON_bits.PEIE
616 #define GIE INTCON_bits.GIE
618 // ----- LVDCON bits --------------------
621 unsigned char LVDL0:1;
622 unsigned char LVDL1:1;
623 unsigned char LVDL2:1;
624 unsigned char LVDL3:1;
625 unsigned char LVDEN:1;
626 unsigned char IRVST:1;
631 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
633 #define LVDL0 LVDCON_bits.LVDL0
634 #define LVDL1 LVDCON_bits.LVDL1
635 #define LVDL2 LVDCON_bits.LVDL2
636 #define LVDL3 LVDCON_bits.LVDL3
637 #define LVDEN LVDCON_bits.LVDEN
638 #define IRVST LVDCON_bits.IRVST
640 // ----- OPTION_REG bits --------------------
647 unsigned char T0SE:1;
648 unsigned char T0CS:1;
649 unsigned char INTEDG:1;
650 unsigned char NOT_RBPU:1;
652 } __OPTION_REG_bits_t;
653 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
655 #define PS0 OPTION_REG_bits.PS0
656 #define PS1 OPTION_REG_bits.PS1
657 #define PS2 OPTION_REG_bits.PS2
658 #define PSA OPTION_REG_bits.PSA
659 #define T0SE OPTION_REG_bits.T0SE
660 #define T0CS OPTION_REG_bits.T0CS
661 #define INTEDG OPTION_REG_bits.INTEDG
662 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
664 // ----- OSCCON bits --------------------
667 unsigned char SCS0:1;
668 unsigned char SCS1:1;
669 unsigned char IOFS:1;
670 unsigned char OSTS:1;
671 unsigned char IRCF0:1;
672 unsigned char IRCF1:1;
673 unsigned char IRCF2:1;
677 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
679 #define SCS0 OSCCON_bits.SCS0
680 #define SCS1 OSCCON_bits.SCS1
681 #define IOFS OSCCON_bits.IOFS
682 #define OSTS OSCCON_bits.OSTS
683 #define IRCF0 OSCCON_bits.IRCF0
684 #define IRCF1 OSCCON_bits.IRCF1
685 #define IRCF2 OSCCON_bits.IRCF2
687 // ----- OSCTUNE bits --------------------
690 unsigned char TUN0:1;
691 unsigned char TUN1:1;
692 unsigned char TUN2:1;
693 unsigned char TUN3:1;
694 unsigned char TUN4:1;
695 unsigned char TUN5:1;
700 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
702 #define TUN0 OSCTUNE_bits.TUN0
703 #define TUN1 OSCTUNE_bits.TUN1
704 #define TUN2 OSCTUNE_bits.TUN2
705 #define TUN3 OSCTUNE_bits.TUN3
706 #define TUN4 OSCTUNE_bits.TUN4
707 #define TUN5 OSCTUNE_bits.TUN5
709 // ----- PCON bits --------------------
712 unsigned char NOT_BO:1;
713 unsigned char NOT_POR:1;
714 unsigned char SBOREN:1;
722 unsigned char NOT_BOR:1;
732 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
734 #define NOT_BO PCON_bits.NOT_BO
735 #define NOT_BOR PCON_bits.NOT_BOR
736 #define NOT_POR PCON_bits.NOT_POR
737 #define SBOREN PCON_bits.SBOREN
739 // ----- PIE1 bits --------------------
742 unsigned char TMR1IE:1;
743 unsigned char TMR2IE:1;
744 unsigned char CCP1IE:1;
745 unsigned char SSPIE:1;
746 unsigned char TXIE:1;
747 unsigned char RCIE:1;
748 unsigned char ADIE:1;
749 unsigned char PSPIE:1;
752 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
754 #define TMR1IE PIE1_bits.TMR1IE
755 #define TMR2IE PIE1_bits.TMR2IE
756 #define CCP1IE PIE1_bits.CCP1IE
757 #define SSPIE PIE1_bits.SSPIE
758 #define TXIE PIE1_bits.TXIE
759 #define RCIE PIE1_bits.RCIE
760 #define ADIE PIE1_bits.ADIE
761 #define PSPIE PIE1_bits.PSPIE
763 // ----- PIE2 bits --------------------
766 unsigned char CCP2IE:1;
767 unsigned char CCP3IE:1;
769 unsigned char BCLIE:1;
771 unsigned char LVDIE:1;
772 unsigned char CMIE:1;
773 unsigned char OSFIE:1;
776 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
778 #define CCP2IE PIE2_bits.CCP2IE
779 #define CCP3IE PIE2_bits.CCP3IE
780 #define BCLIE PIE2_bits.BCLIE
781 #define LVDIE PIE2_bits.LVDIE
782 #define CMIE PIE2_bits.CMIE
783 #define OSFIE PIE2_bits.OSFIE
785 // ----- PIR1 bits --------------------
788 unsigned char TMR1IF:1;
789 unsigned char TMR2IF:1;
790 unsigned char CCP1IF:1;
791 unsigned char SSPIF:1;
792 unsigned char TXIF:1;
793 unsigned char RCIF:1;
794 unsigned char ADIF:1;
795 unsigned char PSPIF:1;
798 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
800 #define TMR1IF PIR1_bits.TMR1IF
801 #define TMR2IF PIR1_bits.TMR2IF
802 #define CCP1IF PIR1_bits.CCP1IF
803 #define SSPIF PIR1_bits.SSPIF
804 #define TXIF PIR1_bits.TXIF
805 #define RCIF PIR1_bits.RCIF
806 #define ADIF PIR1_bits.ADIF
807 #define PSPIF PIR1_bits.PSPIF
809 // ----- PIR2 bits --------------------
812 unsigned char CCP2IF:1;
813 unsigned char CCP3IF:1;
815 unsigned char BCLIF:1;
817 unsigned char LVDIF:1;
818 unsigned char CMIF:1;
819 unsigned char OSFIF:1;
822 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
824 #define CCP2IF PIR2_bits.CCP2IF
825 #define CCP3IF PIR2_bits.CCP3IF
826 #define BCLIF PIR2_bits.BCLIF
827 #define LVDIF PIR2_bits.LVDIF
828 #define CMIF PIR2_bits.CMIF
829 #define OSFIF PIR2_bits.OSFIF
831 // ----- PMCON1 bits --------------------
844 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
846 #define RD PMCON1_bits.RD
848 // ----- PORTA bits --------------------
861 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
863 #define RA0 PORTA_bits.RA0
864 #define RA1 PORTA_bits.RA1
865 #define RA2 PORTA_bits.RA2
866 #define RA3 PORTA_bits.RA3
867 #define RA4 PORTA_bits.RA4
868 #define RA5 PORTA_bits.RA5
870 // ----- PORTB bits --------------------
883 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
885 #define RB0 PORTB_bits.RB0
886 #define RB1 PORTB_bits.RB1
887 #define RB2 PORTB_bits.RB2
888 #define RB3 PORTB_bits.RB3
889 #define RB4 PORTB_bits.RB4
890 #define RB5 PORTB_bits.RB5
891 #define RB6 PORTB_bits.RB6
892 #define RB7 PORTB_bits.RB7
894 // ----- PORTC bits --------------------
907 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
909 #define RC0 PORTC_bits.RC0
910 #define RC1 PORTC_bits.RC1
911 #define RC2 PORTC_bits.RC2
912 #define RC3 PORTC_bits.RC3
913 #define RC4 PORTC_bits.RC4
914 #define RC5 PORTC_bits.RC5
915 #define RC6 PORTC_bits.RC6
916 #define RC7 PORTC_bits.RC7
918 // ----- PORTE bits --------------------
931 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
933 #define RE0 PORTE_bits.RE0
934 #define RE1 PORTE_bits.RE1
935 #define RE2 PORTE_bits.RE2
937 // ----- RCSTA bits --------------------
940 unsigned char RX9D:1;
941 unsigned char OERR:1;
942 unsigned char FERR:1;
943 unsigned char ADDEN:1;
944 unsigned char CREN:1;
945 unsigned char SREN:1;
947 unsigned char SPEN:1;
950 unsigned char RCD8:1;
966 unsigned char NOT_RC8:1;
976 unsigned char RC8_9:1;
980 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
982 #define RX9D RCSTA_bits.RX9D
983 #define RCD8 RCSTA_bits.RCD8
984 #define OERR RCSTA_bits.OERR
985 #define FERR RCSTA_bits.FERR
986 #define ADDEN RCSTA_bits.ADDEN
987 #define CREN RCSTA_bits.CREN
988 #define SREN RCSTA_bits.SREN
989 #define RX9 RCSTA_bits.RX9
990 #define RC9 RCSTA_bits.RC9
991 #define NOT_RC8 RCSTA_bits.NOT_RC8
992 #define RC8_9 RCSTA_bits.RC8_9
993 #define SPEN RCSTA_bits.SPEN
995 // ----- SSPCON bits --------------------
998 unsigned char SSPM0:1;
999 unsigned char SSPM1:1;
1000 unsigned char SSPM2:1;
1001 unsigned char SSPM3:1;
1002 unsigned char CKP:1;
1003 unsigned char SSPEN:1;
1004 unsigned char SSPOV:1;
1005 unsigned char WCOL:1;
1008 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1010 #define SSPM0 SSPCON_bits.SSPM0
1011 #define SSPM1 SSPCON_bits.SSPM1
1012 #define SSPM2 SSPCON_bits.SSPM2
1013 #define SSPM3 SSPCON_bits.SSPM3
1014 #define CKP SSPCON_bits.CKP
1015 #define SSPEN SSPCON_bits.SSPEN
1016 #define SSPOV SSPCON_bits.SSPOV
1017 #define WCOL SSPCON_bits.WCOL
1019 // ----- SSPCON2 bits --------------------
1022 unsigned char SEN:1;
1023 unsigned char RSEN:1;
1024 unsigned char PEN:1;
1025 unsigned char RCEN:1;
1026 unsigned char ACKEN:1;
1027 unsigned char ACKDT:1;
1028 unsigned char ACKSTAT:1;
1029 unsigned char GCEN:1;
1032 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
1034 #define SEN SSPCON2_bits.SEN
1035 #define RSEN SSPCON2_bits.RSEN
1036 #define PEN SSPCON2_bits.PEN
1037 #define RCEN SSPCON2_bits.RCEN
1038 #define ACKEN SSPCON2_bits.ACKEN
1039 #define ACKDT SSPCON2_bits.ACKDT
1040 #define ACKSTAT SSPCON2_bits.ACKSTAT
1041 #define GCEN SSPCON2_bits.GCEN
1043 // ----- SSPSTAT bits --------------------
1052 unsigned char CKE:1;
1053 unsigned char SMP:1;
1058 unsigned char I2C_READ:1;
1059 unsigned char I2C_START:1;
1060 unsigned char I2C_STOP:1;
1061 unsigned char I2C_DATA:1;
1068 unsigned char NOT_W:1;
1071 unsigned char NOT_A:1;
1078 unsigned char NOT_WRITE:1;
1081 unsigned char NOT_ADDRESS:1;
1088 unsigned char R_W:1;
1091 unsigned char D_A:1;
1098 unsigned char READ_WRITE:1;
1101 unsigned char DATA_ADDRESS:1;
1106 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1108 #define BF SSPSTAT_bits.BF
1109 #define UA SSPSTAT_bits.UA
1110 #define R SSPSTAT_bits.R
1111 #define I2C_READ SSPSTAT_bits.I2C_READ
1112 #define NOT_W SSPSTAT_bits.NOT_W
1113 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1114 #define R_W SSPSTAT_bits.R_W
1115 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1116 #define S SSPSTAT_bits.S
1117 #define I2C_START SSPSTAT_bits.I2C_START
1118 #define P SSPSTAT_bits.P
1119 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1120 #define D SSPSTAT_bits.D
1121 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1122 #define NOT_A SSPSTAT_bits.NOT_A
1123 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1124 #define D_A SSPSTAT_bits.D_A
1125 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1126 #define CKE SSPSTAT_bits.CKE
1127 #define SMP SSPSTAT_bits.SMP
1129 // ----- STATUS bits --------------------
1135 unsigned char NOT_PD:1;
1136 unsigned char NOT_TO:1;
1137 unsigned char RP0:1;
1138 unsigned char RP1:1;
1139 unsigned char IRP:1;
1142 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1144 #define C STATUS_bits.C
1145 #define DC STATUS_bits.DC
1146 #define Z STATUS_bits.Z
1147 #define NOT_PD STATUS_bits.NOT_PD
1148 #define NOT_TO STATUS_bits.NOT_TO
1149 #define RP0 STATUS_bits.RP0
1150 #define RP1 STATUS_bits.RP1
1151 #define IRP STATUS_bits.IRP
1153 // ----- T1CON bits --------------------
1156 unsigned char TMR1ON:1;
1157 unsigned char TMR1CS:1;
1158 unsigned char NOT_T1SYNC:1;
1159 unsigned char T1OSCEN:1;
1160 unsigned char T1CKPS0:1;
1161 unsigned char T1CKPS1:1;
1162 unsigned char T1RUN:1;
1168 unsigned char T1INSYNC:1;
1178 unsigned char T1SYNC:1;
1186 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1188 #define TMR1ON T1CON_bits.TMR1ON
1189 #define TMR1CS T1CON_bits.TMR1CS
1190 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1191 #define T1INSYNC T1CON_bits.T1INSYNC
1192 #define T1SYNC T1CON_bits.T1SYNC
1193 #define T1OSCEN T1CON_bits.T1OSCEN
1194 #define T1CKPS0 T1CON_bits.T1CKPS0
1195 #define T1CKPS1 T1CON_bits.T1CKPS1
1196 #define T1RUN T1CON_bits.T1RUN
1198 // ----- T2CON bits --------------------
1201 unsigned char T2CKPS0:1;
1202 unsigned char T2CKPS1:1;
1203 unsigned char TMR2ON:1;
1204 unsigned char TOUTPS0:1;
1205 unsigned char TOUTPS1:1;
1206 unsigned char TOUTPS2:1;
1207 unsigned char TOUTPS3:1;
1211 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1213 #define T2CKPS0 T2CON_bits.T2CKPS0
1214 #define T2CKPS1 T2CON_bits.T2CKPS1
1215 #define TMR2ON T2CON_bits.TMR2ON
1216 #define TOUTPS0 T2CON_bits.TOUTPS0
1217 #define TOUTPS1 T2CON_bits.TOUTPS1
1218 #define TOUTPS2 T2CON_bits.TOUTPS2
1219 #define TOUTPS3 T2CON_bits.TOUTPS3
1221 // ----- TRISA bits --------------------
1224 unsigned char TRISA0:1;
1225 unsigned char TRISA1:1;
1226 unsigned char TRISA2:1;
1227 unsigned char TRISA3:1;
1228 unsigned char TRISA4:1;
1229 unsigned char TRISA5:1;
1234 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1236 #define TRISA0 TRISA_bits.TRISA0
1237 #define TRISA1 TRISA_bits.TRISA1
1238 #define TRISA2 TRISA_bits.TRISA2
1239 #define TRISA3 TRISA_bits.TRISA3
1240 #define TRISA4 TRISA_bits.TRISA4
1241 #define TRISA5 TRISA_bits.TRISA5
1243 // ----- TRISB bits --------------------
1246 unsigned char TRISB0:1;
1247 unsigned char TRISB1:1;
1248 unsigned char TRISB2:1;
1249 unsigned char TRISB3:1;
1250 unsigned char TRISB4:1;
1251 unsigned char TRISB5:1;
1252 unsigned char TRISB6:1;
1253 unsigned char TRISB7:1;
1256 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1258 #define TRISB0 TRISB_bits.TRISB0
1259 #define TRISB1 TRISB_bits.TRISB1
1260 #define TRISB2 TRISB_bits.TRISB2
1261 #define TRISB3 TRISB_bits.TRISB3
1262 #define TRISB4 TRISB_bits.TRISB4
1263 #define TRISB5 TRISB_bits.TRISB5
1264 #define TRISB6 TRISB_bits.TRISB6
1265 #define TRISB7 TRISB_bits.TRISB7
1267 // ----- TRISC bits --------------------
1270 unsigned char TRISC0:1;
1271 unsigned char TRISC1:1;
1272 unsigned char TRISC2:1;
1273 unsigned char TRISC3:1;
1274 unsigned char TRISC4:1;
1275 unsigned char TRISC5:1;
1276 unsigned char TRISC6:1;
1277 unsigned char TRISC7:1;
1280 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1282 #define TRISC0 TRISC_bits.TRISC0
1283 #define TRISC1 TRISC_bits.TRISC1
1284 #define TRISC2 TRISC_bits.TRISC2
1285 #define TRISC3 TRISC_bits.TRISC3
1286 #define TRISC4 TRISC_bits.TRISC4
1287 #define TRISC5 TRISC_bits.TRISC5
1288 #define TRISC6 TRISC_bits.TRISC6
1289 #define TRISC7 TRISC_bits.TRISC7
1291 // ----- TRISE bits --------------------
1294 unsigned char TRISE0:1;
1295 unsigned char TRISE1:1;
1296 unsigned char TRISE2:1;
1297 unsigned char TRISE3:1;
1298 unsigned char PSPMODE:1;
1299 unsigned char IBOV:1;
1300 unsigned char OBF:1;
1301 unsigned char IBF:1;
1304 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1306 #define TRISE0 TRISE_bits.TRISE0
1307 #define TRISE1 TRISE_bits.TRISE1
1308 #define TRISE2 TRISE_bits.TRISE2
1309 #define TRISE3 TRISE_bits.TRISE3
1310 #define PSPMODE TRISE_bits.PSPMODE
1311 #define IBOV TRISE_bits.IBOV
1312 #define OBF TRISE_bits.OBF
1313 #define IBF TRISE_bits.IBF
1315 // ----- TXSTA bits --------------------
1318 unsigned char TX9D:1;
1319 unsigned char TRMT:1;
1320 unsigned char BRGH:1;
1322 unsigned char SYNC:1;
1323 unsigned char TXEN:1;
1324 unsigned char TX9:1;
1325 unsigned char CSRC:1;
1328 unsigned char TXD8:1;
1334 unsigned char NOT_TX8:1;
1344 unsigned char TX8_9:1;
1348 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1350 #define TX9D TXSTA_bits.TX9D
1351 #define TXD8 TXSTA_bits.TXD8
1352 #define TRMT TXSTA_bits.TRMT
1353 #define BRGH TXSTA_bits.BRGH
1354 #define SYNC TXSTA_bits.SYNC
1355 #define TXEN TXSTA_bits.TXEN
1356 #define TX9 TXSTA_bits.TX9
1357 #define NOT_TX8 TXSTA_bits.NOT_TX8
1358 #define TX8_9 TXSTA_bits.TX8_9
1359 #define CSRC TXSTA_bits.CSRC
1361 // ----- WDTCON bits --------------------
1364 unsigned char SWDTEN:1;
1365 unsigned char WDTPS0:1;
1366 unsigned char WDTPS1:1;
1367 unsigned char WDTPS2:1;
1368 unsigned char WDTPS3:1;
1374 unsigned char SWDTE:1;
1384 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1386 #define SWDTEN WDTCON_bits.SWDTEN
1387 #define SWDTE WDTCON_bits.SWDTE
1388 #define WDTPS0 WDTCON_bits.WDTPS0
1389 #define WDTPS1 WDTCON_bits.WDTPS1
1390 #define WDTPS2 WDTCON_bits.WDTPS2
1391 #define WDTPS3 WDTCON_bits.WDTPS3