2 // Register Declarations for Microchip 16F767 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTE_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define PIR1_ADDR 0x000C
40 #define PIR2_ADDR 0x000D
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define RCSTA_ADDR 0x0018
52 #define TXREG_ADDR 0x0019
53 #define RCREG_ADDR 0x001A
54 #define CCPR2L_ADDR 0x001B
55 #define CCPR2H_ADDR 0x001C
56 #define CCP2CON_ADDR 0x001D
57 #define ADRESH_ADDR 0x001E
58 #define ADCON0_ADDR 0x001F
59 #define OPTION_REG_ADDR 0x0081
60 #define TRISA_ADDR 0x0085
61 #define TRISB_ADDR 0x0086
62 #define TRISC_ADDR 0x0087
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define OSCCON_ADDR 0x008F
68 #define OSCTUNE_ADDR 0x0090
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define CCPR3L_ADDR 0x0095
74 #define CCPR3H_ADDR 0x0096
75 #define CCP3CON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define ADCON2_ADDR 0x009B
79 #define CMCON_ADDR 0x009C
80 #define CVRCON_ADDR 0x009D
81 #define ADRESL_ADDR 0x009E
82 #define ADCON1_ADDR 0x009F
83 #define WDTCON_ADDR 0x0105
84 #define LVDCON_ADDR 0x0109
85 #define PMDATA_ADDR 0x010C
86 #define PMADR_ADDR 0x010D
87 #define PMDATH_ADDR 0x010E
88 #define PMADRH_ADDR 0x010F
89 #define PMCON1_ADDR 0x018C
92 // Memory organization.
95 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
96 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
97 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
98 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
99 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
100 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
101 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
102 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
103 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
104 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
105 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
106 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
107 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
108 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
109 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
110 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
111 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
112 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
113 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
114 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
115 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
116 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
117 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
118 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
119 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
120 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
121 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
122 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
123 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
124 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
125 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
126 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
127 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
128 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
129 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
130 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
131 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
132 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
133 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
134 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
135 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
136 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
137 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
138 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
139 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
140 #pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L
141 #pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H
142 #pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON
143 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
144 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
145 #pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2
146 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
147 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
148 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
149 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
150 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
151 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
152 #pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
153 #pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
154 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
155 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
156 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
160 // P16F767.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
163 // This header file defines configurations, registers, and other useful bits of
164 // information for the PIC16F767 microcontroller. These names are taken to match
165 // the data sheets as closely as possible.
167 // Note that the processor must be selected before this file is
168 // included. The processor may be selected the following ways:
170 // 1. Command line switch:
171 // C:\ MPASM MYFILE.ASM /PIC16F767
172 // 2. LIST directive in the source file
174 // 3. Processor Type entry in the MPASM full-screen interface
176 //==========================================================================
180 //==========================================================================
183 //1.00 05/05/03 Initial Release
184 //1.01 10/21/03 Made changes to Program Memory register names.
185 //1.02 04/07/04 Added INT0IE & INT0IF bit names.
187 //==========================================================================
191 //==========================================================================
194 // MESSG "Processor-header file mismatch. Verify selected processor."
197 //==========================================================================
199 // Register Definitions
201 //==========================================================================
206 //----- Register Files------------------------------------------------------
208 extern data __at (INDF_ADDR) volatile char INDF;
209 extern sfr __at (TMR0_ADDR) TMR0;
210 extern data __at (PCL_ADDR) volatile char PCL;
211 extern sfr __at (STATUS_ADDR) STATUS;
212 extern sfr __at (FSR_ADDR) FSR;
213 extern sfr __at (PORTA_ADDR) PORTA;
214 extern sfr __at (PORTB_ADDR) PORTB;
215 extern sfr __at (PORTC_ADDR) PORTC;
216 extern sfr __at (PORTE_ADDR) PORTE;
217 extern sfr __at (PCLATH_ADDR) PCLATH;
218 extern sfr __at (INTCON_ADDR) INTCON;
219 extern sfr __at (PIR1_ADDR) PIR1;
220 extern sfr __at (PIR2_ADDR) PIR2;
221 extern sfr __at (TMR1L_ADDR) TMR1L;
222 extern sfr __at (TMR1H_ADDR) TMR1H;
223 extern sfr __at (T1CON_ADDR) T1CON;
224 extern sfr __at (TMR2_ADDR) TMR2;
225 extern sfr __at (T2CON_ADDR) T2CON;
226 extern sfr __at (SSPBUF_ADDR) SSPBUF;
227 extern sfr __at (SSPCON_ADDR) SSPCON;
228 extern sfr __at (CCPR1L_ADDR) CCPR1L;
229 extern sfr __at (CCPR1H_ADDR) CCPR1H;
230 extern sfr __at (CCP1CON_ADDR) CCP1CON;
231 extern sfr __at (RCSTA_ADDR) RCSTA;
232 extern sfr __at (TXREG_ADDR) TXREG;
233 extern sfr __at (RCREG_ADDR) RCREG;
234 extern sfr __at (CCPR2L_ADDR) CCPR2L;
235 extern sfr __at (CCPR2H_ADDR) CCPR2H;
236 extern sfr __at (CCP2CON_ADDR) CCP2CON;
237 extern sfr __at (ADRESH_ADDR) ADRESH;
238 extern sfr __at (ADCON0_ADDR) ADCON0;
240 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
241 extern sfr __at (TRISA_ADDR) TRISA;
242 extern sfr __at (TRISB_ADDR) TRISB;
243 extern sfr __at (TRISC_ADDR) TRISC;
244 extern sfr __at (TRISE_ADDR) TRISE;
245 extern sfr __at (PIE1_ADDR) PIE1;
246 extern sfr __at (PIE2_ADDR) PIE2;
247 extern sfr __at (PCON_ADDR) PCON;
248 extern sfr __at (OSCCON_ADDR) OSCCON;
249 extern sfr __at (OSCTUNE_ADDR) OSCTUNE;
250 extern sfr __at (SSPCON2_ADDR) SSPCON2;
251 extern sfr __at (PR2_ADDR) PR2;
252 extern sfr __at (SSPADD_ADDR) SSPADD;
253 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
254 extern sfr __at (CCPR3L_ADDR) CCPR3L;
255 extern sfr __at (CCPR3H_ADDR) CCPR3H;
256 extern sfr __at (CCP3CON_ADDR) CCP3CON;
257 extern sfr __at (TXSTA_ADDR) TXSTA;
258 extern sfr __at (SPBRG_ADDR) SPBRG;
259 extern sfr __at (ADCON2_ADDR) ADCON2;
260 extern sfr __at (CMCON_ADDR) CMCON;
261 extern sfr __at (CVRCON_ADDR) CVRCON;
262 extern sfr __at (ADRESL_ADDR) ADRESL;
263 extern sfr __at (ADCON1_ADDR) ADCON1;
265 extern sfr __at (WDTCON_ADDR) WDTCON;
266 extern sfr __at (LVDCON_ADDR) LVDCON;
267 extern sfr __at (PMDATA_ADDR) PMDATA;
268 extern sfr __at (PMADR_ADDR) PMADR;
269 extern sfr __at (PMDATH_ADDR) PMDATH;
270 extern sfr __at (PMADRH_ADDR) PMADRH;
272 extern sfr __at (PMCON1_ADDR) PMCON1;
274 //----- STATUS Bits --------------------------------------------------------
277 //----- INTCON Bits --------------------------------------------------------
280 //----- PIR1 Bits ----------------------------------------------------------
283 //----- PIR2 Bits ----------------------------------------------------------
286 //----- T1CON Bits ---------------------------------------------------------
289 //----- T2CON Bits ---------------------------------------------------------
292 //----- SSPCON Bits --------------------------------------------------------
295 //----- CCP1CON Bits -------------------------------------------------------
298 //----- RCSTA Bits ---------------------------------------------------------
301 //----- CCP2CON Bits -------------------------------------------------------
304 //----- ADCON0 Bits --------------------------------------------------------
307 //----- OPTION Bits -----------------------------------------------------
310 //----- TRISE Bits ---------------------------------------------------------
313 //----- PIE1 Bits ----------------------------------------------------------
316 //----- PIE2 Bits ----------------------------------------------------------
319 //----- PCON Bits ----------------------------------------------------------
322 //----- OSCCON Bits -------------------------------------------------------
324 //----- OSCTUNE Bits -------------------------------------------------------
326 //----- SSPCON2 Bits --------------------------------------------------------
329 //----- SSPSTAT Bits -------------------------------------------------------
332 //----- CCP3CON Bits -------------------------------------------------------
335 //----- TXSTA Bits ---------------------------------------------------------
338 //----- ADCON2 Bits ---------------------------------------------------------
341 //----- CMCON Bits ---------------------------------------------------------
344 //----- CVRCON Bits --------------------------------------------------------
347 //----- ADCON1 Bits --------------------------------------------------------
350 //----- WDTCON Bits --------------------------------------------------------
353 //----- LVDCON Bits --------------------------------------------------------
356 //----- PMCON1 Bits --------------------------------------------------------
360 //==========================================================================
364 //==========================================================================
368 // __BADRAM H'88', H'9A'
369 // __BADRAM H'107'-H'108'
370 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
372 //==========================================================================
374 // Configuration Bits
376 //==========================================================================
378 #define _CONFIG1 0x2007
379 #define _CONFIG2 0x2008
381 //Configuration Byte 1 Options
382 #define _CP_ALL 0x1FFF
383 #define _CP_OFF 0x3FFF
384 #define _CCP2_RC1 0x3FFF
385 #define _CCP2_RB3 0x2FFF
386 #define _DEBUG_OFF 0x3FFF
387 #define _DEBUG_ON 0x37FF
388 #define _VBOR_2_0 0x3FFF
389 #define _VBOR_2_7 0x3F7F
390 #define _VBOR_4_2 0x3EFF
391 #define _VBOR_4_5 0x3E7F
392 #define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
393 #define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
394 #define _MCLR_ON 0x3FFF
395 #define _MCLR_OFF 0x3FDF
396 #define _PWRTE_OFF 0x3FFF
397 #define _PWRTE_ON 0x3FF7
398 #define _WDT_ON 0x3FFF
399 #define _WDT_OFF 0x3FFB
400 #define _EXTRC_CLKOUT 0x3FFF
401 #define _EXTRC_IO 0x3FFE
402 #define _INTRC_CLKOUT 0x3FFD
403 #define _INTRC_IO 0x3FFC
404 #define _EXTCLK 0x3FEF
405 #define _HS_OSC 0x3FEE
406 #define _XT_OSC 0x3FED
407 #define _LP_OSC 0x3FEC
409 //Configuration Byte 2 Options
410 #define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
411 #define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
412 #define _IESO_ON 0x3FFF
413 #define _IESO_OFF 0x3FFD
414 #define _FCMEN_ON 0x3FFF
415 #define _FCMEN_OFF 0x3FFE
418 //**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details)
419 //BOREN_1 & BORSEN_1 = BOR enabled and always on
420 //BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware
421 //BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2)
422 //BOREN_0 & BORSEN_0 = BOR disabled
425 // To use the Configuration Bits, place the following lines in your source code
426 // in the following format, and change the configuration value to the desired
427 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
428 // and each __CONFIG line should have the preceding semicolon removed when
429 // pasted into your source code.
431 //Program Configuration Register 1
432 // __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
434 //Program Configuration Register 2
435 // __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF
440 // ----- ADCON0 bits --------------------
443 unsigned char ADON:1;
444 unsigned char CHS3:1;
446 unsigned char CHS0:1;
447 unsigned char CHS1:1;
448 unsigned char CHS2:1;
449 unsigned char ADCS0:1;
450 unsigned char ADCS1:1;
455 unsigned char NOT_DONE:1;
465 unsigned char GO_DONE:1;
473 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
475 #define ADON ADCON0_bits.ADON
476 #define CHS3 ADCON0_bits.CHS3
477 #define GO ADCON0_bits.GO
478 #define NOT_DONE ADCON0_bits.NOT_DONE
479 #define GO_DONE ADCON0_bits.GO_DONE
480 #define CHS0 ADCON0_bits.CHS0
481 #define CHS1 ADCON0_bits.CHS1
482 #define CHS2 ADCON0_bits.CHS2
483 #define ADCS0 ADCON0_bits.ADCS0
484 #define ADCS1 ADCON0_bits.ADCS1
486 // ----- ADCON1 bits --------------------
489 unsigned char PCFG0:1;
490 unsigned char PCFG1:1;
491 unsigned char PCFG2:1;
492 unsigned char PCFG3:1;
493 unsigned char VCFG0:1;
494 unsigned char VCFG1:1;
495 unsigned char ADCS2:1;
496 unsigned char ADFM:1;
499 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
501 #define PCFG0 ADCON1_bits.PCFG0
502 #define PCFG1 ADCON1_bits.PCFG1
503 #define PCFG2 ADCON1_bits.PCFG2
504 #define PCFG3 ADCON1_bits.PCFG3
505 #define VCFG0 ADCON1_bits.VCFG0
506 #define VCFG1 ADCON1_bits.VCFG1
507 #define ADCS2 ADCON1_bits.ADCS2
508 #define ADFM ADCON1_bits.ADFM
510 // ----- ADCON2 bits --------------------
516 unsigned char ACQT0:1;
517 unsigned char ACQT1:1;
518 unsigned char ACQT2:1;
523 extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits;
525 #define ACQT0 ADCON2_bits.ACQT0
526 #define ACQT1 ADCON2_bits.ACQT1
527 #define ACQT2 ADCON2_bits.ACQT2
529 // ----- CCP1CON bits --------------------
532 unsigned char CCP1M0:1;
533 unsigned char CCP1M1:1;
534 unsigned char CCP1M2:1;
535 unsigned char CCP1M3:1;
536 unsigned char CCP1Y:1;
537 unsigned char CCP1X:1;
542 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
544 #define CCP1M0 CCP1CON_bits.CCP1M0
545 #define CCP1M1 CCP1CON_bits.CCP1M1
546 #define CCP1M2 CCP1CON_bits.CCP1M2
547 #define CCP1M3 CCP1CON_bits.CCP1M3
548 #define CCP1Y CCP1CON_bits.CCP1Y
549 #define CCP1X CCP1CON_bits.CCP1X
551 // ----- CCP2CON bits --------------------
554 unsigned char CCP2M0:1;
555 unsigned char CCP2M1:1;
556 unsigned char CCP2M2:1;
557 unsigned char CCP2M3:1;
558 unsigned char CCP2Y:1;
559 unsigned char CCP2X:1;
564 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
566 #define CCP2M0 CCP2CON_bits.CCP2M0
567 #define CCP2M1 CCP2CON_bits.CCP2M1
568 #define CCP2M2 CCP2CON_bits.CCP2M2
569 #define CCP2M3 CCP2CON_bits.CCP2M3
570 #define CCP2Y CCP2CON_bits.CCP2Y
571 #define CCP2X CCP2CON_bits.CCP2X
573 // ----- CCP3CON bits --------------------
576 unsigned char CCP3M0:1;
577 unsigned char CCP3M1:1;
578 unsigned char CCP3M2:1;
579 unsigned char CCP3M3:1;
580 unsigned char CCP3Y:1;
581 unsigned char CCP3X:1;
586 extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits;
588 #define CCP3M0 CCP3CON_bits.CCP3M0
589 #define CCP3M1 CCP3CON_bits.CCP3M1
590 #define CCP3M2 CCP3CON_bits.CCP3M2
591 #define CCP3M3 CCP3CON_bits.CCP3M3
592 #define CCP3Y CCP3CON_bits.CCP3Y
593 #define CCP3X CCP3CON_bits.CCP3X
595 // ----- CMCON bits --------------------
602 unsigned char C1INV:1;
603 unsigned char C2INV:1;
604 unsigned char C1OUT:1;
605 unsigned char C2OUT:1;
608 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
610 #define CM0 CMCON_bits.CM0
611 #define CM1 CMCON_bits.CM1
612 #define CM2 CMCON_bits.CM2
613 #define CIS CMCON_bits.CIS
614 #define C1INV CMCON_bits.C1INV
615 #define C2INV CMCON_bits.C2INV
616 #define C1OUT CMCON_bits.C1OUT
617 #define C2OUT CMCON_bits.C2OUT
619 // ----- CVRCON bits --------------------
622 unsigned char CVR0:1;
623 unsigned char CVR1:1;
624 unsigned char CVR2:1;
625 unsigned char CVR3:1;
627 unsigned char CVRR:1;
628 unsigned char CVROE:1;
629 unsigned char CVREN:1;
632 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
634 #define CVR0 CVRCON_bits.CVR0
635 #define CVR1 CVRCON_bits.CVR1
636 #define CVR2 CVRCON_bits.CVR2
637 #define CVR3 CVRCON_bits.CVR3
638 #define CVRR CVRCON_bits.CVRR
639 #define CVROE CVRCON_bits.CVROE
640 #define CVREN CVRCON_bits.CVREN
642 // ----- INTCON bits --------------------
645 unsigned char RBIF:1;
646 unsigned char INTF:1;
647 unsigned char T0IF:1;
648 unsigned char RBIE:1;
649 unsigned char INTE:1;
650 unsigned char T0IE:1;
651 unsigned char PEIE:1;
656 unsigned char INT0IF:1;
657 unsigned char TMR0IF:1;
659 unsigned char INT0IE:1;
660 unsigned char TMR0IE:1;
665 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
667 #define RBIF INTCON_bits.RBIF
668 #define INTF INTCON_bits.INTF
669 #define INT0IF INTCON_bits.INT0IF
670 #define T0IF INTCON_bits.T0IF
671 #define TMR0IF INTCON_bits.TMR0IF
672 #define RBIE INTCON_bits.RBIE
673 #define INTE INTCON_bits.INTE
674 #define INT0IE INTCON_bits.INT0IE
675 #define T0IE INTCON_bits.T0IE
676 #define TMR0IE INTCON_bits.TMR0IE
677 #define PEIE INTCON_bits.PEIE
678 #define GIE INTCON_bits.GIE
680 // ----- LVDCON bits --------------------
683 unsigned char LVDL0:1;
684 unsigned char LVDL1:1;
685 unsigned char LVDL2:1;
686 unsigned char LVDL3:1;
687 unsigned char LVDEN:1;
688 unsigned char IRVST:1;
693 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
695 #define LVDL0 LVDCON_bits.LVDL0
696 #define LVDL1 LVDCON_bits.LVDL1
697 #define LVDL2 LVDCON_bits.LVDL2
698 #define LVDL3 LVDCON_bits.LVDL3
699 #define LVDEN LVDCON_bits.LVDEN
700 #define IRVST LVDCON_bits.IRVST
702 // ----- OPTION_REG bits --------------------
709 unsigned char T0SE:1;
710 unsigned char T0CS:1;
711 unsigned char INTEDG:1;
712 unsigned char NOT_RBPU:1;
714 } __OPTION_REG_bits_t;
715 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
717 #define PS0 OPTION_REG_bits.PS0
718 #define PS1 OPTION_REG_bits.PS1
719 #define PS2 OPTION_REG_bits.PS2
720 #define PSA OPTION_REG_bits.PSA
721 #define T0SE OPTION_REG_bits.T0SE
722 #define T0CS OPTION_REG_bits.T0CS
723 #define INTEDG OPTION_REG_bits.INTEDG
724 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
726 // ----- OSCCON bits --------------------
729 unsigned char SCS0:1;
730 unsigned char SCS1:1;
731 unsigned char IOFS:1;
732 unsigned char OSTS:1;
733 unsigned char IRCF0:1;
734 unsigned char IRCF1:1;
735 unsigned char IRCF2:1;
739 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
741 #define SCS0 OSCCON_bits.SCS0
742 #define SCS1 OSCCON_bits.SCS1
743 #define IOFS OSCCON_bits.IOFS
744 #define OSTS OSCCON_bits.OSTS
745 #define IRCF0 OSCCON_bits.IRCF0
746 #define IRCF1 OSCCON_bits.IRCF1
747 #define IRCF2 OSCCON_bits.IRCF2
749 // ----- OSCTUNE bits --------------------
752 unsigned char TUN0:1;
753 unsigned char TUN1:1;
754 unsigned char TUN2:1;
755 unsigned char TUN3:1;
756 unsigned char TUN4:1;
757 unsigned char TUN5:1;
762 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
764 #define TUN0 OSCTUNE_bits.TUN0
765 #define TUN1 OSCTUNE_bits.TUN1
766 #define TUN2 OSCTUNE_bits.TUN2
767 #define TUN3 OSCTUNE_bits.TUN3
768 #define TUN4 OSCTUNE_bits.TUN4
769 #define TUN5 OSCTUNE_bits.TUN5
771 // ----- PCON bits --------------------
774 unsigned char NOT_BO:1;
775 unsigned char NOT_POR:1;
776 unsigned char SBOREN:1;
784 unsigned char NOT_BOR:1;
794 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
796 #define NOT_BO PCON_bits.NOT_BO
797 #define NOT_BOR PCON_bits.NOT_BOR
798 #define NOT_POR PCON_bits.NOT_POR
799 #define SBOREN PCON_bits.SBOREN
801 // ----- PIE1 bits --------------------
804 unsigned char TMR1IE:1;
805 unsigned char TMR2IE:1;
806 unsigned char CCP1IE:1;
807 unsigned char SSPIE:1;
808 unsigned char TXIE:1;
809 unsigned char RCIE:1;
810 unsigned char ADIE:1;
811 unsigned char PSPIE:1;
814 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
816 #define TMR1IE PIE1_bits.TMR1IE
817 #define TMR2IE PIE1_bits.TMR2IE
818 #define CCP1IE PIE1_bits.CCP1IE
819 #define SSPIE PIE1_bits.SSPIE
820 #define TXIE PIE1_bits.TXIE
821 #define RCIE PIE1_bits.RCIE
822 #define ADIE PIE1_bits.ADIE
823 #define PSPIE PIE1_bits.PSPIE
825 // ----- PIE2 bits --------------------
828 unsigned char CCP2IE:1;
829 unsigned char CCP3IE:1;
831 unsigned char BCLIE:1;
833 unsigned char LVDIE:1;
834 unsigned char CMIE:1;
835 unsigned char OSFIE:1;
838 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
840 #define CCP2IE PIE2_bits.CCP2IE
841 #define CCP3IE PIE2_bits.CCP3IE
842 #define BCLIE PIE2_bits.BCLIE
843 #define LVDIE PIE2_bits.LVDIE
844 #define CMIE PIE2_bits.CMIE
845 #define OSFIE PIE2_bits.OSFIE
847 // ----- PIR1 bits --------------------
850 unsigned char TMR1IF:1;
851 unsigned char TMR2IF:1;
852 unsigned char CCP1IF:1;
853 unsigned char SSPIF:1;
854 unsigned char TXIF:1;
855 unsigned char RCIF:1;
856 unsigned char ADIF:1;
857 unsigned char PSPIF:1;
860 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
862 #define TMR1IF PIR1_bits.TMR1IF
863 #define TMR2IF PIR1_bits.TMR2IF
864 #define CCP1IF PIR1_bits.CCP1IF
865 #define SSPIF PIR1_bits.SSPIF
866 #define TXIF PIR1_bits.TXIF
867 #define RCIF PIR1_bits.RCIF
868 #define ADIF PIR1_bits.ADIF
869 #define PSPIF PIR1_bits.PSPIF
871 // ----- PIR2 bits --------------------
874 unsigned char CCP2IF:1;
875 unsigned char CCP3IF:1;
877 unsigned char BCLIF:1;
879 unsigned char LVDIF:1;
880 unsigned char CMIF:1;
881 unsigned char OSFIF:1;
884 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
886 #define CCP2IF PIR2_bits.CCP2IF
887 #define CCP3IF PIR2_bits.CCP3IF
888 #define BCLIF PIR2_bits.BCLIF
889 #define LVDIF PIR2_bits.LVDIF
890 #define CMIF PIR2_bits.CMIF
891 #define OSFIF PIR2_bits.OSFIF
893 // ----- PMCON1 bits --------------------
906 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
908 #define RD PMCON1_bits.RD
910 // ----- RCSTA bits --------------------
913 unsigned char RX9D:1;
914 unsigned char OERR:1;
915 unsigned char FERR:1;
916 unsigned char ADDEN:1;
917 unsigned char CREN:1;
918 unsigned char SREN:1;
920 unsigned char SPEN:1;
923 unsigned char RCD8:1;
939 unsigned char NOT_RC8:1;
949 unsigned char RC8_9:1;
953 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
955 #define RX9D RCSTA_bits.RX9D
956 #define RCD8 RCSTA_bits.RCD8
957 #define OERR RCSTA_bits.OERR
958 #define FERR RCSTA_bits.FERR
959 #define ADDEN RCSTA_bits.ADDEN
960 #define CREN RCSTA_bits.CREN
961 #define SREN RCSTA_bits.SREN
962 #define RX9 RCSTA_bits.RX9
963 #define RC9 RCSTA_bits.RC9
964 #define NOT_RC8 RCSTA_bits.NOT_RC8
965 #define RC8_9 RCSTA_bits.RC8_9
966 #define SPEN RCSTA_bits.SPEN
968 // ----- SSPCON bits --------------------
971 unsigned char SSPM0:1;
972 unsigned char SSPM1:1;
973 unsigned char SSPM2:1;
974 unsigned char SSPM3:1;
976 unsigned char SSPEN:1;
977 unsigned char SSPOV:1;
978 unsigned char WCOL:1;
981 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
983 #define SSPM0 SSPCON_bits.SSPM0
984 #define SSPM1 SSPCON_bits.SSPM1
985 #define SSPM2 SSPCON_bits.SSPM2
986 #define SSPM3 SSPCON_bits.SSPM3
987 #define CKP SSPCON_bits.CKP
988 #define SSPEN SSPCON_bits.SSPEN
989 #define SSPOV SSPCON_bits.SSPOV
990 #define WCOL SSPCON_bits.WCOL
992 // ----- SSPCON2 bits --------------------
996 unsigned char RSEN:1;
998 unsigned char RCEN:1;
999 unsigned char ACKEN:1;
1000 unsigned char ACKDT:1;
1001 unsigned char ACKSTAT:1;
1002 unsigned char GCEN:1;
1005 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
1007 #define SEN SSPCON2_bits.SEN
1008 #define RSEN SSPCON2_bits.RSEN
1009 #define PEN SSPCON2_bits.PEN
1010 #define RCEN SSPCON2_bits.RCEN
1011 #define ACKEN SSPCON2_bits.ACKEN
1012 #define ACKDT SSPCON2_bits.ACKDT
1013 #define ACKSTAT SSPCON2_bits.ACKSTAT
1014 #define GCEN SSPCON2_bits.GCEN
1016 // ----- SSPSTAT bits --------------------
1025 unsigned char CKE:1;
1026 unsigned char SMP:1;
1031 unsigned char I2C_READ:1;
1032 unsigned char I2C_START:1;
1033 unsigned char I2C_STOP:1;
1034 unsigned char I2C_DATA:1;
1041 unsigned char NOT_W:1;
1044 unsigned char NOT_A:1;
1051 unsigned char NOT_WRITE:1;
1054 unsigned char NOT_ADDRESS:1;
1061 unsigned char R_W:1;
1064 unsigned char D_A:1;
1071 unsigned char READ_WRITE:1;
1074 unsigned char DATA_ADDRESS:1;
1079 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1081 #define BF SSPSTAT_bits.BF
1082 #define UA SSPSTAT_bits.UA
1083 #define R SSPSTAT_bits.R
1084 #define I2C_READ SSPSTAT_bits.I2C_READ
1085 #define NOT_W SSPSTAT_bits.NOT_W
1086 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1087 #define R_W SSPSTAT_bits.R_W
1088 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1089 #define S SSPSTAT_bits.S
1090 #define I2C_START SSPSTAT_bits.I2C_START
1091 #define P SSPSTAT_bits.P
1092 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1093 #define D SSPSTAT_bits.D
1094 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1095 #define NOT_A SSPSTAT_bits.NOT_A
1096 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1097 #define D_A SSPSTAT_bits.D_A
1098 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1099 #define CKE SSPSTAT_bits.CKE
1100 #define SMP SSPSTAT_bits.SMP
1102 // ----- STATUS bits --------------------
1108 unsigned char NOT_PD:1;
1109 unsigned char NOT_TO:1;
1110 unsigned char RP0:1;
1111 unsigned char RP1:1;
1112 unsigned char IRP:1;
1115 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1117 #define C STATUS_bits.C
1118 #define DC STATUS_bits.DC
1119 #define Z STATUS_bits.Z
1120 #define NOT_PD STATUS_bits.NOT_PD
1121 #define NOT_TO STATUS_bits.NOT_TO
1122 #define RP0 STATUS_bits.RP0
1123 #define RP1 STATUS_bits.RP1
1124 #define IRP STATUS_bits.IRP
1126 // ----- T1CON bits --------------------
1129 unsigned char TMR1ON:1;
1130 unsigned char TMR1CS:1;
1131 unsigned char NOT_T1SYNC:1;
1132 unsigned char T1OSCEN:1;
1133 unsigned char T1CKPS0:1;
1134 unsigned char T1CKPS1:1;
1135 unsigned char T1RUN:1;
1141 unsigned char T1INSYNC:1;
1151 unsigned char T1SYNC:1;
1159 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1161 #define TMR1ON T1CON_bits.TMR1ON
1162 #define TMR1CS T1CON_bits.TMR1CS
1163 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1164 #define T1INSYNC T1CON_bits.T1INSYNC
1165 #define T1SYNC T1CON_bits.T1SYNC
1166 #define T1OSCEN T1CON_bits.T1OSCEN
1167 #define T1CKPS0 T1CON_bits.T1CKPS0
1168 #define T1CKPS1 T1CON_bits.T1CKPS1
1169 #define T1RUN T1CON_bits.T1RUN
1171 // ----- T2CON bits --------------------
1174 unsigned char T2CKPS0:1;
1175 unsigned char T2CKPS1:1;
1176 unsigned char TMR2ON:1;
1177 unsigned char TOUTPS0:1;
1178 unsigned char TOUTPS1:1;
1179 unsigned char TOUTPS2:1;
1180 unsigned char TOUTPS3:1;
1184 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1186 #define T2CKPS0 T2CON_bits.T2CKPS0
1187 #define T2CKPS1 T2CON_bits.T2CKPS1
1188 #define TMR2ON T2CON_bits.TMR2ON
1189 #define TOUTPS0 T2CON_bits.TOUTPS0
1190 #define TOUTPS1 T2CON_bits.TOUTPS1
1191 #define TOUTPS2 T2CON_bits.TOUTPS2
1192 #define TOUTPS3 T2CON_bits.TOUTPS3
1194 // ----- TRISE bits --------------------
1197 unsigned char TRISE0:1;
1198 unsigned char TRISE1:1;
1199 unsigned char TRISE2:1;
1200 unsigned char TRISE3:1;
1201 unsigned char PSPMODE:1;
1202 unsigned char IBOV:1;
1203 unsigned char OBF:1;
1204 unsigned char IBF:1;
1207 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1209 #define TRISE0 TRISE_bits.TRISE0
1210 #define TRISE1 TRISE_bits.TRISE1
1211 #define TRISE2 TRISE_bits.TRISE2
1212 #define TRISE3 TRISE_bits.TRISE3
1213 #define PSPMODE TRISE_bits.PSPMODE
1214 #define IBOV TRISE_bits.IBOV
1215 #define OBF TRISE_bits.OBF
1216 #define IBF TRISE_bits.IBF
1218 // ----- TXSTA bits --------------------
1221 unsigned char TX9D:1;
1222 unsigned char TRMT:1;
1223 unsigned char BRGH:1;
1225 unsigned char SYNC:1;
1226 unsigned char TXEN:1;
1227 unsigned char TX9:1;
1228 unsigned char CSRC:1;
1231 unsigned char TXD8:1;
1237 unsigned char NOT_TX8:1;
1247 unsigned char TX8_9:1;
1251 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1253 #define TX9D TXSTA_bits.TX9D
1254 #define TXD8 TXSTA_bits.TXD8
1255 #define TRMT TXSTA_bits.TRMT
1256 #define BRGH TXSTA_bits.BRGH
1257 #define SYNC TXSTA_bits.SYNC
1258 #define TXEN TXSTA_bits.TXEN
1259 #define TX9 TXSTA_bits.TX9
1260 #define NOT_TX8 TXSTA_bits.NOT_TX8
1261 #define TX8_9 TXSTA_bits.TX8_9
1262 #define CSRC TXSTA_bits.CSRC
1264 // ----- WDTCON bits --------------------
1267 unsigned char SWDTEN:1;
1268 unsigned char WDTPS0:1;
1269 unsigned char WDTPS1:1;
1270 unsigned char WDTPS2:1;
1271 unsigned char WDTPS3:1;
1277 unsigned char SWDTE:1;
1287 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1289 #define SWDTEN WDTCON_bits.SWDTEN
1290 #define SWDTE WDTCON_bits.SWDTE
1291 #define WDTPS0 WDTCON_bits.WDTPS0
1292 #define WDTPS1 WDTCON_bits.WDTPS1
1293 #define WDTPS2 WDTCON_bits.WDTPS2
1294 #define WDTPS3 WDTCON_bits.WDTPS3