2 // Register Declarations for Microchip 16F76 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define SSPADD_ADDR 0x0093
67 #define SSPSTAT_ADDR 0x0094
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
71 #define PMDATA_ADDR 0x010C
72 #define PMADR_ADDR 0x010D
73 #define PMDATH_ADDR 0x010E
74 #define PMADRH_ADDR 0x010F
75 #define PMCON1_ADDR 0x018C
78 // Memory organization.
84 // P16F76.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
87 // This header file defines configurations, registers, and other useful bits of
88 // information for the PIC16F76 microcontroller. These names are taken to match
89 // the data sheets as closely as possible.
91 // Note that the processor must be selected before this file is
92 // included. The processor may be selected the following ways:
94 // 1. Command line switch:
95 // C:\ MPASM MYFILE.ASM /PIC16F76
96 // 2. LIST directive in the source file
98 // 3. Processor Type entry in the MPASM full-screen interface
100 //==========================================================================
104 //==========================================================================
108 //1.00 00/00/00 Initial Release
110 //==========================================================================
114 //==========================================================================
117 // MESSG "Processor-header file mismatch. Verify selected processor."
120 //==========================================================================
122 // Register Definitions
124 //==========================================================================
129 //----- Register Files------------------------------------------------------
131 extern __data __at (INDF_ADDR) volatile char INDF;
132 extern __sfr __at (TMR0_ADDR) TMR0;
133 extern __data __at (PCL_ADDR) volatile char PCL;
134 extern __sfr __at (STATUS_ADDR) STATUS;
135 extern __sfr __at (FSR_ADDR) FSR;
136 extern __sfr __at (PORTA_ADDR) PORTA;
137 extern __sfr __at (PORTB_ADDR) PORTB;
138 extern __sfr __at (PORTC_ADDR) PORTC;
139 extern __sfr __at (PCLATH_ADDR) PCLATH;
140 extern __sfr __at (INTCON_ADDR) INTCON;
141 extern __sfr __at (PIR1_ADDR) PIR1;
142 extern __sfr __at (PIR2_ADDR) PIR2;
143 extern __sfr __at (TMR1L_ADDR) TMR1L;
144 extern __sfr __at (TMR1H_ADDR) TMR1H;
145 extern __sfr __at (T1CON_ADDR) T1CON;
146 extern __sfr __at (TMR2_ADDR) TMR2;
147 extern __sfr __at (T2CON_ADDR) T2CON;
148 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
149 extern __sfr __at (SSPCON_ADDR) SSPCON;
150 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
151 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
152 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
153 extern __sfr __at (RCSTA_ADDR) RCSTA;
154 extern __sfr __at (TXREG_ADDR) TXREG;
155 extern __sfr __at (RCREG_ADDR) RCREG;
156 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
157 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
158 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
159 extern __sfr __at (ADRES_ADDR) ADRES;
160 extern __sfr __at (ADCON0_ADDR) ADCON0;
162 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
163 extern __sfr __at (TRISA_ADDR) TRISA;
164 extern __sfr __at (TRISB_ADDR) TRISB;
165 extern __sfr __at (TRISC_ADDR) TRISC;
166 extern __sfr __at (PIE1_ADDR) PIE1;
167 extern __sfr __at (PIE2_ADDR) PIE2;
168 extern __sfr __at (PCON_ADDR) PCON;
169 extern __sfr __at (PR2_ADDR) PR2;
170 extern __sfr __at (SSPADD_ADDR) SSPADD;
171 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
172 extern __sfr __at (TXSTA_ADDR) TXSTA;
173 extern __sfr __at (SPBRG_ADDR) SPBRG;
174 extern __sfr __at (ADCON1_ADDR) ADCON1;
176 extern __sfr __at (PMDATA_ADDR) PMDATA;
177 extern __sfr __at (PMADR_ADDR) PMADR;
178 extern __sfr __at (PMDATH_ADDR) PMDATH;
179 extern __sfr __at (PMADRH_ADDR) PMADRH;
181 extern __sfr __at (PMCON1_ADDR) PMCON1;
183 //----- STATUS Bits --------------------------------------------------------
186 //----- INTCON Bits --------------------------------------------------------
189 //----- PIR1 Bits ----------------------------------------------------------
192 //----- PIR2 Bits ----------------------------------------------------------
195 //----- T1CON Bits ---------------------------------------------------------
198 //----- T2CON Bits ---------------------------------------------------------
201 //----- SSPCON Bits --------------------------------------------------------
204 //----- CCP1CON Bits -------------------------------------------------------
207 //----- RCSTA Bits ---------------------------------------------------------
210 //----- CCP2CON Bits -------------------------------------------------------
213 //----- ADCON0 Bits --------------------------------------------------------
216 //----- OPTION Bits --------------------------------------------------------
219 //----- PIE1 Bits ----------------------------------------------------------
222 //----- PIE2 Bits ----------------------------------------------------------
225 //----- PCON Bits ----------------------------------------------------------
228 //----- SSPSTAT Bits -------------------------------------------------------
231 //----- TXSTA Bits ---------------------------------------------------------
234 //----- ADCON1 Bits --------------------------------------------------------
237 //----- PMCON1 Bits --------------------------------------------------------
239 //==========================================================================
243 //==========================================================================
246 // __BADRAM H'08'-H'09', H'88'-H'89'
247 // __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
248 // __BADRAM H'105', H'107'-H'109'
249 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
251 //==========================================================================
253 // Configuration Bits
255 //==========================================================================
257 #define _BODEN_ON 0x3FFF
258 #define _BODEN_OFF 0x3FBF
259 #define _CP_ALL 0x3FEF
260 #define _CP_OFF 0x3FFF
261 #define _PWRTE_OFF 0x3FFF
262 #define _PWRTE_ON 0x3FF7
263 #define _WDT_ON 0x3FFF
264 #define _WDT_OFF 0x3FFB
265 #define _LP_OSC 0x3FFC
266 #define _XT_OSC 0x3FFD
267 #define _HS_OSC 0x3FFE
268 #define _RC_OSC 0x3FFF
272 // ----- ADCON0 bits --------------------
275 unsigned char ADON:1;
278 unsigned char CHS0:1;
279 unsigned char CHS1:1;
280 unsigned char CHS2:1;
281 unsigned char ADCS0:1;
282 unsigned char ADCS1:1;
287 unsigned char NOT_DONE:1;
297 unsigned char GO_DONE:1;
305 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
307 #define ADON ADCON0_bits.ADON
308 #define GO ADCON0_bits.GO
309 #define NOT_DONE ADCON0_bits.NOT_DONE
310 #define GO_DONE ADCON0_bits.GO_DONE
311 #define CHS0 ADCON0_bits.CHS0
312 #define CHS1 ADCON0_bits.CHS1
313 #define CHS2 ADCON0_bits.CHS2
314 #define ADCS0 ADCON0_bits.ADCS0
315 #define ADCS1 ADCON0_bits.ADCS1
317 // ----- ADCON1 bits --------------------
320 unsigned char PCFG0:1;
321 unsigned char PCFG1:1;
322 unsigned char PCFG2:1;
330 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
332 #define PCFG0 ADCON1_bits.PCFG0
333 #define PCFG1 ADCON1_bits.PCFG1
334 #define PCFG2 ADCON1_bits.PCFG2
336 // ----- CCP1CON bits --------------------
339 unsigned char CCP1M0:1;
340 unsigned char CCP1M1:1;
341 unsigned char CCP1M2:1;
342 unsigned char CCP1M3:1;
343 unsigned char CCP1Y:1;
344 unsigned char CCP1X:1;
349 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
351 #define CCP1M0 CCP1CON_bits.CCP1M0
352 #define CCP1M1 CCP1CON_bits.CCP1M1
353 #define CCP1M2 CCP1CON_bits.CCP1M2
354 #define CCP1M3 CCP1CON_bits.CCP1M3
355 #define CCP1Y CCP1CON_bits.CCP1Y
356 #define CCP1X CCP1CON_bits.CCP1X
358 // ----- CCP2CON bits --------------------
361 unsigned char CCP2M0:1;
362 unsigned char CCP2M1:1;
363 unsigned char CCP2M2:1;
364 unsigned char CCP2M3:1;
365 unsigned char CCP2Y:1;
366 unsigned char CCP2X:1;
371 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
373 #define CCP2M0 CCP2CON_bits.CCP2M0
374 #define CCP2M1 CCP2CON_bits.CCP2M1
375 #define CCP2M2 CCP2CON_bits.CCP2M2
376 #define CCP2M3 CCP2CON_bits.CCP2M3
377 #define CCP2Y CCP2CON_bits.CCP2Y
378 #define CCP2X CCP2CON_bits.CCP2X
380 // ----- INTCON bits --------------------
383 unsigned char RBIF:1;
384 unsigned char INTF:1;
385 unsigned char T0IF:1;
386 unsigned char RBIE:1;
387 unsigned char INTE:1;
388 unsigned char T0IE:1;
389 unsigned char PEIE:1;
393 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
395 #define RBIF INTCON_bits.RBIF
396 #define INTF INTCON_bits.INTF
397 #define T0IF INTCON_bits.T0IF
398 #define RBIE INTCON_bits.RBIE
399 #define INTE INTCON_bits.INTE
400 #define T0IE INTCON_bits.T0IE
401 #define PEIE INTCON_bits.PEIE
402 #define GIE INTCON_bits.GIE
404 // ----- OPTION_REG bits --------------------
411 unsigned char T0SE:1;
412 unsigned char T0CS:1;
413 unsigned char INTEDG:1;
414 unsigned char NOT_RBPU:1;
416 } __OPTION_REG_bits_t;
417 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
419 #define PS0 OPTION_REG_bits.PS0
420 #define PS1 OPTION_REG_bits.PS1
421 #define PS2 OPTION_REG_bits.PS2
422 #define PSA OPTION_REG_bits.PSA
423 #define T0SE OPTION_REG_bits.T0SE
424 #define T0CS OPTION_REG_bits.T0CS
425 #define INTEDG OPTION_REG_bits.INTEDG
426 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
428 // ----- PCON bits --------------------
431 unsigned char NOT_BO:1;
432 unsigned char NOT_POR:1;
441 unsigned char NOT_BOR:1;
451 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
453 #define NOT_BO PCON_bits.NOT_BO
454 #define NOT_BOR PCON_bits.NOT_BOR
455 #define NOT_POR PCON_bits.NOT_POR
457 // ----- PIE1 bits --------------------
460 unsigned char TMR1IE:1;
461 unsigned char TMR2IE:1;
462 unsigned char CCP1IE:1;
463 unsigned char SSPIE:1;
464 unsigned char TXIE:1;
465 unsigned char RCIE:1;
466 unsigned char ADIE:1;
470 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
472 #define TMR1IE PIE1_bits.TMR1IE
473 #define TMR2IE PIE1_bits.TMR2IE
474 #define CCP1IE PIE1_bits.CCP1IE
475 #define SSPIE PIE1_bits.SSPIE
476 #define TXIE PIE1_bits.TXIE
477 #define RCIE PIE1_bits.RCIE
478 #define ADIE PIE1_bits.ADIE
480 // ----- PIE2 bits --------------------
483 unsigned char CCP2IE:1;
493 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
495 #define CCP2IE PIE2_bits.CCP2IE
497 // ----- PIR1 bits --------------------
500 unsigned char TMR1IF:1;
501 unsigned char TMR2IF:1;
502 unsigned char CCP1IF:1;
503 unsigned char SSPIF:1;
504 unsigned char TXIF:1;
505 unsigned char RCIF:1;
506 unsigned char ADIF:1;
510 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
512 #define TMR1IF PIR1_bits.TMR1IF
513 #define TMR2IF PIR1_bits.TMR2IF
514 #define CCP1IF PIR1_bits.CCP1IF
515 #define SSPIF PIR1_bits.SSPIF
516 #define TXIF PIR1_bits.TXIF
517 #define RCIF PIR1_bits.RCIF
518 #define ADIF PIR1_bits.ADIF
520 // ----- PIR2 bits --------------------
523 unsigned char CCP2IF:1;
533 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
535 #define CCP2IF PIR2_bits.CCP2IF
537 // ----- PMCON1 bits --------------------
550 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
552 #define RD PMCON1_bits.RD
554 // ----- PORTA bits --------------------
567 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
569 #define RA0 PORTA_bits.RA0
570 #define RA1 PORTA_bits.RA1
571 #define RA2 PORTA_bits.RA2
572 #define RA3 PORTA_bits.RA3
573 #define RA4 PORTA_bits.RA4
574 #define RA5 PORTA_bits.RA5
576 // ----- PORTB bits --------------------
589 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
591 #define RB0 PORTB_bits.RB0
592 #define RB1 PORTB_bits.RB1
593 #define RB2 PORTB_bits.RB2
594 #define RB3 PORTB_bits.RB3
595 #define RB4 PORTB_bits.RB4
596 #define RB5 PORTB_bits.RB5
597 #define RB6 PORTB_bits.RB6
598 #define RB7 PORTB_bits.RB7
600 // ----- PORTC bits --------------------
613 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
615 #define RC0 PORTC_bits.RC0
616 #define RC1 PORTC_bits.RC1
617 #define RC2 PORTC_bits.RC2
618 #define RC3 PORTC_bits.RC3
619 #define RC4 PORTC_bits.RC4
620 #define RC5 PORTC_bits.RC5
621 #define RC6 PORTC_bits.RC6
622 #define RC7 PORTC_bits.RC7
624 // ----- RCSTA bits --------------------
627 unsigned char RX9D:1;
628 unsigned char OERR:1;
629 unsigned char FERR:1;
631 unsigned char CREN:1;
632 unsigned char SREN:1;
634 unsigned char SPEN:1;
637 unsigned char RCD8:1;
653 unsigned char NOT_RC8:1;
663 unsigned char RC8_9:1;
667 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
669 #define RX9D RCSTA_bits.RX9D
670 #define RCD8 RCSTA_bits.RCD8
671 #define OERR RCSTA_bits.OERR
672 #define FERR RCSTA_bits.FERR
673 #define CREN RCSTA_bits.CREN
674 #define SREN RCSTA_bits.SREN
675 #define RX9 RCSTA_bits.RX9
676 #define RC9 RCSTA_bits.RC9
677 #define NOT_RC8 RCSTA_bits.NOT_RC8
678 #define RC8_9 RCSTA_bits.RC8_9
679 #define SPEN RCSTA_bits.SPEN
681 // ----- SSPCON bits --------------------
684 unsigned char SSPM0:1;
685 unsigned char SSPM1:1;
686 unsigned char SSPM2:1;
687 unsigned char SSPM3:1;
689 unsigned char SSPEN:1;
690 unsigned char SSPOV:1;
691 unsigned char WCOL:1;
694 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
696 #define SSPM0 SSPCON_bits.SSPM0
697 #define SSPM1 SSPCON_bits.SSPM1
698 #define SSPM2 SSPCON_bits.SSPM2
699 #define SSPM3 SSPCON_bits.SSPM3
700 #define CKP SSPCON_bits.CKP
701 #define SSPEN SSPCON_bits.SSPEN
702 #define SSPOV SSPCON_bits.SSPOV
703 #define WCOL SSPCON_bits.WCOL
705 // ----- SSPSTAT bits --------------------
720 unsigned char I2C_READ:1;
721 unsigned char I2C_START:1;
722 unsigned char I2C_STOP:1;
723 unsigned char I2C_DATA:1;
730 unsigned char NOT_W:1;
733 unsigned char NOT_A:1;
740 unsigned char NOT_WRITE:1;
743 unsigned char NOT_ADDRESS:1;
760 unsigned char READ_WRITE:1;
763 unsigned char DATA_ADDRESS:1;
768 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
770 #define BF SSPSTAT_bits.BF
771 #define UA SSPSTAT_bits.UA
772 #define R SSPSTAT_bits.R
773 #define I2C_READ SSPSTAT_bits.I2C_READ
774 #define NOT_W SSPSTAT_bits.NOT_W
775 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
776 #define R_W SSPSTAT_bits.R_W
777 #define READ_WRITE SSPSTAT_bits.READ_WRITE
778 #define S SSPSTAT_bits.S
779 #define I2C_START SSPSTAT_bits.I2C_START
780 #define P SSPSTAT_bits.P
781 #define I2C_STOP SSPSTAT_bits.I2C_STOP
782 #define D SSPSTAT_bits.D
783 #define I2C_DATA SSPSTAT_bits.I2C_DATA
784 #define NOT_A SSPSTAT_bits.NOT_A
785 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
786 #define D_A SSPSTAT_bits.D_A
787 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
788 #define CKE SSPSTAT_bits.CKE
789 #define SMP SSPSTAT_bits.SMP
791 // ----- STATUS bits --------------------
797 unsigned char NOT_PD:1;
798 unsigned char NOT_TO:1;
804 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
806 #define C STATUS_bits.C
807 #define DC STATUS_bits.DC
808 #define Z STATUS_bits.Z
809 #define NOT_PD STATUS_bits.NOT_PD
810 #define NOT_TO STATUS_bits.NOT_TO
811 #define RP0 STATUS_bits.RP0
812 #define RP1 STATUS_bits.RP1
813 #define IRP STATUS_bits.IRP
815 // ----- T1CON bits --------------------
818 unsigned char TMR1ON:1;
819 unsigned char TMR1CS:1;
820 unsigned char NOT_T1SYNC:1;
821 unsigned char T1OSCEN:1;
822 unsigned char T1CKPS0:1;
823 unsigned char T1CKPS1:1;
830 unsigned char T1INSYNC:1;
838 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
840 #define TMR1ON T1CON_bits.TMR1ON
841 #define TMR1CS T1CON_bits.TMR1CS
842 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
843 #define T1INSYNC T1CON_bits.T1INSYNC
844 #define T1OSCEN T1CON_bits.T1OSCEN
845 #define T1CKPS0 T1CON_bits.T1CKPS0
846 #define T1CKPS1 T1CON_bits.T1CKPS1
848 // ----- T2CON bits --------------------
851 unsigned char T2CKPS0:1;
852 unsigned char T2CKPS1:1;
853 unsigned char TMR2ON:1;
854 unsigned char TOUTPS0:1;
855 unsigned char TOUTPS1:1;
856 unsigned char TOUTPS2:1;
857 unsigned char TOUTPS3:1;
861 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
863 #define T2CKPS0 T2CON_bits.T2CKPS0
864 #define T2CKPS1 T2CON_bits.T2CKPS1
865 #define TMR2ON T2CON_bits.TMR2ON
866 #define TOUTPS0 T2CON_bits.TOUTPS0
867 #define TOUTPS1 T2CON_bits.TOUTPS1
868 #define TOUTPS2 T2CON_bits.TOUTPS2
869 #define TOUTPS3 T2CON_bits.TOUTPS3
871 // ----- TRISA bits --------------------
874 unsigned char TRISA0:1;
875 unsigned char TRISA1:1;
876 unsigned char TRISA2:1;
877 unsigned char TRISA3:1;
878 unsigned char TRISA4:1;
879 unsigned char TRISA5:1;
884 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
886 #define TRISA0 TRISA_bits.TRISA0
887 #define TRISA1 TRISA_bits.TRISA1
888 #define TRISA2 TRISA_bits.TRISA2
889 #define TRISA3 TRISA_bits.TRISA3
890 #define TRISA4 TRISA_bits.TRISA4
891 #define TRISA5 TRISA_bits.TRISA5
893 // ----- TRISB bits --------------------
896 unsigned char TRISB0:1;
897 unsigned char TRISB1:1;
898 unsigned char TRISB2:1;
899 unsigned char TRISB3:1;
900 unsigned char TRISB4:1;
901 unsigned char TRISB5:1;
902 unsigned char TRISB6:1;
903 unsigned char TRISB7:1;
906 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
908 #define TRISB0 TRISB_bits.TRISB0
909 #define TRISB1 TRISB_bits.TRISB1
910 #define TRISB2 TRISB_bits.TRISB2
911 #define TRISB3 TRISB_bits.TRISB3
912 #define TRISB4 TRISB_bits.TRISB4
913 #define TRISB5 TRISB_bits.TRISB5
914 #define TRISB6 TRISB_bits.TRISB6
915 #define TRISB7 TRISB_bits.TRISB7
917 // ----- TRISC bits --------------------
920 unsigned char TRISC0:1;
921 unsigned char TRISC1:1;
922 unsigned char TRISC2:1;
923 unsigned char TRISC3:1;
924 unsigned char TRISC4:1;
925 unsigned char TRISC5:1;
926 unsigned char TRISC6:1;
927 unsigned char TRISC7:1;
930 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
932 #define TRISC0 TRISC_bits.TRISC0
933 #define TRISC1 TRISC_bits.TRISC1
934 #define TRISC2 TRISC_bits.TRISC2
935 #define TRISC3 TRISC_bits.TRISC3
936 #define TRISC4 TRISC_bits.TRISC4
937 #define TRISC5 TRISC_bits.TRISC5
938 #define TRISC6 TRISC_bits.TRISC6
939 #define TRISC7 TRISC_bits.TRISC7
941 // ----- TXSTA bits --------------------
944 unsigned char TX9D:1;
945 unsigned char TRMT:1;
946 unsigned char BRGH:1;
948 unsigned char SYNC:1;
949 unsigned char TXEN:1;
951 unsigned char CSRC:1;
954 unsigned char TXD8:1;
960 unsigned char NOT_TX8:1;
970 unsigned char TX8_9:1;
974 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
976 #define TX9D TXSTA_bits.TX9D
977 #define TXD8 TXSTA_bits.TXD8
978 #define TRMT TXSTA_bits.TRMT
979 #define BRGH TXSTA_bits.BRGH
980 #define SYNC TXSTA_bits.SYNC
981 #define TXEN TXSTA_bits.TXEN
982 #define TX9 TXSTA_bits.TX9
983 #define NOT_TX8 TXSTA_bits.NOT_TX8
984 #define TX8_9 TXSTA_bits.TX8_9
985 #define CSRC TXSTA_bits.CSRC