2 // Register Declarations for Microchip 16F74 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRES_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define PR2_ADDR 0x0092
70 #define SSPADD_ADDR 0x0093
71 #define SSPSTAT_ADDR 0x0094
72 #define TXSTA_ADDR 0x0098
73 #define SPBRG_ADDR 0x0099
74 #define ADCON1_ADDR 0x009F
75 #define PMDATA_ADDR 0x010C
76 #define PMADR_ADDR 0x010D
77 #define PMDATH_ADDR 0x010E
78 #define PMADRH_ADDR 0x010F
79 #define PMCON1_ADDR 0x018C
82 // Memory organization.
85 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
86 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
87 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
88 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
89 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
90 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
91 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
92 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
93 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
94 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
95 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
96 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
97 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
98 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
99 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
100 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
101 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
102 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
103 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
104 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
105 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
106 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
107 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
108 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
109 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
110 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
111 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
112 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
113 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
114 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
115 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
116 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
117 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
118 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
119 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
120 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
121 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
122 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
123 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
124 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
125 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
126 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
127 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
128 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
129 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
130 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
131 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
132 #pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
133 #pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
134 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
135 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
136 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
140 // P16F74.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
143 // This header file defines configurations, registers, and other useful bits of
144 // information for the PIC16F74 microcontroller. These names are taken to match
145 // the data sheets as closely as possible.
147 // Note that the processor must be selected before this file is
148 // included. The processor may be selected the following ways:
150 // 1. Command line switch:
151 // C:\ MPASM MYFILE.ASM /PIC16F74
152 // 2. LIST directive in the source file
154 // 3. Processor Type entry in the MPASM full-screen interface
156 //==========================================================================
160 //==========================================================================
164 //1.00 00/00/00 Initial Release
166 //==========================================================================
170 //==========================================================================
173 // MESSG "Processor-header file mismatch. Verify selected processor."
176 //==========================================================================
178 // Register Definitions
180 //==========================================================================
185 //----- Register Files------------------------------------------------------
187 extern data __at (INDF_ADDR) volatile char INDF;
188 extern sfr __at (TMR0_ADDR) TMR0;
189 extern data __at (PCL_ADDR) volatile char PCL;
190 extern sfr __at (STATUS_ADDR) STATUS;
191 extern sfr __at (FSR_ADDR) FSR;
192 extern sfr __at (PORTA_ADDR) PORTA;
193 extern sfr __at (PORTB_ADDR) PORTB;
194 extern sfr __at (PORTC_ADDR) PORTC;
195 extern sfr __at (PORTD_ADDR) PORTD;
196 extern sfr __at (PORTE_ADDR) PORTE;
197 extern sfr __at (PCLATH_ADDR) PCLATH;
198 extern sfr __at (INTCON_ADDR) INTCON;
199 extern sfr __at (PIR1_ADDR) PIR1;
200 extern sfr __at (PIR2_ADDR) PIR2;
201 extern sfr __at (TMR1L_ADDR) TMR1L;
202 extern sfr __at (TMR1H_ADDR) TMR1H;
203 extern sfr __at (T1CON_ADDR) T1CON;
204 extern sfr __at (TMR2_ADDR) TMR2;
205 extern sfr __at (T2CON_ADDR) T2CON;
206 extern sfr __at (SSPBUF_ADDR) SSPBUF;
207 extern sfr __at (SSPCON_ADDR) SSPCON;
208 extern sfr __at (CCPR1L_ADDR) CCPR1L;
209 extern sfr __at (CCPR1H_ADDR) CCPR1H;
210 extern sfr __at (CCP1CON_ADDR) CCP1CON;
211 extern sfr __at (RCSTA_ADDR) RCSTA;
212 extern sfr __at (TXREG_ADDR) TXREG;
213 extern sfr __at (RCREG_ADDR) RCREG;
214 extern sfr __at (CCPR2L_ADDR) CCPR2L;
215 extern sfr __at (CCPR2H_ADDR) CCPR2H;
216 extern sfr __at (CCP2CON_ADDR) CCP2CON;
217 extern sfr __at (ADRES_ADDR) ADRES;
218 extern sfr __at (ADCON0_ADDR) ADCON0;
220 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
221 extern sfr __at (TRISA_ADDR) TRISA;
222 extern sfr __at (TRISB_ADDR) TRISB;
223 extern sfr __at (TRISC_ADDR) TRISC;
224 extern sfr __at (TRISD_ADDR) TRISD;
225 extern sfr __at (TRISE_ADDR) TRISE;
226 extern sfr __at (PIE1_ADDR) PIE1;
227 extern sfr __at (PIE2_ADDR) PIE2;
228 extern sfr __at (PCON_ADDR) PCON;
229 extern sfr __at (PR2_ADDR) PR2;
230 extern sfr __at (SSPADD_ADDR) SSPADD;
231 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
232 extern sfr __at (TXSTA_ADDR) TXSTA;
233 extern sfr __at (SPBRG_ADDR) SPBRG;
234 extern sfr __at (ADCON1_ADDR) ADCON1;
236 extern sfr __at (PMDATA_ADDR) PMDATA;
237 extern sfr __at (PMADR_ADDR) PMADR;
238 extern sfr __at (PMDATH_ADDR) PMDATH;
239 extern sfr __at (PMADRH_ADDR) PMADRH;
241 extern sfr __at (PMCON1_ADDR) PMCON1;
243 //----- STATUS Bits --------------------------------------------------------
246 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
252 //----- PIR2 Bits ----------------------------------------------------------
255 //----- T1CON Bits ---------------------------------------------------------
258 //----- T2CON Bits ---------------------------------------------------------
261 //----- SSPCON Bits --------------------------------------------------------
264 //----- CCP1CON Bits -------------------------------------------------------
267 //----- RCSTA Bits ---------------------------------------------------------
270 //----- CCP2CON Bits -------------------------------------------------------
273 //----- ADCON0 Bits --------------------------------------------------------
276 //----- OPTION Bits --------------------------------------------------------
279 //----- TRISE Bits ---------------------------------------------------------
282 //----- PIE1 Bits ----------------------------------------------------------
285 //----- PIE2 Bits ----------------------------------------------------------
288 //----- PCON Bits ----------------------------------------------------------
291 //----- SSPSTAT Bits -------------------------------------------------------
294 //----- TXSTA Bits ---------------------------------------------------------
297 //----- ADCON1 Bits --------------------------------------------------------
300 //----- PMCON1 Bits --------------------------------------------------------
302 //==========================================================================
306 //==========================================================================
309 // __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
310 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
311 // __BADRAM H'185', H'187'-H'189', H'18D'-H'19F'
313 //==========================================================================
315 // Configuration Bits
317 //==========================================================================
319 #define _BODEN_ON 0x3FFF
320 #define _BODEN_OFF 0x3FBF
321 #define _CP_ALL 0x3FEF
322 #define _CP_OFF 0x3FFF
323 #define _PWRTE_OFF 0x3FFF
324 #define _PWRTE_ON 0x3FF7
325 #define _WDT_ON 0x3FFF
326 #define _WDT_OFF 0x3FFB
327 #define _LP_OSC 0x3FFC
328 #define _XT_OSC 0x3FFD
329 #define _HS_OSC 0x3FFE
330 #define _RC_OSC 0x3FFF
334 // ----- ADCON0 bits --------------------
337 unsigned char ADON:1;
340 unsigned char CHS0:1;
341 unsigned char CHS1:1;
342 unsigned char CHS2:1;
343 unsigned char ADCS0:1;
344 unsigned char ADCS1:1;
349 unsigned char NOT_DONE:1;
359 unsigned char GO_DONE:1;
367 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
369 #define ADON ADCON0_bits.ADON
370 #define GO ADCON0_bits.GO
371 #define NOT_DONE ADCON0_bits.NOT_DONE
372 #define GO_DONE ADCON0_bits.GO_DONE
373 #define CHS0 ADCON0_bits.CHS0
374 #define CHS1 ADCON0_bits.CHS1
375 #define CHS2 ADCON0_bits.CHS2
376 #define ADCS0 ADCON0_bits.ADCS0
377 #define ADCS1 ADCON0_bits.ADCS1
379 // ----- ADCON1 bits --------------------
382 unsigned char PCFG0:1;
383 unsigned char PCFG1:1;
384 unsigned char PCFG2:1;
392 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
394 #define PCFG0 ADCON1_bits.PCFG0
395 #define PCFG1 ADCON1_bits.PCFG1
396 #define PCFG2 ADCON1_bits.PCFG2
398 // ----- CCP1CON bits --------------------
401 unsigned char CCP1M0:1;
402 unsigned char CCP1M1:1;
403 unsigned char CCP1M2:1;
404 unsigned char CCP1M3:1;
405 unsigned char CCP1Y:1;
406 unsigned char CCP1X:1;
411 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
413 #define CCP1M0 CCP1CON_bits.CCP1M0
414 #define CCP1M1 CCP1CON_bits.CCP1M1
415 #define CCP1M2 CCP1CON_bits.CCP1M2
416 #define CCP1M3 CCP1CON_bits.CCP1M3
417 #define CCP1Y CCP1CON_bits.CCP1Y
418 #define CCP1X CCP1CON_bits.CCP1X
420 // ----- CCP2CON bits --------------------
423 unsigned char CCP2M0:1;
424 unsigned char CCP2M1:1;
425 unsigned char CCP2M2:1;
426 unsigned char CCP2M3:1;
427 unsigned char CCP2Y:1;
428 unsigned char CCP2X:1;
433 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
435 #define CCP2M0 CCP2CON_bits.CCP2M0
436 #define CCP2M1 CCP2CON_bits.CCP2M1
437 #define CCP2M2 CCP2CON_bits.CCP2M2
438 #define CCP2M3 CCP2CON_bits.CCP2M3
439 #define CCP2Y CCP2CON_bits.CCP2Y
440 #define CCP2X CCP2CON_bits.CCP2X
442 // ----- INTCON bits --------------------
445 unsigned char RBIF:1;
446 unsigned char INTF:1;
447 unsigned char T0IF:1;
448 unsigned char RBIE:1;
449 unsigned char INTE:1;
450 unsigned char T0IE:1;
451 unsigned char PEIE:1;
455 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
457 #define RBIF INTCON_bits.RBIF
458 #define INTF INTCON_bits.INTF
459 #define T0IF INTCON_bits.T0IF
460 #define RBIE INTCON_bits.RBIE
461 #define INTE INTCON_bits.INTE
462 #define T0IE INTCON_bits.T0IE
463 #define PEIE INTCON_bits.PEIE
464 #define GIE INTCON_bits.GIE
466 // ----- OPTION_REG bits --------------------
473 unsigned char T0SE:1;
474 unsigned char T0CS:1;
475 unsigned char INTEDG:1;
476 unsigned char NOT_RBPU:1;
478 } __OPTION_REG_bits_t;
479 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
481 #define PS0 OPTION_REG_bits.PS0
482 #define PS1 OPTION_REG_bits.PS1
483 #define PS2 OPTION_REG_bits.PS2
484 #define PSA OPTION_REG_bits.PSA
485 #define T0SE OPTION_REG_bits.T0SE
486 #define T0CS OPTION_REG_bits.T0CS
487 #define INTEDG OPTION_REG_bits.INTEDG
488 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
490 // ----- PCON bits --------------------
493 unsigned char NOT_BO:1;
494 unsigned char NOT_POR:1;
503 unsigned char NOT_BOR:1;
513 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
515 #define NOT_BO PCON_bits.NOT_BO
516 #define NOT_BOR PCON_bits.NOT_BOR
517 #define NOT_POR PCON_bits.NOT_POR
519 // ----- PIE1 bits --------------------
522 unsigned char TMR1IE:1;
523 unsigned char TMR2IE:1;
524 unsigned char CCP1IE:1;
525 unsigned char SSPIE:1;
526 unsigned char TXIE:1;
527 unsigned char RCIE:1;
528 unsigned char ADIE:1;
529 unsigned char PSPIE:1;
532 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
534 #define TMR1IE PIE1_bits.TMR1IE
535 #define TMR2IE PIE1_bits.TMR2IE
536 #define CCP1IE PIE1_bits.CCP1IE
537 #define SSPIE PIE1_bits.SSPIE
538 #define TXIE PIE1_bits.TXIE
539 #define RCIE PIE1_bits.RCIE
540 #define ADIE PIE1_bits.ADIE
541 #define PSPIE PIE1_bits.PSPIE
543 // ----- PIE2 bits --------------------
546 unsigned char CCP2IE:1;
556 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
558 #define CCP2IE PIE2_bits.CCP2IE
560 // ----- PIR1 bits --------------------
563 unsigned char TMR1IF:1;
564 unsigned char TMR2IF:1;
565 unsigned char CCP1IF:1;
566 unsigned char SSPIF:1;
567 unsigned char TXIF:1;
568 unsigned char RCIF:1;
569 unsigned char ADIF:1;
570 unsigned char PSPIF:1;
573 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
575 #define TMR1IF PIR1_bits.TMR1IF
576 #define TMR2IF PIR1_bits.TMR2IF
577 #define CCP1IF PIR1_bits.CCP1IF
578 #define SSPIF PIR1_bits.SSPIF
579 #define TXIF PIR1_bits.TXIF
580 #define RCIF PIR1_bits.RCIF
581 #define ADIF PIR1_bits.ADIF
582 #define PSPIF PIR1_bits.PSPIF
584 // ----- PIR2 bits --------------------
587 unsigned char CCP2IF:1;
597 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
599 #define CCP2IF PIR2_bits.CCP2IF
601 // ----- PMCON1 bits --------------------
614 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
616 #define RD PMCON1_bits.RD
618 // ----- RCSTA bits --------------------
621 unsigned char RX9D:1;
622 unsigned char OERR:1;
623 unsigned char FERR:1;
625 unsigned char CREN:1;
626 unsigned char SREN:1;
628 unsigned char SPEN:1;
631 unsigned char RCD8:1;
647 unsigned char NOT_RC8:1;
657 unsigned char RC8_9:1;
661 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
663 #define RX9D RCSTA_bits.RX9D
664 #define RCD8 RCSTA_bits.RCD8
665 #define OERR RCSTA_bits.OERR
666 #define FERR RCSTA_bits.FERR
667 #define CREN RCSTA_bits.CREN
668 #define SREN RCSTA_bits.SREN
669 #define RX9 RCSTA_bits.RX9
670 #define RC9 RCSTA_bits.RC9
671 #define NOT_RC8 RCSTA_bits.NOT_RC8
672 #define RC8_9 RCSTA_bits.RC8_9
673 #define SPEN RCSTA_bits.SPEN
675 // ----- SSPCON bits --------------------
678 unsigned char SSPM0:1;
679 unsigned char SSPM1:1;
680 unsigned char SSPM2:1;
681 unsigned char SSPM3:1;
683 unsigned char SSPEN:1;
684 unsigned char SSPOV:1;
685 unsigned char WCOL:1;
688 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
690 #define SSPM0 SSPCON_bits.SSPM0
691 #define SSPM1 SSPCON_bits.SSPM1
692 #define SSPM2 SSPCON_bits.SSPM2
693 #define SSPM3 SSPCON_bits.SSPM3
694 #define CKP SSPCON_bits.CKP
695 #define SSPEN SSPCON_bits.SSPEN
696 #define SSPOV SSPCON_bits.SSPOV
697 #define WCOL SSPCON_bits.WCOL
699 // ----- SSPSTAT bits --------------------
714 unsigned char I2C_READ:1;
715 unsigned char I2C_START:1;
716 unsigned char I2C_STOP:1;
717 unsigned char I2C_DATA:1;
724 unsigned char NOT_W:1;
727 unsigned char NOT_A:1;
734 unsigned char NOT_WRITE:1;
737 unsigned char NOT_ADDRESS:1;
754 unsigned char READ_WRITE:1;
757 unsigned char DATA_ADDRESS:1;
762 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
764 #define BF SSPSTAT_bits.BF
765 #define UA SSPSTAT_bits.UA
766 #define R SSPSTAT_bits.R
767 #define I2C_READ SSPSTAT_bits.I2C_READ
768 #define NOT_W SSPSTAT_bits.NOT_W
769 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
770 #define R_W SSPSTAT_bits.R_W
771 #define READ_WRITE SSPSTAT_bits.READ_WRITE
772 #define S SSPSTAT_bits.S
773 #define I2C_START SSPSTAT_bits.I2C_START
774 #define P SSPSTAT_bits.P
775 #define I2C_STOP SSPSTAT_bits.I2C_STOP
776 #define D SSPSTAT_bits.D
777 #define I2C_DATA SSPSTAT_bits.I2C_DATA
778 #define NOT_A SSPSTAT_bits.NOT_A
779 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
780 #define D_A SSPSTAT_bits.D_A
781 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
782 #define CKE SSPSTAT_bits.CKE
783 #define SMP SSPSTAT_bits.SMP
785 // ----- STATUS bits --------------------
791 unsigned char NOT_PD:1;
792 unsigned char NOT_TO:1;
798 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
800 #define C STATUS_bits.C
801 #define DC STATUS_bits.DC
802 #define Z STATUS_bits.Z
803 #define NOT_PD STATUS_bits.NOT_PD
804 #define NOT_TO STATUS_bits.NOT_TO
805 #define RP0 STATUS_bits.RP0
806 #define RP1 STATUS_bits.RP1
807 #define IRP STATUS_bits.IRP
809 // ----- T1CON bits --------------------
812 unsigned char TMR1ON:1;
813 unsigned char TMR1CS:1;
814 unsigned char NOT_T1SYNC:1;
815 unsigned char T1OSCEN:1;
816 unsigned char T1CKPS0:1;
817 unsigned char T1CKPS1:1;
824 unsigned char T1INSYNC:1;
832 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
834 #define TMR1ON T1CON_bits.TMR1ON
835 #define TMR1CS T1CON_bits.TMR1CS
836 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
837 #define T1INSYNC T1CON_bits.T1INSYNC
838 #define T1OSCEN T1CON_bits.T1OSCEN
839 #define T1CKPS0 T1CON_bits.T1CKPS0
840 #define T1CKPS1 T1CON_bits.T1CKPS1
842 // ----- T2CON bits --------------------
845 unsigned char T2CKPS0:1;
846 unsigned char T2CKPS1:1;
847 unsigned char TMR2ON:1;
848 unsigned char TOUTPS0:1;
849 unsigned char TOUTPS1:1;
850 unsigned char TOUTPS2:1;
851 unsigned char TOUTPS3:1;
855 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
857 #define T2CKPS0 T2CON_bits.T2CKPS0
858 #define T2CKPS1 T2CON_bits.T2CKPS1
859 #define TMR2ON T2CON_bits.TMR2ON
860 #define TOUTPS0 T2CON_bits.TOUTPS0
861 #define TOUTPS1 T2CON_bits.TOUTPS1
862 #define TOUTPS2 T2CON_bits.TOUTPS2
863 #define TOUTPS3 T2CON_bits.TOUTPS3
865 // ----- TRISE bits --------------------
868 unsigned char TRISE0:1;
869 unsigned char TRISE1:1;
870 unsigned char TRISE2:1;
872 unsigned char PSPMODE:1;
873 unsigned char IBOV:1;
878 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
880 #define TRISE0 TRISE_bits.TRISE0
881 #define TRISE1 TRISE_bits.TRISE1
882 #define TRISE2 TRISE_bits.TRISE2
883 #define PSPMODE TRISE_bits.PSPMODE
884 #define IBOV TRISE_bits.IBOV
885 #define OBF TRISE_bits.OBF
886 #define IBF TRISE_bits.IBF
888 // ----- TXSTA bits --------------------
891 unsigned char TX9D:1;
892 unsigned char TRMT:1;
893 unsigned char BRGH:1;
895 unsigned char SYNC:1;
896 unsigned char TXEN:1;
898 unsigned char CSRC:1;
901 unsigned char TXD8:1;
907 unsigned char NOT_TX8:1;
917 unsigned char TX8_9:1;
921 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
923 #define TX9D TXSTA_bits.TX9D
924 #define TXD8 TXSTA_bits.TXD8
925 #define TRMT TXSTA_bits.TRMT
926 #define BRGH TXSTA_bits.BRGH
927 #define SYNC TXSTA_bits.SYNC
928 #define TXEN TXSTA_bits.TXEN
929 #define TX9 TXSTA_bits.TX9
930 #define NOT_TX8 TXSTA_bits.NOT_TX8
931 #define TX8_9 TXSTA_bits.TX8_9
932 #define CSRC TXSTA_bits.CSRC