2 // Register Declarations for Microchip 16F737 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define OSCCON_ADDR 0x008F
70 #define OSCTUNE_ADDR 0x0090
71 #define SSPCON2_ADDR 0x0091
72 #define PR2_ADDR 0x0092
73 #define SSPADD_ADDR 0x0093
74 #define SSPSTAT_ADDR 0x0094
75 #define CCPR3L_ADDR 0x0095
76 #define CCPR3H_ADDR 0x0096
77 #define CCP3CON_ADDR 0x0097
78 #define TXSTA_ADDR 0x0098
79 #define SPBRG_ADDR 0x0099
80 #define ADCON2_ADDR 0x009B
81 #define CMCON_ADDR 0x009C
82 #define CVRCON_ADDR 0x009D
83 #define ADRESL_ADDR 0x009E
84 #define ADCON1_ADDR 0x009F
85 #define WDTCON_ADDR 0x0105
86 #define LVDCON_ADDR 0x0109
87 #define PMDATA_ADDR 0x010C
88 #define PMADR_ADDR 0x010D
89 #define PMDATH_ADDR 0x010E
90 #define PMADRH_ADDR 0x010F
91 #define PMCON1_ADDR 0x018C
94 // Memory organization.
97 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
98 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
99 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
100 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
101 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
102 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
103 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
104 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
105 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
106 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
107 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
108 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
109 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
110 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
111 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
112 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
113 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
114 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
115 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
116 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
117 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
118 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
119 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
120 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
121 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
122 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
123 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
124 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
125 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
126 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
127 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
128 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
129 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
130 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
131 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
132 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
133 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
134 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
135 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
136 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
137 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
138 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
139 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
140 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
141 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
142 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
143 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
144 #pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L
145 #pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H
146 #pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON
147 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
148 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
149 #pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2
150 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
151 #pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
152 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
153 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
154 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
155 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
156 #pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
157 #pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
158 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
159 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
160 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
164 // P16F737.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
167 // This header file defines configurations, registers, and other useful bits of
168 // information for the PIC16F737 microcontroller. These names are taken to match
169 // the data sheets as closely as possible.
171 // Note that the processor must be selected before this file is
172 // included. The processor may be selected the following ways:
174 // 1. Command line switch:
175 // C:\ MPASM MYFILE.ASM /PIC16F737
176 // 2. LIST directive in the source file
178 // 3. Processor Type entry in the MPASM full-screen interface
180 //==========================================================================
184 //==========================================================================
187 //1.00 05/05/03 Initial Release
188 //1.01 10/21/03 Made changes to Program Memory register names.
189 //1.02 04/07/04 Added INT0IE & INT0IF bit names.
191 //==========================================================================
195 //==========================================================================
198 // MESSG "Processor-header file mismatch. Verify selected processor."
201 //==========================================================================
203 // Register Definitions
205 //==========================================================================
210 //----- Register Files------------------------------------------------------
212 extern __data __at (INDF_ADDR) volatile char INDF;
213 extern __sfr __at (TMR0_ADDR) TMR0;
214 extern __data __at (PCL_ADDR) volatile char PCL;
215 extern __sfr __at (STATUS_ADDR) STATUS;
216 extern __sfr __at (FSR_ADDR) FSR;
217 extern __sfr __at (PORTA_ADDR) PORTA;
218 extern __sfr __at (PORTB_ADDR) PORTB;
219 extern __sfr __at (PORTC_ADDR) PORTC;
220 extern __sfr __at (PORTD_ADDR) PORTD;
221 extern __sfr __at (PORTE_ADDR) PORTE;
222 extern __sfr __at (PCLATH_ADDR) PCLATH;
223 extern __sfr __at (INTCON_ADDR) INTCON;
224 extern __sfr __at (PIR1_ADDR) PIR1;
225 extern __sfr __at (PIR2_ADDR) PIR2;
226 extern __sfr __at (TMR1L_ADDR) TMR1L;
227 extern __sfr __at (TMR1H_ADDR) TMR1H;
228 extern __sfr __at (T1CON_ADDR) T1CON;
229 extern __sfr __at (TMR2_ADDR) TMR2;
230 extern __sfr __at (T2CON_ADDR) T2CON;
231 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
232 extern __sfr __at (SSPCON_ADDR) SSPCON;
233 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
234 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
235 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
236 extern __sfr __at (RCSTA_ADDR) RCSTA;
237 extern __sfr __at (TXREG_ADDR) TXREG;
238 extern __sfr __at (RCREG_ADDR) RCREG;
239 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
240 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
241 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
242 extern __sfr __at (ADRESH_ADDR) ADRESH;
243 extern __sfr __at (ADCON0_ADDR) ADCON0;
245 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
246 extern __sfr __at (TRISA_ADDR) TRISA;
247 extern __sfr __at (TRISB_ADDR) TRISB;
248 extern __sfr __at (TRISC_ADDR) TRISC;
249 extern __sfr __at (TRISD_ADDR) TRISD;
250 extern __sfr __at (TRISE_ADDR) TRISE;
251 extern __sfr __at (PIE1_ADDR) PIE1;
252 extern __sfr __at (PIE2_ADDR) PIE2;
253 extern __sfr __at (PCON_ADDR) PCON;
254 extern __sfr __at (OSCCON_ADDR) OSCCON;
255 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
256 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
257 extern __sfr __at (PR2_ADDR) PR2;
258 extern __sfr __at (SSPADD_ADDR) SSPADD;
259 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
260 extern __sfr __at (CCPR3L_ADDR) CCPR3L;
261 extern __sfr __at (CCPR3H_ADDR) CCPR3H;
262 extern __sfr __at (CCP3CON_ADDR) CCP3CON;
263 extern __sfr __at (TXSTA_ADDR) TXSTA;
264 extern __sfr __at (SPBRG_ADDR) SPBRG;
265 extern __sfr __at (ADCON2_ADDR) ADCON2;
266 extern __sfr __at (CMCON_ADDR) CMCON;
267 extern __sfr __at (CVRCON_ADDR) CVRCON;
268 extern __sfr __at (ADRESL_ADDR) ADRESL;
269 extern __sfr __at (ADCON1_ADDR) ADCON1;
271 extern __sfr __at (WDTCON_ADDR) WDTCON;
272 extern __sfr __at (LVDCON_ADDR) LVDCON;
273 extern __sfr __at (PMDATA_ADDR) PMDATA;
274 extern __sfr __at (PMADR_ADDR) PMADR;
275 extern __sfr __at (PMDATH_ADDR) PMDATH;
276 extern __sfr __at (PMADRH_ADDR) PMADRH;
278 extern __sfr __at (PMCON1_ADDR) PMCON1;
280 //----- STATUS Bits --------------------------------------------------------
283 //----- INTCON Bits --------------------------------------------------------
286 //----- PIR1 Bits ----------------------------------------------------------
289 //----- PIR2 Bits ----------------------------------------------------------
292 //----- T1CON Bits ---------------------------------------------------------
295 //----- T2CON Bits ---------------------------------------------------------
298 //----- SSPCON Bits --------------------------------------------------------
301 //----- CCP1CON Bits -------------------------------------------------------
304 //----- RCSTA Bits ---------------------------------------------------------
307 //----- CCP2CON Bits -------------------------------------------------------
310 //----- ADCON0 Bits --------------------------------------------------------
313 //----- OPTION Bits -----------------------------------------------------
316 //----- TRISE Bits ---------------------------------------------------------
319 //----- PIE1 Bits ----------------------------------------------------------
322 //----- PIE2 Bits ----------------------------------------------------------
325 //----- PCON Bits ----------------------------------------------------------
328 //----- OSCCON Bits -------------------------------------------------------
330 //----- OSCTUNE Bits -------------------------------------------------------
332 //----- SSPCON2 Bits --------------------------------------------------------
335 //----- SSPSTAT Bits -------------------------------------------------------
338 //----- CCP3CON Bits -------------------------------------------------------
341 //----- TXSTA Bits ---------------------------------------------------------
344 //----- ADCON2 Bits ---------------------------------------------------------
347 //----- CMCON Bits ---------------------------------------------------------
350 //----- CVRCON Bits --------------------------------------------------------
353 //----- ADCON1 Bits --------------------------------------------------------
356 //----- WDTCON Bits --------------------------------------------------------
359 //----- LVDCON Bits --------------------------------------------------------
362 //----- PMCON1 Bits --------------------------------------------------------
366 //==========================================================================
370 //==========================================================================
374 // __BADRAM H'88', H'9A'
375 // __BADRAM H'107'-H'108'
376 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
378 //==========================================================================
380 // Configuration Bits
382 //==========================================================================
384 #define _CONFIG1 0x2007
385 #define _CONFIG2 0x2008
387 //Configuration Byte 1 Options
388 #define _CP_ALL 0x1FFF
389 #define _CP_OFF 0x3FFF
390 #define _CCP2_RC1 0x3FFF
391 #define _CCP2_RB3 0x2FFF
392 #define _DEBUG_OFF 0x3FFF
393 #define _DEBUG_ON 0x37FF
394 #define _VBOR_2_0 0x3FFF
395 #define _VBOR_2_7 0x3F7F
396 #define _VBOR_4_2 0x3EFF
397 #define _VBOR_4_5 0x3E7F
398 #define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
399 #define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
400 #define _MCLR_ON 0x3FFF
401 #define _MCLR_OFF 0x3FDF
402 #define _PWRTE_OFF 0x3FFF
403 #define _PWRTE_ON 0x3FF7
404 #define _WDT_ON 0x3FFF
405 #define _WDT_OFF 0x3FFB
406 #define _EXTRC_CLKOUT 0x3FFF
407 #define _EXTRC_IO 0x3FFE
408 #define _INTRC_CLKOUT 0x3FFD
409 #define _INTRC_IO 0x3FFC
410 #define _EXTCLK 0x3FEF
411 #define _HS_OSC 0x3FEE
412 #define _XT_OSC 0x3FED
413 #define _LP_OSC 0x3FEC
415 //Configuration Byte 2 Options
416 #define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
417 #define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
418 #define _IESO_ON 0x3FFF
419 #define _IESO_OFF 0x3FFD
420 #define _FCMEN_ON 0x3FFF
421 #define _FCMEN_OFF 0x3FFE
424 //**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details)
425 //BOREN_1 & BORSEN_1 = BOR enabled and always on
426 //BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware
427 //BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2)
428 //BOREN_0 & BORSEN_0 = BOR disabled
431 // To use the Configuration Bits, place the following lines in your source code
432 // in the following format, and change the configuration value to the desired
433 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
434 // and each __CONFIG line should have the preceding semicolon removed when
435 // pasted into your source code.
437 //Program Configuration Register 1
438 // __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
440 //Program Configuration Register 2
441 // __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF
446 // ----- ADCON0 bits --------------------
449 unsigned char ADON:1;
450 unsigned char CHS3:1;
452 unsigned char CHS0:1;
453 unsigned char CHS1:1;
454 unsigned char CHS2:1;
455 unsigned char ADCS0:1;
456 unsigned char ADCS1:1;
461 unsigned char NOT_DONE:1;
471 unsigned char GO_DONE:1;
479 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
481 #define ADON ADCON0_bits.ADON
482 #define CHS3 ADCON0_bits.CHS3
483 #define GO ADCON0_bits.GO
484 #define NOT_DONE ADCON0_bits.NOT_DONE
485 #define GO_DONE ADCON0_bits.GO_DONE
486 #define CHS0 ADCON0_bits.CHS0
487 #define CHS1 ADCON0_bits.CHS1
488 #define CHS2 ADCON0_bits.CHS2
489 #define ADCS0 ADCON0_bits.ADCS0
490 #define ADCS1 ADCON0_bits.ADCS1
492 // ----- ADCON1 bits --------------------
495 unsigned char PCFG0:1;
496 unsigned char PCFG1:1;
497 unsigned char PCFG2:1;
498 unsigned char PCFG3:1;
499 unsigned char VCFG0:1;
500 unsigned char VCFG1:1;
501 unsigned char ADCS2:1;
502 unsigned char ADFM:1;
505 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
507 #define PCFG0 ADCON1_bits.PCFG0
508 #define PCFG1 ADCON1_bits.PCFG1
509 #define PCFG2 ADCON1_bits.PCFG2
510 #define PCFG3 ADCON1_bits.PCFG3
511 #define VCFG0 ADCON1_bits.VCFG0
512 #define VCFG1 ADCON1_bits.VCFG1
513 #define ADCS2 ADCON1_bits.ADCS2
514 #define ADFM ADCON1_bits.ADFM
516 // ----- ADCON2 bits --------------------
522 unsigned char ACQT0:1;
523 unsigned char ACQT1:1;
524 unsigned char ACQT2:1;
529 extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits;
531 #define ACQT0 ADCON2_bits.ACQT0
532 #define ACQT1 ADCON2_bits.ACQT1
533 #define ACQT2 ADCON2_bits.ACQT2
535 // ----- CCP1CON bits --------------------
538 unsigned char CCP1M0:1;
539 unsigned char CCP1M1:1;
540 unsigned char CCP1M2:1;
541 unsigned char CCP1M3:1;
542 unsigned char CCP1Y:1;
543 unsigned char CCP1X:1;
548 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
550 #define CCP1M0 CCP1CON_bits.CCP1M0
551 #define CCP1M1 CCP1CON_bits.CCP1M1
552 #define CCP1M2 CCP1CON_bits.CCP1M2
553 #define CCP1M3 CCP1CON_bits.CCP1M3
554 #define CCP1Y CCP1CON_bits.CCP1Y
555 #define CCP1X CCP1CON_bits.CCP1X
557 // ----- CCP2CON bits --------------------
560 unsigned char CCP2M0:1;
561 unsigned char CCP2M1:1;
562 unsigned char CCP2M2:1;
563 unsigned char CCP2M3:1;
564 unsigned char CCP2Y:1;
565 unsigned char CCP2X:1;
570 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
572 #define CCP2M0 CCP2CON_bits.CCP2M0
573 #define CCP2M1 CCP2CON_bits.CCP2M1
574 #define CCP2M2 CCP2CON_bits.CCP2M2
575 #define CCP2M3 CCP2CON_bits.CCP2M3
576 #define CCP2Y CCP2CON_bits.CCP2Y
577 #define CCP2X CCP2CON_bits.CCP2X
579 // ----- CCP3CON bits --------------------
582 unsigned char CCP3M0:1;
583 unsigned char CCP3M1:1;
584 unsigned char CCP3M2:1;
585 unsigned char CCP3M3:1;
586 unsigned char CCP3Y:1;
587 unsigned char CCP3X:1;
592 extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits;
594 #define CCP3M0 CCP3CON_bits.CCP3M0
595 #define CCP3M1 CCP3CON_bits.CCP3M1
596 #define CCP3M2 CCP3CON_bits.CCP3M2
597 #define CCP3M3 CCP3CON_bits.CCP3M3
598 #define CCP3Y CCP3CON_bits.CCP3Y
599 #define CCP3X CCP3CON_bits.CCP3X
601 // ----- CMCON bits --------------------
608 unsigned char C1INV:1;
609 unsigned char C2INV:1;
610 unsigned char C1OUT:1;
611 unsigned char C2OUT:1;
614 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
616 #define CM0 CMCON_bits.CM0
617 #define CM1 CMCON_bits.CM1
618 #define CM2 CMCON_bits.CM2
619 #define CIS CMCON_bits.CIS
620 #define C1INV CMCON_bits.C1INV
621 #define C2INV CMCON_bits.C2INV
622 #define C1OUT CMCON_bits.C1OUT
623 #define C2OUT CMCON_bits.C2OUT
625 // ----- CVRCON bits --------------------
628 unsigned char CVR0:1;
629 unsigned char CVR1:1;
630 unsigned char CVR2:1;
631 unsigned char CVR3:1;
633 unsigned char CVRR:1;
634 unsigned char CVROE:1;
635 unsigned char CVREN:1;
638 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
640 #define CVR0 CVRCON_bits.CVR0
641 #define CVR1 CVRCON_bits.CVR1
642 #define CVR2 CVRCON_bits.CVR2
643 #define CVR3 CVRCON_bits.CVR3
644 #define CVRR CVRCON_bits.CVRR
645 #define CVROE CVRCON_bits.CVROE
646 #define CVREN CVRCON_bits.CVREN
648 // ----- INTCON bits --------------------
651 unsigned char RBIF:1;
652 unsigned char INTF:1;
653 unsigned char T0IF:1;
654 unsigned char RBIE:1;
655 unsigned char INTE:1;
656 unsigned char T0IE:1;
657 unsigned char PEIE:1;
662 unsigned char INT0IF:1;
663 unsigned char TMR0IF:1;
665 unsigned char INT0IE:1;
666 unsigned char TMR0IE:1;
671 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
673 #define RBIF INTCON_bits.RBIF
674 #define INTF INTCON_bits.INTF
675 #define INT0IF INTCON_bits.INT0IF
676 #define T0IF INTCON_bits.T0IF
677 #define TMR0IF INTCON_bits.TMR0IF
678 #define RBIE INTCON_bits.RBIE
679 #define INTE INTCON_bits.INTE
680 #define INT0IE INTCON_bits.INT0IE
681 #define T0IE INTCON_bits.T0IE
682 #define TMR0IE INTCON_bits.TMR0IE
683 #define PEIE INTCON_bits.PEIE
684 #define GIE INTCON_bits.GIE
686 // ----- LVDCON bits --------------------
689 unsigned char LVDL0:1;
690 unsigned char LVDL1:1;
691 unsigned char LVDL2:1;
692 unsigned char LVDL3:1;
693 unsigned char LVDEN:1;
694 unsigned char IRVST:1;
699 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
701 #define LVDL0 LVDCON_bits.LVDL0
702 #define LVDL1 LVDCON_bits.LVDL1
703 #define LVDL2 LVDCON_bits.LVDL2
704 #define LVDL3 LVDCON_bits.LVDL3
705 #define LVDEN LVDCON_bits.LVDEN
706 #define IRVST LVDCON_bits.IRVST
708 // ----- OPTION_REG bits --------------------
715 unsigned char T0SE:1;
716 unsigned char T0CS:1;
717 unsigned char INTEDG:1;
718 unsigned char NOT_RBPU:1;
720 } __OPTION_REG_bits_t;
721 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
723 #define PS0 OPTION_REG_bits.PS0
724 #define PS1 OPTION_REG_bits.PS1
725 #define PS2 OPTION_REG_bits.PS2
726 #define PSA OPTION_REG_bits.PSA
727 #define T0SE OPTION_REG_bits.T0SE
728 #define T0CS OPTION_REG_bits.T0CS
729 #define INTEDG OPTION_REG_bits.INTEDG
730 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
732 // ----- OSCCON bits --------------------
735 unsigned char SCS0:1;
736 unsigned char SCS1:1;
737 unsigned char IOFS:1;
738 unsigned char OSTS:1;
739 unsigned char IRCF0:1;
740 unsigned char IRCF1:1;
741 unsigned char IRCF2:1;
745 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
747 #define SCS0 OSCCON_bits.SCS0
748 #define SCS1 OSCCON_bits.SCS1
749 #define IOFS OSCCON_bits.IOFS
750 #define OSTS OSCCON_bits.OSTS
751 #define IRCF0 OSCCON_bits.IRCF0
752 #define IRCF1 OSCCON_bits.IRCF1
753 #define IRCF2 OSCCON_bits.IRCF2
755 // ----- OSCTUNE bits --------------------
758 unsigned char TUN0:1;
759 unsigned char TUN1:1;
760 unsigned char TUN2:1;
761 unsigned char TUN3:1;
762 unsigned char TUN4:1;
763 unsigned char TUN5:1;
768 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
770 #define TUN0 OSCTUNE_bits.TUN0
771 #define TUN1 OSCTUNE_bits.TUN1
772 #define TUN2 OSCTUNE_bits.TUN2
773 #define TUN3 OSCTUNE_bits.TUN3
774 #define TUN4 OSCTUNE_bits.TUN4
775 #define TUN5 OSCTUNE_bits.TUN5
777 // ----- PCON bits --------------------
780 unsigned char NOT_BO:1;
781 unsigned char NOT_POR:1;
782 unsigned char SBOREN:1;
790 unsigned char NOT_BOR:1;
800 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
802 #define NOT_BO PCON_bits.NOT_BO
803 #define NOT_BOR PCON_bits.NOT_BOR
804 #define NOT_POR PCON_bits.NOT_POR
805 #define SBOREN PCON_bits.SBOREN
807 // ----- PIE1 bits --------------------
810 unsigned char TMR1IE:1;
811 unsigned char TMR2IE:1;
812 unsigned char CCP1IE:1;
813 unsigned char SSPIE:1;
814 unsigned char TXIE:1;
815 unsigned char RCIE:1;
816 unsigned char ADIE:1;
817 unsigned char PSPIE:1;
820 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
822 #define TMR1IE PIE1_bits.TMR1IE
823 #define TMR2IE PIE1_bits.TMR2IE
824 #define CCP1IE PIE1_bits.CCP1IE
825 #define SSPIE PIE1_bits.SSPIE
826 #define TXIE PIE1_bits.TXIE
827 #define RCIE PIE1_bits.RCIE
828 #define ADIE PIE1_bits.ADIE
829 #define PSPIE PIE1_bits.PSPIE
831 // ----- PIE2 bits --------------------
834 unsigned char CCP2IE:1;
835 unsigned char CCP3IE:1;
837 unsigned char BCLIE:1;
839 unsigned char LVDIE:1;
840 unsigned char CMIE:1;
841 unsigned char OSFIE:1;
844 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
846 #define CCP2IE PIE2_bits.CCP2IE
847 #define CCP3IE PIE2_bits.CCP3IE
848 #define BCLIE PIE2_bits.BCLIE
849 #define LVDIE PIE2_bits.LVDIE
850 #define CMIE PIE2_bits.CMIE
851 #define OSFIE PIE2_bits.OSFIE
853 // ----- PIR1 bits --------------------
856 unsigned char TMR1IF:1;
857 unsigned char TMR2IF:1;
858 unsigned char CCP1IF:1;
859 unsigned char SSPIF:1;
860 unsigned char TXIF:1;
861 unsigned char RCIF:1;
862 unsigned char ADIF:1;
863 unsigned char PSPIF:1;
866 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
868 #define TMR1IF PIR1_bits.TMR1IF
869 #define TMR2IF PIR1_bits.TMR2IF
870 #define CCP1IF PIR1_bits.CCP1IF
871 #define SSPIF PIR1_bits.SSPIF
872 #define TXIF PIR1_bits.TXIF
873 #define RCIF PIR1_bits.RCIF
874 #define ADIF PIR1_bits.ADIF
875 #define PSPIF PIR1_bits.PSPIF
877 // ----- PIR2 bits --------------------
880 unsigned char CCP2IF:1;
881 unsigned char CCP3IF:1;
883 unsigned char BCLIF:1;
885 unsigned char LVDIF:1;
886 unsigned char CMIF:1;
887 unsigned char OSFIF:1;
890 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
892 #define CCP2IF PIR2_bits.CCP2IF
893 #define CCP3IF PIR2_bits.CCP3IF
894 #define BCLIF PIR2_bits.BCLIF
895 #define LVDIF PIR2_bits.LVDIF
896 #define CMIF PIR2_bits.CMIF
897 #define OSFIF PIR2_bits.OSFIF
899 // ----- PMCON1 bits --------------------
912 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
914 #define RD PMCON1_bits.RD
916 // ----- RCSTA bits --------------------
919 unsigned char RX9D:1;
920 unsigned char OERR:1;
921 unsigned char FERR:1;
922 unsigned char ADDEN:1;
923 unsigned char CREN:1;
924 unsigned char SREN:1;
926 unsigned char SPEN:1;
929 unsigned char RCD8:1;
945 unsigned char NOT_RC8:1;
955 unsigned char RC8_9:1;
959 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
961 #define RX9D RCSTA_bits.RX9D
962 #define RCD8 RCSTA_bits.RCD8
963 #define OERR RCSTA_bits.OERR
964 #define FERR RCSTA_bits.FERR
965 #define ADDEN RCSTA_bits.ADDEN
966 #define CREN RCSTA_bits.CREN
967 #define SREN RCSTA_bits.SREN
968 #define RX9 RCSTA_bits.RX9
969 #define RC9 RCSTA_bits.RC9
970 #define NOT_RC8 RCSTA_bits.NOT_RC8
971 #define RC8_9 RCSTA_bits.RC8_9
972 #define SPEN RCSTA_bits.SPEN
974 // ----- SSPCON bits --------------------
977 unsigned char SSPM0:1;
978 unsigned char SSPM1:1;
979 unsigned char SSPM2:1;
980 unsigned char SSPM3:1;
982 unsigned char SSPEN:1;
983 unsigned char SSPOV:1;
984 unsigned char WCOL:1;
987 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
989 #define SSPM0 SSPCON_bits.SSPM0
990 #define SSPM1 SSPCON_bits.SSPM1
991 #define SSPM2 SSPCON_bits.SSPM2
992 #define SSPM3 SSPCON_bits.SSPM3
993 #define CKP SSPCON_bits.CKP
994 #define SSPEN SSPCON_bits.SSPEN
995 #define SSPOV SSPCON_bits.SSPOV
996 #define WCOL SSPCON_bits.WCOL
998 // ----- SSPCON2 bits --------------------
1001 unsigned char SEN:1;
1002 unsigned char RSEN:1;
1003 unsigned char PEN:1;
1004 unsigned char RCEN:1;
1005 unsigned char ACKEN:1;
1006 unsigned char ACKDT:1;
1007 unsigned char ACKSTAT:1;
1008 unsigned char GCEN:1;
1011 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
1013 #define SEN SSPCON2_bits.SEN
1014 #define RSEN SSPCON2_bits.RSEN
1015 #define PEN SSPCON2_bits.PEN
1016 #define RCEN SSPCON2_bits.RCEN
1017 #define ACKEN SSPCON2_bits.ACKEN
1018 #define ACKDT SSPCON2_bits.ACKDT
1019 #define ACKSTAT SSPCON2_bits.ACKSTAT
1020 #define GCEN SSPCON2_bits.GCEN
1022 // ----- SSPSTAT bits --------------------
1031 unsigned char CKE:1;
1032 unsigned char SMP:1;
1037 unsigned char I2C_READ:1;
1038 unsigned char I2C_START:1;
1039 unsigned char I2C_STOP:1;
1040 unsigned char I2C_DATA:1;
1047 unsigned char NOT_W:1;
1050 unsigned char NOT_A:1;
1057 unsigned char NOT_WRITE:1;
1060 unsigned char NOT_ADDRESS:1;
1067 unsigned char R_W:1;
1070 unsigned char D_A:1;
1077 unsigned char READ_WRITE:1;
1080 unsigned char DATA_ADDRESS:1;
1085 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1087 #define BF SSPSTAT_bits.BF
1088 #define UA SSPSTAT_bits.UA
1089 #define R SSPSTAT_bits.R
1090 #define I2C_READ SSPSTAT_bits.I2C_READ
1091 #define NOT_W SSPSTAT_bits.NOT_W
1092 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1093 #define R_W SSPSTAT_bits.R_W
1094 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1095 #define S SSPSTAT_bits.S
1096 #define I2C_START SSPSTAT_bits.I2C_START
1097 #define P SSPSTAT_bits.P
1098 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1099 #define D SSPSTAT_bits.D
1100 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1101 #define NOT_A SSPSTAT_bits.NOT_A
1102 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1103 #define D_A SSPSTAT_bits.D_A
1104 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1105 #define CKE SSPSTAT_bits.CKE
1106 #define SMP SSPSTAT_bits.SMP
1108 // ----- STATUS bits --------------------
1114 unsigned char NOT_PD:1;
1115 unsigned char NOT_TO:1;
1116 unsigned char RP0:1;
1117 unsigned char RP1:1;
1118 unsigned char IRP:1;
1121 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1123 #define C STATUS_bits.C
1124 #define DC STATUS_bits.DC
1125 #define Z STATUS_bits.Z
1126 #define NOT_PD STATUS_bits.NOT_PD
1127 #define NOT_TO STATUS_bits.NOT_TO
1128 #define RP0 STATUS_bits.RP0
1129 #define RP1 STATUS_bits.RP1
1130 #define IRP STATUS_bits.IRP
1132 // ----- T1CON bits --------------------
1135 unsigned char TMR1ON:1;
1136 unsigned char TMR1CS:1;
1137 unsigned char NOT_T1SYNC:1;
1138 unsigned char T1OSCEN:1;
1139 unsigned char T1CKPS0:1;
1140 unsigned char T1CKPS1:1;
1141 unsigned char T1RUN:1;
1147 unsigned char T1INSYNC:1;
1157 unsigned char T1SYNC:1;
1165 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1167 #define TMR1ON T1CON_bits.TMR1ON
1168 #define TMR1CS T1CON_bits.TMR1CS
1169 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1170 #define T1INSYNC T1CON_bits.T1INSYNC
1171 #define T1SYNC T1CON_bits.T1SYNC
1172 #define T1OSCEN T1CON_bits.T1OSCEN
1173 #define T1CKPS0 T1CON_bits.T1CKPS0
1174 #define T1CKPS1 T1CON_bits.T1CKPS1
1175 #define T1RUN T1CON_bits.T1RUN
1177 // ----- T2CON bits --------------------
1180 unsigned char T2CKPS0:1;
1181 unsigned char T2CKPS1:1;
1182 unsigned char TMR2ON:1;
1183 unsigned char TOUTPS0:1;
1184 unsigned char TOUTPS1:1;
1185 unsigned char TOUTPS2:1;
1186 unsigned char TOUTPS3:1;
1190 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1192 #define T2CKPS0 T2CON_bits.T2CKPS0
1193 #define T2CKPS1 T2CON_bits.T2CKPS1
1194 #define TMR2ON T2CON_bits.TMR2ON
1195 #define TOUTPS0 T2CON_bits.TOUTPS0
1196 #define TOUTPS1 T2CON_bits.TOUTPS1
1197 #define TOUTPS2 T2CON_bits.TOUTPS2
1198 #define TOUTPS3 T2CON_bits.TOUTPS3
1200 // ----- TRISE bits --------------------
1203 unsigned char TRISE0:1;
1204 unsigned char TRISE1:1;
1205 unsigned char TRISE2:1;
1206 unsigned char TRISE3:1;
1207 unsigned char PSPMODE:1;
1208 unsigned char IBOV:1;
1209 unsigned char OBF:1;
1210 unsigned char IBF:1;
1213 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1215 #define TRISE0 TRISE_bits.TRISE0
1216 #define TRISE1 TRISE_bits.TRISE1
1217 #define TRISE2 TRISE_bits.TRISE2
1218 #define TRISE3 TRISE_bits.TRISE3
1219 #define PSPMODE TRISE_bits.PSPMODE
1220 #define IBOV TRISE_bits.IBOV
1221 #define OBF TRISE_bits.OBF
1222 #define IBF TRISE_bits.IBF
1224 // ----- TXSTA bits --------------------
1227 unsigned char TX9D:1;
1228 unsigned char TRMT:1;
1229 unsigned char BRGH:1;
1231 unsigned char SYNC:1;
1232 unsigned char TXEN:1;
1233 unsigned char TX9:1;
1234 unsigned char CSRC:1;
1237 unsigned char TXD8:1;
1243 unsigned char NOT_TX8:1;
1253 unsigned char TX8_9:1;
1257 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1259 #define TX9D TXSTA_bits.TX9D
1260 #define TXD8 TXSTA_bits.TXD8
1261 #define TRMT TXSTA_bits.TRMT
1262 #define BRGH TXSTA_bits.BRGH
1263 #define SYNC TXSTA_bits.SYNC
1264 #define TXEN TXSTA_bits.TXEN
1265 #define TX9 TXSTA_bits.TX9
1266 #define NOT_TX8 TXSTA_bits.NOT_TX8
1267 #define TX8_9 TXSTA_bits.TX8_9
1268 #define CSRC TXSTA_bits.CSRC
1270 // ----- WDTCON bits --------------------
1273 unsigned char SWDTEN:1;
1274 unsigned char WDTPS0:1;
1275 unsigned char WDTPS1:1;
1276 unsigned char WDTPS2:1;
1277 unsigned char WDTPS3:1;
1283 unsigned char SWDTE:1;
1293 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1295 #define SWDTEN WDTCON_bits.SWDTEN
1296 #define SWDTE WDTCON_bits.SWDTE
1297 #define WDTPS0 WDTCON_bits.WDTPS0
1298 #define WDTPS1 WDTCON_bits.WDTPS1
1299 #define WDTPS2 WDTCON_bits.WDTPS2
1300 #define WDTPS3 WDTCON_bits.WDTPS3