2 // Register Declarations for Microchip 16F737 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define OSCCON_ADDR 0x008F
70 #define OSCTUNE_ADDR 0x0090
71 #define SSPCON2_ADDR 0x0091
72 #define PR2_ADDR 0x0092
73 #define SSPADD_ADDR 0x0093
74 #define SSPSTAT_ADDR 0x0094
75 #define CCPR3L_ADDR 0x0095
76 #define CCPR3H_ADDR 0x0096
77 #define CCP3CON_ADDR 0x0097
78 #define TXSTA_ADDR 0x0098
79 #define SPBRG_ADDR 0x0099
80 #define ADCON2_ADDR 0x009B
81 #define CMCON_ADDR 0x009C
82 #define CVRCON_ADDR 0x009D
83 #define ADRESL_ADDR 0x009E
84 #define ADCON1_ADDR 0x009F
85 #define WDTCON_ADDR 0x0105
86 #define LVDCON_ADDR 0x0109
87 #define PMDATA_ADDR 0x010C
88 #define PMADR_ADDR 0x010D
89 #define PMDATH_ADDR 0x010E
90 #define PMADRH_ADDR 0x010F
91 #define PMCON1_ADDR 0x018C
94 // Memory organization.
100 // P16F737.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
103 // This header file defines configurations, registers, and other useful bits of
104 // information for the PIC16F737 microcontroller. These names are taken to match
105 // the data sheets as closely as possible.
107 // Note that the processor must be selected before this file is
108 // included. The processor may be selected the following ways:
110 // 1. Command line switch:
111 // C:\ MPASM MYFILE.ASM /PIC16F737
112 // 2. LIST directive in the source file
114 // 3. Processor Type entry in the MPASM full-screen interface
116 //==========================================================================
120 //==========================================================================
123 //1.00 05/05/03 Initial Release
124 //1.01 10/21/03 Made changes to Program Memory register names.
125 //1.02 04/07/04 Added INT0IE & INT0IF bit names.
127 //==========================================================================
131 //==========================================================================
134 // MESSG "Processor-header file mismatch. Verify selected processor."
137 //==========================================================================
139 // Register Definitions
141 //==========================================================================
146 //----- Register Files------------------------------------------------------
148 extern __data __at (INDF_ADDR) volatile char INDF;
149 extern __sfr __at (TMR0_ADDR) TMR0;
150 extern __data __at (PCL_ADDR) volatile char PCL;
151 extern __sfr __at (STATUS_ADDR) STATUS;
152 extern __sfr __at (FSR_ADDR) FSR;
153 extern __sfr __at (PORTA_ADDR) PORTA;
154 extern __sfr __at (PORTB_ADDR) PORTB;
155 extern __sfr __at (PORTC_ADDR) PORTC;
156 extern __sfr __at (PORTD_ADDR) PORTD;
157 extern __sfr __at (PORTE_ADDR) PORTE;
158 extern __sfr __at (PCLATH_ADDR) PCLATH;
159 extern __sfr __at (INTCON_ADDR) INTCON;
160 extern __sfr __at (PIR1_ADDR) PIR1;
161 extern __sfr __at (PIR2_ADDR) PIR2;
162 extern __sfr __at (TMR1L_ADDR) TMR1L;
163 extern __sfr __at (TMR1H_ADDR) TMR1H;
164 extern __sfr __at (T1CON_ADDR) T1CON;
165 extern __sfr __at (TMR2_ADDR) TMR2;
166 extern __sfr __at (T2CON_ADDR) T2CON;
167 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
168 extern __sfr __at (SSPCON_ADDR) SSPCON;
169 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
170 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
171 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
172 extern __sfr __at (RCSTA_ADDR) RCSTA;
173 extern __sfr __at (TXREG_ADDR) TXREG;
174 extern __sfr __at (RCREG_ADDR) RCREG;
175 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
176 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
177 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
178 extern __sfr __at (ADRESH_ADDR) ADRESH;
179 extern __sfr __at (ADCON0_ADDR) ADCON0;
181 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
182 extern __sfr __at (TRISA_ADDR) TRISA;
183 extern __sfr __at (TRISB_ADDR) TRISB;
184 extern __sfr __at (TRISC_ADDR) TRISC;
185 extern __sfr __at (TRISD_ADDR) TRISD;
186 extern __sfr __at (TRISE_ADDR) TRISE;
187 extern __sfr __at (PIE1_ADDR) PIE1;
188 extern __sfr __at (PIE2_ADDR) PIE2;
189 extern __sfr __at (PCON_ADDR) PCON;
190 extern __sfr __at (OSCCON_ADDR) OSCCON;
191 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
192 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
193 extern __sfr __at (PR2_ADDR) PR2;
194 extern __sfr __at (SSPADD_ADDR) SSPADD;
195 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
196 extern __sfr __at (CCPR3L_ADDR) CCPR3L;
197 extern __sfr __at (CCPR3H_ADDR) CCPR3H;
198 extern __sfr __at (CCP3CON_ADDR) CCP3CON;
199 extern __sfr __at (TXSTA_ADDR) TXSTA;
200 extern __sfr __at (SPBRG_ADDR) SPBRG;
201 extern __sfr __at (ADCON2_ADDR) ADCON2;
202 extern __sfr __at (CMCON_ADDR) CMCON;
203 extern __sfr __at (CVRCON_ADDR) CVRCON;
204 extern __sfr __at (ADRESL_ADDR) ADRESL;
205 extern __sfr __at (ADCON1_ADDR) ADCON1;
207 extern __sfr __at (WDTCON_ADDR) WDTCON;
208 extern __sfr __at (LVDCON_ADDR) LVDCON;
209 extern __sfr __at (PMDATA_ADDR) PMDATA;
210 extern __sfr __at (PMADR_ADDR) PMADR;
211 extern __sfr __at (PMDATH_ADDR) PMDATH;
212 extern __sfr __at (PMADRH_ADDR) PMADRH;
214 extern __sfr __at (PMCON1_ADDR) PMCON1;
216 //----- STATUS Bits --------------------------------------------------------
219 //----- INTCON Bits --------------------------------------------------------
222 //----- PIR1 Bits ----------------------------------------------------------
225 //----- PIR2 Bits ----------------------------------------------------------
228 //----- T1CON Bits ---------------------------------------------------------
231 //----- T2CON Bits ---------------------------------------------------------
234 //----- SSPCON Bits --------------------------------------------------------
237 //----- CCP1CON Bits -------------------------------------------------------
240 //----- RCSTA Bits ---------------------------------------------------------
243 //----- CCP2CON Bits -------------------------------------------------------
246 //----- ADCON0 Bits --------------------------------------------------------
249 //----- OPTION Bits -----------------------------------------------------
252 //----- TRISE Bits ---------------------------------------------------------
255 //----- PIE1 Bits ----------------------------------------------------------
258 //----- PIE2 Bits ----------------------------------------------------------
261 //----- PCON Bits ----------------------------------------------------------
264 //----- OSCCON Bits -------------------------------------------------------
266 //----- OSCTUNE Bits -------------------------------------------------------
268 //----- SSPCON2 Bits --------------------------------------------------------
271 //----- SSPSTAT Bits -------------------------------------------------------
274 //----- CCP3CON Bits -------------------------------------------------------
277 //----- TXSTA Bits ---------------------------------------------------------
280 //----- ADCON2 Bits ---------------------------------------------------------
283 //----- CMCON Bits ---------------------------------------------------------
286 //----- CVRCON Bits --------------------------------------------------------
289 //----- ADCON1 Bits --------------------------------------------------------
292 //----- WDTCON Bits --------------------------------------------------------
295 //----- LVDCON Bits --------------------------------------------------------
298 //----- PMCON1 Bits --------------------------------------------------------
302 //==========================================================================
306 //==========================================================================
310 // __BADRAM H'88', H'9A'
311 // __BADRAM H'107'-H'108'
312 // __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
314 //==========================================================================
316 // Configuration Bits
318 //==========================================================================
320 #define _CONFIG1 0x2007
321 #define _CONFIG2 0x2008
323 //Configuration Byte 1 Options
324 #define _CP_ALL 0x1FFF
325 #define _CP_OFF 0x3FFF
326 #define _CCP2_RC1 0x3FFF
327 #define _CCP2_RB3 0x2FFF
328 #define _DEBUG_OFF 0x3FFF
329 #define _DEBUG_ON 0x37FF
330 #define _VBOR_2_0 0x3FFF
331 #define _VBOR_2_7 0x3F7F
332 #define _VBOR_4_2 0x3EFF
333 #define _VBOR_4_5 0x3E7F
334 #define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
335 #define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
336 #define _MCLR_ON 0x3FFF
337 #define _MCLR_OFF 0x3FDF
338 #define _PWRTE_OFF 0x3FFF
339 #define _PWRTE_ON 0x3FF7
340 #define _WDT_ON 0x3FFF
341 #define _WDT_OFF 0x3FFB
342 #define _EXTRC_CLKOUT 0x3FFF
343 #define _EXTRC_IO 0x3FFE
344 #define _INTRC_CLKOUT 0x3FFD
345 #define _INTRC_IO 0x3FFC
346 #define _EXTCLK 0x3FEF
347 #define _HS_OSC 0x3FEE
348 #define _XT_OSC 0x3FED
349 #define _LP_OSC 0x3FEC
351 //Configuration Byte 2 Options
352 #define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
353 #define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
354 #define _IESO_ON 0x3FFF
355 #define _IESO_OFF 0x3FFD
356 #define _FCMEN_ON 0x3FFF
357 #define _FCMEN_OFF 0x3FFE
360 //**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details)
361 //BOREN_1 & BORSEN_1 = BOR enabled and always on
362 //BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware
363 //BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2)
364 //BOREN_0 & BORSEN_0 = BOR disabled
367 // To use the Configuration Bits, place the following lines in your source code
368 // in the following format, and change the configuration value to the desired
369 // setting (such as CP_OFF to CP_ALL). These are currently commented out here
370 // and each __CONFIG line should have the preceding semicolon removed when
371 // pasted into your source code.
373 //Program Configuration Register 1
374 // __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
376 //Program Configuration Register 2
377 // __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF
382 // ----- ADCON0 bits --------------------
385 unsigned char ADON:1;
386 unsigned char CHS3:1;
388 unsigned char CHS0:1;
389 unsigned char CHS1:1;
390 unsigned char CHS2:1;
391 unsigned char ADCS0:1;
392 unsigned char ADCS1:1;
397 unsigned char NOT_DONE:1;
407 unsigned char GO_DONE:1;
415 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
417 #define ADON ADCON0_bits.ADON
418 #define CHS3 ADCON0_bits.CHS3
419 #define GO ADCON0_bits.GO
420 #define NOT_DONE ADCON0_bits.NOT_DONE
421 #define GO_DONE ADCON0_bits.GO_DONE
422 #define CHS0 ADCON0_bits.CHS0
423 #define CHS1 ADCON0_bits.CHS1
424 #define CHS2 ADCON0_bits.CHS2
425 #define ADCS0 ADCON0_bits.ADCS0
426 #define ADCS1 ADCON0_bits.ADCS1
428 // ----- ADCON1 bits --------------------
431 unsigned char PCFG0:1;
432 unsigned char PCFG1:1;
433 unsigned char PCFG2:1;
434 unsigned char PCFG3:1;
435 unsigned char VCFG0:1;
436 unsigned char VCFG1:1;
437 unsigned char ADCS2:1;
438 unsigned char ADFM:1;
441 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
443 #define PCFG0 ADCON1_bits.PCFG0
444 #define PCFG1 ADCON1_bits.PCFG1
445 #define PCFG2 ADCON1_bits.PCFG2
446 #define PCFG3 ADCON1_bits.PCFG3
447 #define VCFG0 ADCON1_bits.VCFG0
448 #define VCFG1 ADCON1_bits.VCFG1
449 #define ADCS2 ADCON1_bits.ADCS2
450 #define ADFM ADCON1_bits.ADFM
452 // ----- ADCON2 bits --------------------
458 unsigned char ACQT0:1;
459 unsigned char ACQT1:1;
460 unsigned char ACQT2:1;
465 extern volatile __ADCON2_bits_t __at(ADCON2_ADDR) ADCON2_bits;
467 #define ACQT0 ADCON2_bits.ACQT0
468 #define ACQT1 ADCON2_bits.ACQT1
469 #define ACQT2 ADCON2_bits.ACQT2
471 // ----- CCP1CON bits --------------------
474 unsigned char CCP1M0:1;
475 unsigned char CCP1M1:1;
476 unsigned char CCP1M2:1;
477 unsigned char CCP1M3:1;
478 unsigned char CCP1Y:1;
479 unsigned char CCP1X:1;
484 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
486 #define CCP1M0 CCP1CON_bits.CCP1M0
487 #define CCP1M1 CCP1CON_bits.CCP1M1
488 #define CCP1M2 CCP1CON_bits.CCP1M2
489 #define CCP1M3 CCP1CON_bits.CCP1M3
490 #define CCP1Y CCP1CON_bits.CCP1Y
491 #define CCP1X CCP1CON_bits.CCP1X
493 // ----- CCP2CON bits --------------------
496 unsigned char CCP2M0:1;
497 unsigned char CCP2M1:1;
498 unsigned char CCP2M2:1;
499 unsigned char CCP2M3:1;
500 unsigned char CCP2Y:1;
501 unsigned char CCP2X:1;
506 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
508 #define CCP2M0 CCP2CON_bits.CCP2M0
509 #define CCP2M1 CCP2CON_bits.CCP2M1
510 #define CCP2M2 CCP2CON_bits.CCP2M2
511 #define CCP2M3 CCP2CON_bits.CCP2M3
512 #define CCP2Y CCP2CON_bits.CCP2Y
513 #define CCP2X CCP2CON_bits.CCP2X
515 // ----- CCP3CON bits --------------------
518 unsigned char CCP3M0:1;
519 unsigned char CCP3M1:1;
520 unsigned char CCP3M2:1;
521 unsigned char CCP3M3:1;
522 unsigned char CCP3Y:1;
523 unsigned char CCP3X:1;
528 extern volatile __CCP3CON_bits_t __at(CCP3CON_ADDR) CCP3CON_bits;
530 #define CCP3M0 CCP3CON_bits.CCP3M0
531 #define CCP3M1 CCP3CON_bits.CCP3M1
532 #define CCP3M2 CCP3CON_bits.CCP3M2
533 #define CCP3M3 CCP3CON_bits.CCP3M3
534 #define CCP3Y CCP3CON_bits.CCP3Y
535 #define CCP3X CCP3CON_bits.CCP3X
537 // ----- CMCON bits --------------------
544 unsigned char C1INV:1;
545 unsigned char C2INV:1;
546 unsigned char C1OUT:1;
547 unsigned char C2OUT:1;
550 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
552 #define CM0 CMCON_bits.CM0
553 #define CM1 CMCON_bits.CM1
554 #define CM2 CMCON_bits.CM2
555 #define CIS CMCON_bits.CIS
556 #define C1INV CMCON_bits.C1INV
557 #define C2INV CMCON_bits.C2INV
558 #define C1OUT CMCON_bits.C1OUT
559 #define C2OUT CMCON_bits.C2OUT
561 // ----- CVRCON bits --------------------
564 unsigned char CVR0:1;
565 unsigned char CVR1:1;
566 unsigned char CVR2:1;
567 unsigned char CVR3:1;
569 unsigned char CVRR:1;
570 unsigned char CVROE:1;
571 unsigned char CVREN:1;
574 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
576 #define CVR0 CVRCON_bits.CVR0
577 #define CVR1 CVRCON_bits.CVR1
578 #define CVR2 CVRCON_bits.CVR2
579 #define CVR3 CVRCON_bits.CVR3
580 #define CVRR CVRCON_bits.CVRR
581 #define CVROE CVRCON_bits.CVROE
582 #define CVREN CVRCON_bits.CVREN
584 // ----- INTCON bits --------------------
587 unsigned char RBIF:1;
588 unsigned char INTF:1;
589 unsigned char T0IF:1;
590 unsigned char RBIE:1;
591 unsigned char INTE:1;
592 unsigned char T0IE:1;
593 unsigned char PEIE:1;
598 unsigned char INT0IF:1;
599 unsigned char TMR0IF:1;
601 unsigned char INT0IE:1;
602 unsigned char TMR0IE:1;
607 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
609 #define RBIF INTCON_bits.RBIF
610 #define INTF INTCON_bits.INTF
611 #define INT0IF INTCON_bits.INT0IF
612 #define T0IF INTCON_bits.T0IF
613 #define TMR0IF INTCON_bits.TMR0IF
614 #define RBIE INTCON_bits.RBIE
615 #define INTE INTCON_bits.INTE
616 #define INT0IE INTCON_bits.INT0IE
617 #define T0IE INTCON_bits.T0IE
618 #define TMR0IE INTCON_bits.TMR0IE
619 #define PEIE INTCON_bits.PEIE
620 #define GIE INTCON_bits.GIE
622 // ----- LVDCON bits --------------------
625 unsigned char LVDL0:1;
626 unsigned char LVDL1:1;
627 unsigned char LVDL2:1;
628 unsigned char LVDL3:1;
629 unsigned char LVDEN:1;
630 unsigned char IRVST:1;
635 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
637 #define LVDL0 LVDCON_bits.LVDL0
638 #define LVDL1 LVDCON_bits.LVDL1
639 #define LVDL2 LVDCON_bits.LVDL2
640 #define LVDL3 LVDCON_bits.LVDL3
641 #define LVDEN LVDCON_bits.LVDEN
642 #define IRVST LVDCON_bits.IRVST
644 // ----- OPTION_REG bits --------------------
651 unsigned char T0SE:1;
652 unsigned char T0CS:1;
653 unsigned char INTEDG:1;
654 unsigned char NOT_RBPU:1;
656 } __OPTION_REG_bits_t;
657 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
659 #define PS0 OPTION_REG_bits.PS0
660 #define PS1 OPTION_REG_bits.PS1
661 #define PS2 OPTION_REG_bits.PS2
662 #define PSA OPTION_REG_bits.PSA
663 #define T0SE OPTION_REG_bits.T0SE
664 #define T0CS OPTION_REG_bits.T0CS
665 #define INTEDG OPTION_REG_bits.INTEDG
666 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
668 // ----- OSCCON bits --------------------
671 unsigned char SCS0:1;
672 unsigned char SCS1:1;
673 unsigned char IOFS:1;
674 unsigned char OSTS:1;
675 unsigned char IRCF0:1;
676 unsigned char IRCF1:1;
677 unsigned char IRCF2:1;
681 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
683 #define SCS0 OSCCON_bits.SCS0
684 #define SCS1 OSCCON_bits.SCS1
685 #define IOFS OSCCON_bits.IOFS
686 #define OSTS OSCCON_bits.OSTS
687 #define IRCF0 OSCCON_bits.IRCF0
688 #define IRCF1 OSCCON_bits.IRCF1
689 #define IRCF2 OSCCON_bits.IRCF2
691 // ----- OSCTUNE bits --------------------
694 unsigned char TUN0:1;
695 unsigned char TUN1:1;
696 unsigned char TUN2:1;
697 unsigned char TUN3:1;
698 unsigned char TUN4:1;
699 unsigned char TUN5:1;
704 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
706 #define TUN0 OSCTUNE_bits.TUN0
707 #define TUN1 OSCTUNE_bits.TUN1
708 #define TUN2 OSCTUNE_bits.TUN2
709 #define TUN3 OSCTUNE_bits.TUN3
710 #define TUN4 OSCTUNE_bits.TUN4
711 #define TUN5 OSCTUNE_bits.TUN5
713 // ----- PCON bits --------------------
716 unsigned char NOT_BO:1;
717 unsigned char NOT_POR:1;
718 unsigned char SBOREN:1;
726 unsigned char NOT_BOR:1;
736 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
738 #define NOT_BO PCON_bits.NOT_BO
739 #define NOT_BOR PCON_bits.NOT_BOR
740 #define NOT_POR PCON_bits.NOT_POR
741 #define SBOREN PCON_bits.SBOREN
743 // ----- PIE1 bits --------------------
746 unsigned char TMR1IE:1;
747 unsigned char TMR2IE:1;
748 unsigned char CCP1IE:1;
749 unsigned char SSPIE:1;
750 unsigned char TXIE:1;
751 unsigned char RCIE:1;
752 unsigned char ADIE:1;
753 unsigned char PSPIE:1;
756 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
758 #define TMR1IE PIE1_bits.TMR1IE
759 #define TMR2IE PIE1_bits.TMR2IE
760 #define CCP1IE PIE1_bits.CCP1IE
761 #define SSPIE PIE1_bits.SSPIE
762 #define TXIE PIE1_bits.TXIE
763 #define RCIE PIE1_bits.RCIE
764 #define ADIE PIE1_bits.ADIE
765 #define PSPIE PIE1_bits.PSPIE
767 // ----- PIE2 bits --------------------
770 unsigned char CCP2IE:1;
771 unsigned char CCP3IE:1;
773 unsigned char BCLIE:1;
775 unsigned char LVDIE:1;
776 unsigned char CMIE:1;
777 unsigned char OSFIE:1;
780 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
782 #define CCP2IE PIE2_bits.CCP2IE
783 #define CCP3IE PIE2_bits.CCP3IE
784 #define BCLIE PIE2_bits.BCLIE
785 #define LVDIE PIE2_bits.LVDIE
786 #define CMIE PIE2_bits.CMIE
787 #define OSFIE PIE2_bits.OSFIE
789 // ----- PIR1 bits --------------------
792 unsigned char TMR1IF:1;
793 unsigned char TMR2IF:1;
794 unsigned char CCP1IF:1;
795 unsigned char SSPIF:1;
796 unsigned char TXIF:1;
797 unsigned char RCIF:1;
798 unsigned char ADIF:1;
799 unsigned char PSPIF:1;
802 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
804 #define TMR1IF PIR1_bits.TMR1IF
805 #define TMR2IF PIR1_bits.TMR2IF
806 #define CCP1IF PIR1_bits.CCP1IF
807 #define SSPIF PIR1_bits.SSPIF
808 #define TXIF PIR1_bits.TXIF
809 #define RCIF PIR1_bits.RCIF
810 #define ADIF PIR1_bits.ADIF
811 #define PSPIF PIR1_bits.PSPIF
813 // ----- PIR2 bits --------------------
816 unsigned char CCP2IF:1;
817 unsigned char CCP3IF:1;
819 unsigned char BCLIF:1;
821 unsigned char LVDIF:1;
822 unsigned char CMIF:1;
823 unsigned char OSFIF:1;
826 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
828 #define CCP2IF PIR2_bits.CCP2IF
829 #define CCP3IF PIR2_bits.CCP3IF
830 #define BCLIF PIR2_bits.BCLIF
831 #define LVDIF PIR2_bits.LVDIF
832 #define CMIF PIR2_bits.CMIF
833 #define OSFIF PIR2_bits.OSFIF
835 // ----- PMCON1 bits --------------------
848 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
850 #define RD PMCON1_bits.RD
852 // ----- RCSTA bits --------------------
855 unsigned char RX9D:1;
856 unsigned char OERR:1;
857 unsigned char FERR:1;
858 unsigned char ADDEN:1;
859 unsigned char CREN:1;
860 unsigned char SREN:1;
862 unsigned char SPEN:1;
865 unsigned char RCD8:1;
881 unsigned char NOT_RC8:1;
891 unsigned char RC8_9:1;
895 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
897 #define RX9D RCSTA_bits.RX9D
898 #define RCD8 RCSTA_bits.RCD8
899 #define OERR RCSTA_bits.OERR
900 #define FERR RCSTA_bits.FERR
901 #define ADDEN RCSTA_bits.ADDEN
902 #define CREN RCSTA_bits.CREN
903 #define SREN RCSTA_bits.SREN
904 #define RX9 RCSTA_bits.RX9
905 #define RC9 RCSTA_bits.RC9
906 #define NOT_RC8 RCSTA_bits.NOT_RC8
907 #define RC8_9 RCSTA_bits.RC8_9
908 #define SPEN RCSTA_bits.SPEN
910 // ----- SSPCON bits --------------------
913 unsigned char SSPM0:1;
914 unsigned char SSPM1:1;
915 unsigned char SSPM2:1;
916 unsigned char SSPM3:1;
918 unsigned char SSPEN:1;
919 unsigned char SSPOV:1;
920 unsigned char WCOL:1;
923 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
925 #define SSPM0 SSPCON_bits.SSPM0
926 #define SSPM1 SSPCON_bits.SSPM1
927 #define SSPM2 SSPCON_bits.SSPM2
928 #define SSPM3 SSPCON_bits.SSPM3
929 #define CKP SSPCON_bits.CKP
930 #define SSPEN SSPCON_bits.SSPEN
931 #define SSPOV SSPCON_bits.SSPOV
932 #define WCOL SSPCON_bits.WCOL
934 // ----- SSPCON2 bits --------------------
938 unsigned char RSEN:1;
940 unsigned char RCEN:1;
941 unsigned char ACKEN:1;
942 unsigned char ACKDT:1;
943 unsigned char ACKSTAT:1;
944 unsigned char GCEN:1;
947 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
949 #define SEN SSPCON2_bits.SEN
950 #define RSEN SSPCON2_bits.RSEN
951 #define PEN SSPCON2_bits.PEN
952 #define RCEN SSPCON2_bits.RCEN
953 #define ACKEN SSPCON2_bits.ACKEN
954 #define ACKDT SSPCON2_bits.ACKDT
955 #define ACKSTAT SSPCON2_bits.ACKSTAT
956 #define GCEN SSPCON2_bits.GCEN
958 // ----- SSPSTAT bits --------------------
973 unsigned char I2C_READ:1;
974 unsigned char I2C_START:1;
975 unsigned char I2C_STOP:1;
976 unsigned char I2C_DATA:1;
983 unsigned char NOT_W:1;
986 unsigned char NOT_A:1;
993 unsigned char NOT_WRITE:1;
996 unsigned char NOT_ADDRESS:1;
1003 unsigned char R_W:1;
1006 unsigned char D_A:1;
1013 unsigned char READ_WRITE:1;
1016 unsigned char DATA_ADDRESS:1;
1021 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1023 #define BF SSPSTAT_bits.BF
1024 #define UA SSPSTAT_bits.UA
1025 #define R SSPSTAT_bits.R
1026 #define I2C_READ SSPSTAT_bits.I2C_READ
1027 #define NOT_W SSPSTAT_bits.NOT_W
1028 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1029 #define R_W SSPSTAT_bits.R_W
1030 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1031 #define S SSPSTAT_bits.S
1032 #define I2C_START SSPSTAT_bits.I2C_START
1033 #define P SSPSTAT_bits.P
1034 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1035 #define D SSPSTAT_bits.D
1036 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1037 #define NOT_A SSPSTAT_bits.NOT_A
1038 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1039 #define D_A SSPSTAT_bits.D_A
1040 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1041 #define CKE SSPSTAT_bits.CKE
1042 #define SMP SSPSTAT_bits.SMP
1044 // ----- STATUS bits --------------------
1050 unsigned char NOT_PD:1;
1051 unsigned char NOT_TO:1;
1052 unsigned char RP0:1;
1053 unsigned char RP1:1;
1054 unsigned char IRP:1;
1057 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1059 #define C STATUS_bits.C
1060 #define DC STATUS_bits.DC
1061 #define Z STATUS_bits.Z
1062 #define NOT_PD STATUS_bits.NOT_PD
1063 #define NOT_TO STATUS_bits.NOT_TO
1064 #define RP0 STATUS_bits.RP0
1065 #define RP1 STATUS_bits.RP1
1066 #define IRP STATUS_bits.IRP
1068 // ----- T1CON bits --------------------
1071 unsigned char TMR1ON:1;
1072 unsigned char TMR1CS:1;
1073 unsigned char NOT_T1SYNC:1;
1074 unsigned char T1OSCEN:1;
1075 unsigned char T1CKPS0:1;
1076 unsigned char T1CKPS1:1;
1077 unsigned char T1RUN:1;
1083 unsigned char T1INSYNC:1;
1093 unsigned char T1SYNC:1;
1101 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1103 #define TMR1ON T1CON_bits.TMR1ON
1104 #define TMR1CS T1CON_bits.TMR1CS
1105 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1106 #define T1INSYNC T1CON_bits.T1INSYNC
1107 #define T1SYNC T1CON_bits.T1SYNC
1108 #define T1OSCEN T1CON_bits.T1OSCEN
1109 #define T1CKPS0 T1CON_bits.T1CKPS0
1110 #define T1CKPS1 T1CON_bits.T1CKPS1
1111 #define T1RUN T1CON_bits.T1RUN
1113 // ----- T2CON bits --------------------
1116 unsigned char T2CKPS0:1;
1117 unsigned char T2CKPS1:1;
1118 unsigned char TMR2ON:1;
1119 unsigned char TOUTPS0:1;
1120 unsigned char TOUTPS1:1;
1121 unsigned char TOUTPS2:1;
1122 unsigned char TOUTPS3:1;
1126 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1128 #define T2CKPS0 T2CON_bits.T2CKPS0
1129 #define T2CKPS1 T2CON_bits.T2CKPS1
1130 #define TMR2ON T2CON_bits.TMR2ON
1131 #define TOUTPS0 T2CON_bits.TOUTPS0
1132 #define TOUTPS1 T2CON_bits.TOUTPS1
1133 #define TOUTPS2 T2CON_bits.TOUTPS2
1134 #define TOUTPS3 T2CON_bits.TOUTPS3
1136 // ----- TRISE bits --------------------
1139 unsigned char TRISE0:1;
1140 unsigned char TRISE1:1;
1141 unsigned char TRISE2:1;
1142 unsigned char TRISE3:1;
1143 unsigned char PSPMODE:1;
1144 unsigned char IBOV:1;
1145 unsigned char OBF:1;
1146 unsigned char IBF:1;
1149 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1151 #define TRISE0 TRISE_bits.TRISE0
1152 #define TRISE1 TRISE_bits.TRISE1
1153 #define TRISE2 TRISE_bits.TRISE2
1154 #define TRISE3 TRISE_bits.TRISE3
1155 #define PSPMODE TRISE_bits.PSPMODE
1156 #define IBOV TRISE_bits.IBOV
1157 #define OBF TRISE_bits.OBF
1158 #define IBF TRISE_bits.IBF
1160 // ----- TXSTA bits --------------------
1163 unsigned char TX9D:1;
1164 unsigned char TRMT:1;
1165 unsigned char BRGH:1;
1167 unsigned char SYNC:1;
1168 unsigned char TXEN:1;
1169 unsigned char TX9:1;
1170 unsigned char CSRC:1;
1173 unsigned char TXD8:1;
1179 unsigned char NOT_TX8:1;
1189 unsigned char TX8_9:1;
1193 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1195 #define TX9D TXSTA_bits.TX9D
1196 #define TXD8 TXSTA_bits.TXD8
1197 #define TRMT TXSTA_bits.TRMT
1198 #define BRGH TXSTA_bits.BRGH
1199 #define SYNC TXSTA_bits.SYNC
1200 #define TXEN TXSTA_bits.TXEN
1201 #define TX9 TXSTA_bits.TX9
1202 #define NOT_TX8 TXSTA_bits.NOT_TX8
1203 #define TX8_9 TXSTA_bits.TX8_9
1204 #define CSRC TXSTA_bits.CSRC
1206 // ----- WDTCON bits --------------------
1209 unsigned char SWDTEN:1;
1210 unsigned char WDTPS0:1;
1211 unsigned char WDTPS1:1;
1212 unsigned char WDTPS2:1;
1213 unsigned char WDTPS3:1;
1219 unsigned char SWDTE:1;
1229 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1231 #define SWDTEN WDTCON_bits.SWDTEN
1232 #define SWDTE WDTCON_bits.SWDTE
1233 #define WDTPS0 WDTCON_bits.WDTPS0
1234 #define WDTPS1 WDTCON_bits.WDTPS1
1235 #define WDTPS2 WDTCON_bits.WDTPS2
1236 #define WDTPS3 WDTCON_bits.WDTPS3