2 // Register Declarations for Microchip 16F73 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define SSPADD_ADDR 0x0093
67 #define SSPSTAT_ADDR 0x0094
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
71 #define PMDATA_ADDR 0x010C
72 #define PMADR_ADDR 0x010D
73 #define PMDATH_ADDR 0x010E
74 #define PMADRH_ADDR 0x010F
75 #define PMCON1_ADDR 0x018C
78 // Memory organization.
84 // P16F73.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
87 // This header file defines configurations, registers, and other useful bits of
88 // information for the PIC16F73 microcontroller. These names are taken to match
89 // the data sheets as closely as possible.
91 // Note that the processor must be selected before this file is
92 // included. The processor may be selected the following ways:
94 // 1. Command line switch:
95 // C:\ MPASM MYFILE.ASM /PIC16F73
96 // 2. LIST directive in the source file
98 // 3. Processor Type entry in the MPASM full-screen interface
100 //==========================================================================
104 //==========================================================================
108 //1.00 00/00/00 Initial Release
110 //==========================================================================
114 //==========================================================================
117 // MESSG "Processor-header file mismatch. Verify selected processor."
120 //==========================================================================
122 // Register Definitions
124 //==========================================================================
129 //----- Register Files------------------------------------------------------
131 extern __sfr __at (INDF_ADDR) INDF;
132 extern __sfr __at (TMR0_ADDR) TMR0;
133 extern __sfr __at (PCL_ADDR) PCL;
134 extern __sfr __at (STATUS_ADDR) STATUS;
135 extern __sfr __at (FSR_ADDR) FSR;
136 extern __sfr __at (PORTA_ADDR) PORTA;
137 extern __sfr __at (PORTB_ADDR) PORTB;
138 extern __sfr __at (PORTC_ADDR) PORTC;
139 extern __sfr __at (PCLATH_ADDR) PCLATH;
140 extern __sfr __at (INTCON_ADDR) INTCON;
141 extern __sfr __at (PIR1_ADDR) PIR1;
142 extern __sfr __at (PIR2_ADDR) PIR2;
143 extern __sfr __at (TMR1L_ADDR) TMR1L;
144 extern __sfr __at (TMR1H_ADDR) TMR1H;
145 extern __sfr __at (T1CON_ADDR) T1CON;
146 extern __sfr __at (TMR2_ADDR) TMR2;
147 extern __sfr __at (T2CON_ADDR) T2CON;
148 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
149 extern __sfr __at (SSPCON_ADDR) SSPCON;
150 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
151 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
152 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
153 extern __sfr __at (RCSTA_ADDR) RCSTA;
154 extern __sfr __at (TXREG_ADDR) TXREG;
155 extern __sfr __at (RCREG_ADDR) RCREG;
156 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
157 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
158 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
159 extern __sfr __at (ADRES_ADDR) ADRES;
160 extern __sfr __at (ADCON0_ADDR) ADCON0;
162 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
163 extern __sfr __at (TRISA_ADDR) TRISA;
164 extern __sfr __at (TRISB_ADDR) TRISB;
165 extern __sfr __at (TRISC_ADDR) TRISC;
166 extern __sfr __at (PIE1_ADDR) PIE1;
167 extern __sfr __at (PIE2_ADDR) PIE2;
168 extern __sfr __at (PCON_ADDR) PCON;
169 extern __sfr __at (PR2_ADDR) PR2;
170 extern __sfr __at (SSPADD_ADDR) SSPADD;
171 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
172 extern __sfr __at (TXSTA_ADDR) TXSTA;
173 extern __sfr __at (SPBRG_ADDR) SPBRG;
174 extern __sfr __at (ADCON1_ADDR) ADCON1;
176 extern __sfr __at (PMDATA_ADDR) PMDATA;
177 extern __sfr __at (PMADR_ADDR) PMADR;
178 extern __sfr __at (PMDATH_ADDR) PMDATH;
179 extern __sfr __at (PMADRH_ADDR) PMADRH;
181 extern __sfr __at (PMCON1_ADDR) PMCON1;
183 //----- STATUS Bits --------------------------------------------------------
186 //----- INTCON Bits --------------------------------------------------------
189 //----- PIR1 Bits ----------------------------------------------------------
192 //----- PIR2 Bits ----------------------------------------------------------
195 //----- T1CON Bits ---------------------------------------------------------
198 //----- T2CON Bits ---------------------------------------------------------
201 //----- SSPCON Bits --------------------------------------------------------
204 //----- CCP1CON Bits -------------------------------------------------------
207 //----- RCSTA Bits ---------------------------------------------------------
210 //----- CCP2CON Bits -------------------------------------------------------
213 //----- ADCON0 Bits --------------------------------------------------------
216 //----- OPTION Bits --------------------------------------------------------
219 //----- PIE1 Bits ----------------------------------------------------------
222 //----- PIE2 Bits ----------------------------------------------------------
225 //----- PCON Bits ----------------------------------------------------------
228 //----- SSPSTAT Bits -------------------------------------------------------
231 //----- TXSTA Bits ---------------------------------------------------------
234 //----- ADCON1 Bits --------------------------------------------------------
237 //----- PMCON1 Bits --------------------------------------------------------
239 //==========================================================================
243 //==========================================================================
246 // __BADRAM H'08'-H'09'
247 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
248 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
249 // __BADRAM H'185', H'187'-H'189', H'18D'-H'19F'
251 //==========================================================================
253 // Configuration Bits
255 //==========================================================================
257 #define _BODEN_ON 0x3FFF
258 #define _BODEN_OFF 0x3FBF
259 #define _CP_ALL 0x3FEF
260 #define _CP_OFF 0x3FFF
261 #define _PWRTE_OFF 0x3FFF
262 #define _PWRTE_ON 0x3FF7
263 #define _WDT_ON 0x3FFF
264 #define _WDT_OFF 0x3FFB
265 #define _LP_OSC 0x3FFC
266 #define _XT_OSC 0x3FFD
267 #define _HS_OSC 0x3FFE
268 #define _RC_OSC 0x3FFF
273 // ----- ADCON0 bits --------------------
276 unsigned char ADON:1;
279 unsigned char CHS0:1;
280 unsigned char CHS1:1;
281 unsigned char CHS2:1;
282 unsigned char ADCS0:1;
283 unsigned char ADCS1:1;
288 unsigned char NOT_DONE:1;
298 unsigned char GO_DONE:1;
306 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
308 #define ADON ADCON0_bits.ADON
309 #define GO ADCON0_bits.GO
310 #define NOT_DONE ADCON0_bits.NOT_DONE
311 #define GO_DONE ADCON0_bits.GO_DONE
312 #define CHS0 ADCON0_bits.CHS0
313 #define CHS1 ADCON0_bits.CHS1
314 #define CHS2 ADCON0_bits.CHS2
315 #define ADCS0 ADCON0_bits.ADCS0
316 #define ADCS1 ADCON0_bits.ADCS1
318 // ----- ADCON1 bits --------------------
321 unsigned char PCFG0:1;
322 unsigned char PCFG1:1;
323 unsigned char PCFG2:1;
331 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
333 #define PCFG0 ADCON1_bits.PCFG0
334 #define PCFG1 ADCON1_bits.PCFG1
335 #define PCFG2 ADCON1_bits.PCFG2
337 // ----- CCP1CON bits --------------------
340 unsigned char CCP1M0:1;
341 unsigned char CCP1M1:1;
342 unsigned char CCP1M2:1;
343 unsigned char CCP1M3:1;
344 unsigned char CCP1Y:1;
345 unsigned char CCP1X:1;
350 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
352 #define CCP1M0 CCP1CON_bits.CCP1M0
353 #define CCP1M1 CCP1CON_bits.CCP1M1
354 #define CCP1M2 CCP1CON_bits.CCP1M2
355 #define CCP1M3 CCP1CON_bits.CCP1M3
356 #define CCP1Y CCP1CON_bits.CCP1Y
357 #define CCP1X CCP1CON_bits.CCP1X
359 // ----- CCP2CON bits --------------------
362 unsigned char CCP2M0:1;
363 unsigned char CCP2M1:1;
364 unsigned char CCP2M2:1;
365 unsigned char CCP2M3:1;
366 unsigned char CCP2Y:1;
367 unsigned char CCP2X:1;
372 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
374 #define CCP2M0 CCP2CON_bits.CCP2M0
375 #define CCP2M1 CCP2CON_bits.CCP2M1
376 #define CCP2M2 CCP2CON_bits.CCP2M2
377 #define CCP2M3 CCP2CON_bits.CCP2M3
378 #define CCP2Y CCP2CON_bits.CCP2Y
379 #define CCP2X CCP2CON_bits.CCP2X
381 // ----- INTCON bits --------------------
384 unsigned char RBIF:1;
385 unsigned char INTF:1;
386 unsigned char T0IF:1;
387 unsigned char RBIE:1;
388 unsigned char INTE:1;
389 unsigned char T0IE:1;
390 unsigned char PEIE:1;
394 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
396 #define RBIF INTCON_bits.RBIF
397 #define INTF INTCON_bits.INTF
398 #define T0IF INTCON_bits.T0IF
399 #define RBIE INTCON_bits.RBIE
400 #define INTE INTCON_bits.INTE
401 #define T0IE INTCON_bits.T0IE
402 #define PEIE INTCON_bits.PEIE
403 #define GIE INTCON_bits.GIE
405 // ----- OPTION_REG bits --------------------
412 unsigned char T0SE:1;
413 unsigned char T0CS:1;
414 unsigned char INTEDG:1;
415 unsigned char NOT_RBPU:1;
417 } __OPTION_REG_bits_t;
418 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
420 #define PS0 OPTION_REG_bits.PS0
421 #define PS1 OPTION_REG_bits.PS1
422 #define PS2 OPTION_REG_bits.PS2
423 #define PSA OPTION_REG_bits.PSA
424 #define T0SE OPTION_REG_bits.T0SE
425 #define T0CS OPTION_REG_bits.T0CS
426 #define INTEDG OPTION_REG_bits.INTEDG
427 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
429 // ----- PCON bits --------------------
432 unsigned char NOT_BO:1;
433 unsigned char NOT_POR:1;
442 unsigned char NOT_BOR:1;
452 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
454 #define NOT_BO PCON_bits.NOT_BO
455 #define NOT_BOR PCON_bits.NOT_BOR
456 #define NOT_POR PCON_bits.NOT_POR
458 // ----- PIE1 bits --------------------
461 unsigned char TMR1IE:1;
462 unsigned char TMR2IE:1;
463 unsigned char CCP1IE:1;
464 unsigned char SSPIE:1;
465 unsigned char TXIE:1;
466 unsigned char RCIE:1;
467 unsigned char ADIE:1;
471 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
473 #define TMR1IE PIE1_bits.TMR1IE
474 #define TMR2IE PIE1_bits.TMR2IE
475 #define CCP1IE PIE1_bits.CCP1IE
476 #define SSPIE PIE1_bits.SSPIE
477 #define TXIE PIE1_bits.TXIE
478 #define RCIE PIE1_bits.RCIE
479 #define ADIE PIE1_bits.ADIE
481 // ----- PIE2 bits --------------------
484 unsigned char CCP2IE:1;
494 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
496 #define CCP2IE PIE2_bits.CCP2IE
498 // ----- PIR1 bits --------------------
501 unsigned char TMR1IF:1;
502 unsigned char TMR2IF:1;
503 unsigned char CCP1IF:1;
504 unsigned char SSPIF:1;
505 unsigned char TXIF:1;
506 unsigned char RCIF:1;
507 unsigned char ADIF:1;
511 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
513 #define TMR1IF PIR1_bits.TMR1IF
514 #define TMR2IF PIR1_bits.TMR2IF
515 #define CCP1IF PIR1_bits.CCP1IF
516 #define SSPIF PIR1_bits.SSPIF
517 #define TXIF PIR1_bits.TXIF
518 #define RCIF PIR1_bits.RCIF
519 #define ADIF PIR1_bits.ADIF
521 // ----- PIR2 bits --------------------
524 unsigned char CCP2IF:1;
534 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
536 #define CCP2IF PIR2_bits.CCP2IF
538 // ----- PMCON1 bits --------------------
551 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
553 #define RD PMCON1_bits.RD
555 // ----- PORTA bits --------------------
568 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
570 #define RA0 PORTA_bits.RA0
571 #define RA1 PORTA_bits.RA1
572 #define RA2 PORTA_bits.RA2
573 #define RA3 PORTA_bits.RA3
574 #define RA4 PORTA_bits.RA4
575 #define RA5 PORTA_bits.RA5
577 // ----- PORTB bits --------------------
590 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
592 #define RB0 PORTB_bits.RB0
593 #define RB1 PORTB_bits.RB1
594 #define RB2 PORTB_bits.RB2
595 #define RB3 PORTB_bits.RB3
596 #define RB4 PORTB_bits.RB4
597 #define RB5 PORTB_bits.RB5
598 #define RB6 PORTB_bits.RB6
599 #define RB7 PORTB_bits.RB7
601 // ----- PORTC bits --------------------
614 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
616 #define RC0 PORTC_bits.RC0
617 #define RC1 PORTC_bits.RC1
618 #define RC2 PORTC_bits.RC2
619 #define RC3 PORTC_bits.RC3
620 #define RC4 PORTC_bits.RC4
621 #define RC5 PORTC_bits.RC5
622 #define RC6 PORTC_bits.RC6
623 #define RC7 PORTC_bits.RC7
625 // ----- RCSTA bits --------------------
628 unsigned char RX9D:1;
629 unsigned char OERR:1;
630 unsigned char FERR:1;
632 unsigned char CREN:1;
633 unsigned char SREN:1;
635 unsigned char SPEN:1;
638 unsigned char RCD8:1;
654 unsigned char NOT_RC8:1;
664 unsigned char RC8_9:1;
668 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
670 #define RX9D RCSTA_bits.RX9D
671 #define RCD8 RCSTA_bits.RCD8
672 #define OERR RCSTA_bits.OERR
673 #define FERR RCSTA_bits.FERR
674 #define CREN RCSTA_bits.CREN
675 #define SREN RCSTA_bits.SREN
676 #define RX9 RCSTA_bits.RX9
677 #define RC9 RCSTA_bits.RC9
678 #define NOT_RC8 RCSTA_bits.NOT_RC8
679 #define RC8_9 RCSTA_bits.RC8_9
680 #define SPEN RCSTA_bits.SPEN
682 // ----- SSPCON bits --------------------
685 unsigned char SSPM0:1;
686 unsigned char SSPM1:1;
687 unsigned char SSPM2:1;
688 unsigned char SSPM3:1;
690 unsigned char SSPEN:1;
691 unsigned char SSPOV:1;
692 unsigned char WCOL:1;
695 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
697 #define SSPM0 SSPCON_bits.SSPM0
698 #define SSPM1 SSPCON_bits.SSPM1
699 #define SSPM2 SSPCON_bits.SSPM2
700 #define SSPM3 SSPCON_bits.SSPM3
701 #define CKP SSPCON_bits.CKP
702 #define SSPEN SSPCON_bits.SSPEN
703 #define SSPOV SSPCON_bits.SSPOV
704 #define WCOL SSPCON_bits.WCOL
706 // ----- SSPSTAT bits --------------------
721 unsigned char I2C_READ:1;
722 unsigned char I2C_START:1;
723 unsigned char I2C_STOP:1;
724 unsigned char I2C_DATA:1;
731 unsigned char NOT_W:1;
734 unsigned char NOT_A:1;
741 unsigned char NOT_WRITE:1;
744 unsigned char NOT_ADDRESS:1;
761 unsigned char READ_WRITE:1;
764 unsigned char DATA_ADDRESS:1;
769 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
771 #define BF SSPSTAT_bits.BF
772 #define UA SSPSTAT_bits.UA
773 #define R SSPSTAT_bits.R
774 #define I2C_READ SSPSTAT_bits.I2C_READ
775 #define NOT_W SSPSTAT_bits.NOT_W
776 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
777 #define R_W SSPSTAT_bits.R_W
778 #define READ_WRITE SSPSTAT_bits.READ_WRITE
779 #define S SSPSTAT_bits.S
780 #define I2C_START SSPSTAT_bits.I2C_START
781 #define P SSPSTAT_bits.P
782 #define I2C_STOP SSPSTAT_bits.I2C_STOP
783 #define D SSPSTAT_bits.D
784 #define I2C_DATA SSPSTAT_bits.I2C_DATA
785 #define NOT_A SSPSTAT_bits.NOT_A
786 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
787 #define D_A SSPSTAT_bits.D_A
788 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
789 #define CKE SSPSTAT_bits.CKE
790 #define SMP SSPSTAT_bits.SMP
792 // ----- STATUS bits --------------------
798 unsigned char NOT_PD:1;
799 unsigned char NOT_TO:1;
805 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
807 #define C STATUS_bits.C
808 #define DC STATUS_bits.DC
809 #define Z STATUS_bits.Z
810 #define NOT_PD STATUS_bits.NOT_PD
811 #define NOT_TO STATUS_bits.NOT_TO
812 #define RP0 STATUS_bits.RP0
813 #define RP1 STATUS_bits.RP1
814 #define IRP STATUS_bits.IRP
816 // ----- T1CON bits --------------------
819 unsigned char TMR1ON:1;
820 unsigned char TMR1CS:1;
821 unsigned char NOT_T1SYNC:1;
822 unsigned char T1OSCEN:1;
823 unsigned char T1CKPS0:1;
824 unsigned char T1CKPS1:1;
831 unsigned char T1INSYNC:1;
839 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
841 #define TMR1ON T1CON_bits.TMR1ON
842 #define TMR1CS T1CON_bits.TMR1CS
843 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
844 #define T1INSYNC T1CON_bits.T1INSYNC
845 #define T1OSCEN T1CON_bits.T1OSCEN
846 #define T1CKPS0 T1CON_bits.T1CKPS0
847 #define T1CKPS1 T1CON_bits.T1CKPS1
849 // ----- T2CON bits --------------------
852 unsigned char T2CKPS0:1;
853 unsigned char T2CKPS1:1;
854 unsigned char TMR2ON:1;
855 unsigned char TOUTPS0:1;
856 unsigned char TOUTPS1:1;
857 unsigned char TOUTPS2:1;
858 unsigned char TOUTPS3:1;
862 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
864 #define T2CKPS0 T2CON_bits.T2CKPS0
865 #define T2CKPS1 T2CON_bits.T2CKPS1
866 #define TMR2ON T2CON_bits.TMR2ON
867 #define TOUTPS0 T2CON_bits.TOUTPS0
868 #define TOUTPS1 T2CON_bits.TOUTPS1
869 #define TOUTPS2 T2CON_bits.TOUTPS2
870 #define TOUTPS3 T2CON_bits.TOUTPS3
872 // ----- TRISA bits --------------------
875 unsigned char TRISA0:1;
876 unsigned char TRISA1:1;
877 unsigned char TRISA2:1;
878 unsigned char TRISA3:1;
879 unsigned char TRISA4:1;
880 unsigned char TRISA5:1;
885 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
887 #define TRISA0 TRISA_bits.TRISA0
888 #define TRISA1 TRISA_bits.TRISA1
889 #define TRISA2 TRISA_bits.TRISA2
890 #define TRISA3 TRISA_bits.TRISA3
891 #define TRISA4 TRISA_bits.TRISA4
892 #define TRISA5 TRISA_bits.TRISA5
894 // ----- TRISB bits --------------------
897 unsigned char TRISB0:1;
898 unsigned char TRISB1:1;
899 unsigned char TRISB2:1;
900 unsigned char TRISB3:1;
901 unsigned char TRISB4:1;
902 unsigned char TRISB5:1;
903 unsigned char TRISB6:1;
904 unsigned char TRISB7:1;
907 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
909 #define TRISB0 TRISB_bits.TRISB0
910 #define TRISB1 TRISB_bits.TRISB1
911 #define TRISB2 TRISB_bits.TRISB2
912 #define TRISB3 TRISB_bits.TRISB3
913 #define TRISB4 TRISB_bits.TRISB4
914 #define TRISB5 TRISB_bits.TRISB5
915 #define TRISB6 TRISB_bits.TRISB6
916 #define TRISB7 TRISB_bits.TRISB7
918 // ----- TRISC bits --------------------
921 unsigned char TRISC0:1;
922 unsigned char TRISC1:1;
923 unsigned char TRISC2:1;
924 unsigned char TRISC3:1;
925 unsigned char TRISC4:1;
926 unsigned char TRISC5:1;
927 unsigned char TRISC6:1;
928 unsigned char TRISC7:1;
931 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
933 #define TRISC0 TRISC_bits.TRISC0
934 #define TRISC1 TRISC_bits.TRISC1
935 #define TRISC2 TRISC_bits.TRISC2
936 #define TRISC3 TRISC_bits.TRISC3
937 #define TRISC4 TRISC_bits.TRISC4
938 #define TRISC5 TRISC_bits.TRISC5
939 #define TRISC6 TRISC_bits.TRISC6
940 #define TRISC7 TRISC_bits.TRISC7
942 // ----- TXSTA bits --------------------
945 unsigned char TX9D:1;
946 unsigned char TRMT:1;
947 unsigned char BRGH:1;
949 unsigned char SYNC:1;
950 unsigned char TXEN:1;
952 unsigned char CSRC:1;
955 unsigned char TXD8:1;
961 unsigned char NOT_TX8:1;
971 unsigned char TX8_9:1;
975 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
977 #define TX9D TXSTA_bits.TX9D
978 #define TXD8 TXSTA_bits.TXD8
979 #define TRMT TXSTA_bits.TRMT
980 #define BRGH TXSTA_bits.BRGH
981 #define SYNC TXSTA_bits.SYNC
982 #define TXEN TXSTA_bits.TXEN
983 #define TX9 TXSTA_bits.TX9
984 #define NOT_TX8 TXSTA_bits.NOT_TX8
985 #define TX8_9 TXSTA_bits.TX8_9
986 #define CSRC TXSTA_bits.CSRC