2 // Register Declarations for Microchip 16F73 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define SSPADD_ADDR 0x0093
67 #define SSPSTAT_ADDR 0x0094
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
71 #define PMDATA_ADDR 0x010C
72 #define PMADR_ADDR 0x010D
73 #define PMDATH_ADDR 0x010E
74 #define PMADRH_ADDR 0x010F
75 #define PMCON1_ADDR 0x018C
78 // Memory organization.
81 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
82 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
83 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
84 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
85 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
86 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
87 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
88 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
89 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
90 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
91 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
92 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
93 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
94 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
95 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
96 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
97 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
98 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
99 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
100 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
101 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
102 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
103 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
104 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
105 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
106 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
107 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
108 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
109 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
110 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
111 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
112 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
113 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
114 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
115 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
116 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
117 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
118 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
119 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
120 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
121 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
122 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
123 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
124 #pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
125 #pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
126 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
127 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
128 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
132 // P16F73.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
135 // This header file defines configurations, registers, and other useful bits of
136 // information for the PIC16F73 microcontroller. These names are taken to match
137 // the data sheets as closely as possible.
139 // Note that the processor must be selected before this file is
140 // included. The processor may be selected the following ways:
142 // 1. Command line switch:
143 // C:\ MPASM MYFILE.ASM /PIC16F73
144 // 2. LIST directive in the source file
146 // 3. Processor Type entry in the MPASM full-screen interface
148 //==========================================================================
152 //==========================================================================
156 //1.00 00/00/00 Initial Release
158 //==========================================================================
162 //==========================================================================
165 // MESSG "Processor-header file mismatch. Verify selected processor."
168 //==========================================================================
170 // Register Definitions
172 //==========================================================================
177 //----- Register Files------------------------------------------------------
179 extern data __at (INDF_ADDR) volatile char INDF;
180 extern sfr __at (TMR0_ADDR) TMR0;
181 extern data __at (PCL_ADDR) volatile char PCL;
182 extern sfr __at (STATUS_ADDR) STATUS;
183 extern sfr __at (FSR_ADDR) FSR;
184 extern sfr __at (PORTA_ADDR) PORTA;
185 extern sfr __at (PORTB_ADDR) PORTB;
186 extern sfr __at (PORTC_ADDR) PORTC;
187 extern sfr __at (PCLATH_ADDR) PCLATH;
188 extern sfr __at (INTCON_ADDR) INTCON;
189 extern sfr __at (PIR1_ADDR) PIR1;
190 extern sfr __at (PIR2_ADDR) PIR2;
191 extern sfr __at (TMR1L_ADDR) TMR1L;
192 extern sfr __at (TMR1H_ADDR) TMR1H;
193 extern sfr __at (T1CON_ADDR) T1CON;
194 extern sfr __at (TMR2_ADDR) TMR2;
195 extern sfr __at (T2CON_ADDR) T2CON;
196 extern sfr __at (SSPBUF_ADDR) SSPBUF;
197 extern sfr __at (SSPCON_ADDR) SSPCON;
198 extern sfr __at (CCPR1L_ADDR) CCPR1L;
199 extern sfr __at (CCPR1H_ADDR) CCPR1H;
200 extern sfr __at (CCP1CON_ADDR) CCP1CON;
201 extern sfr __at (RCSTA_ADDR) RCSTA;
202 extern sfr __at (TXREG_ADDR) TXREG;
203 extern sfr __at (RCREG_ADDR) RCREG;
204 extern sfr __at (CCPR2L_ADDR) CCPR2L;
205 extern sfr __at (CCPR2H_ADDR) CCPR2H;
206 extern sfr __at (CCP2CON_ADDR) CCP2CON;
207 extern sfr __at (ADRES_ADDR) ADRES;
208 extern sfr __at (ADCON0_ADDR) ADCON0;
210 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
211 extern sfr __at (TRISA_ADDR) TRISA;
212 extern sfr __at (TRISB_ADDR) TRISB;
213 extern sfr __at (TRISC_ADDR) TRISC;
214 extern sfr __at (PIE1_ADDR) PIE1;
215 extern sfr __at (PIE2_ADDR) PIE2;
216 extern sfr __at (PCON_ADDR) PCON;
217 extern sfr __at (PR2_ADDR) PR2;
218 extern sfr __at (SSPADD_ADDR) SSPADD;
219 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
220 extern sfr __at (TXSTA_ADDR) TXSTA;
221 extern sfr __at (SPBRG_ADDR) SPBRG;
222 extern sfr __at (ADCON1_ADDR) ADCON1;
224 extern sfr __at (PMDATA_ADDR) PMDATA;
225 extern sfr __at (PMADR_ADDR) PMADR;
226 extern sfr __at (PMDATH_ADDR) PMDATH;
227 extern sfr __at (PMADRH_ADDR) PMADRH;
229 extern sfr __at (PMCON1_ADDR) PMCON1;
231 //----- STATUS Bits --------------------------------------------------------
234 //----- INTCON Bits --------------------------------------------------------
237 //----- PIR1 Bits ----------------------------------------------------------
240 //----- PIR2 Bits ----------------------------------------------------------
243 //----- T1CON Bits ---------------------------------------------------------
246 //----- T2CON Bits ---------------------------------------------------------
249 //----- SSPCON Bits --------------------------------------------------------
252 //----- CCP1CON Bits -------------------------------------------------------
255 //----- RCSTA Bits ---------------------------------------------------------
258 //----- CCP2CON Bits -------------------------------------------------------
261 //----- ADCON0 Bits --------------------------------------------------------
264 //----- OPTION Bits --------------------------------------------------------
267 //----- PIE1 Bits ----------------------------------------------------------
270 //----- PIE2 Bits ----------------------------------------------------------
273 //----- PCON Bits ----------------------------------------------------------
276 //----- SSPSTAT Bits -------------------------------------------------------
279 //----- TXSTA Bits ---------------------------------------------------------
282 //----- ADCON1 Bits --------------------------------------------------------
285 //----- PMCON1 Bits --------------------------------------------------------
287 //==========================================================================
291 //==========================================================================
294 // __BADRAM H'08'-H'09'
295 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
296 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
297 // __BADRAM H'185', H'187'-H'189', H'18D'-H'19F'
299 //==========================================================================
301 // Configuration Bits
303 //==========================================================================
305 #define _BODEN_ON 0x3FFF
306 #define _BODEN_OFF 0x3FBF
307 #define _CP_ALL 0x3FEF
308 #define _CP_OFF 0x3FFF
309 #define _PWRTE_OFF 0x3FFF
310 #define _PWRTE_ON 0x3FF7
311 #define _WDT_ON 0x3FFF
312 #define _WDT_OFF 0x3FFB
313 #define _LP_OSC 0x3FFC
314 #define _XT_OSC 0x3FFD
315 #define _HS_OSC 0x3FFE
316 #define _RC_OSC 0x3FFF
321 // ----- ADCON0 bits --------------------
324 unsigned char ADON:1;
327 unsigned char CHS0:1;
328 unsigned char CHS1:1;
329 unsigned char CHS2:1;
330 unsigned char ADCS0:1;
331 unsigned char ADCS1:1;
336 unsigned char NOT_DONE:1;
346 unsigned char GO_DONE:1;
354 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
356 #define ADON ADCON0_bits.ADON
357 #define GO ADCON0_bits.GO
358 #define NOT_DONE ADCON0_bits.NOT_DONE
359 #define GO_DONE ADCON0_bits.GO_DONE
360 #define CHS0 ADCON0_bits.CHS0
361 #define CHS1 ADCON0_bits.CHS1
362 #define CHS2 ADCON0_bits.CHS2
363 #define ADCS0 ADCON0_bits.ADCS0
364 #define ADCS1 ADCON0_bits.ADCS1
366 // ----- ADCON1 bits --------------------
369 unsigned char PCFG0:1;
370 unsigned char PCFG1:1;
371 unsigned char PCFG2:1;
379 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
381 #define PCFG0 ADCON1_bits.PCFG0
382 #define PCFG1 ADCON1_bits.PCFG1
383 #define PCFG2 ADCON1_bits.PCFG2
385 // ----- CCP1CON bits --------------------
388 unsigned char CCP1M0:1;
389 unsigned char CCP1M1:1;
390 unsigned char CCP1M2:1;
391 unsigned char CCP1M3:1;
392 unsigned char CCP1Y:1;
393 unsigned char CCP1X:1;
398 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
400 #define CCP1M0 CCP1CON_bits.CCP1M0
401 #define CCP1M1 CCP1CON_bits.CCP1M1
402 #define CCP1M2 CCP1CON_bits.CCP1M2
403 #define CCP1M3 CCP1CON_bits.CCP1M3
404 #define CCP1Y CCP1CON_bits.CCP1Y
405 #define CCP1X CCP1CON_bits.CCP1X
407 // ----- CCP2CON bits --------------------
410 unsigned char CCP2M0:1;
411 unsigned char CCP2M1:1;
412 unsigned char CCP2M2:1;
413 unsigned char CCP2M3:1;
414 unsigned char CCP2Y:1;
415 unsigned char CCP2X:1;
420 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
422 #define CCP2M0 CCP2CON_bits.CCP2M0
423 #define CCP2M1 CCP2CON_bits.CCP2M1
424 #define CCP2M2 CCP2CON_bits.CCP2M2
425 #define CCP2M3 CCP2CON_bits.CCP2M3
426 #define CCP2Y CCP2CON_bits.CCP2Y
427 #define CCP2X CCP2CON_bits.CCP2X
429 // ----- INTCON bits --------------------
432 unsigned char RBIF:1;
433 unsigned char INTF:1;
434 unsigned char T0IF:1;
435 unsigned char RBIE:1;
436 unsigned char INTE:1;
437 unsigned char T0IE:1;
438 unsigned char PEIE:1;
442 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
444 #define RBIF INTCON_bits.RBIF
445 #define INTF INTCON_bits.INTF
446 #define T0IF INTCON_bits.T0IF
447 #define RBIE INTCON_bits.RBIE
448 #define INTE INTCON_bits.INTE
449 #define T0IE INTCON_bits.T0IE
450 #define PEIE INTCON_bits.PEIE
451 #define GIE INTCON_bits.GIE
453 // ----- OPTION_REG bits --------------------
460 unsigned char T0SE:1;
461 unsigned char T0CS:1;
462 unsigned char INTEDG:1;
463 unsigned char NOT_RBPU:1;
465 } __OPTION_REG_bits_t;
466 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
468 #define PS0 OPTION_REG_bits.PS0
469 #define PS1 OPTION_REG_bits.PS1
470 #define PS2 OPTION_REG_bits.PS2
471 #define PSA OPTION_REG_bits.PSA
472 #define T0SE OPTION_REG_bits.T0SE
473 #define T0CS OPTION_REG_bits.T0CS
474 #define INTEDG OPTION_REG_bits.INTEDG
475 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
477 // ----- PCON bits --------------------
480 unsigned char NOT_BO:1;
481 unsigned char NOT_POR:1;
490 unsigned char NOT_BOR:1;
500 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
502 #define NOT_BO PCON_bits.NOT_BO
503 #define NOT_BOR PCON_bits.NOT_BOR
504 #define NOT_POR PCON_bits.NOT_POR
506 // ----- PIE1 bits --------------------
509 unsigned char TMR1IE:1;
510 unsigned char TMR2IE:1;
511 unsigned char CCP1IE:1;
512 unsigned char SSPIE:1;
513 unsigned char TXIE:1;
514 unsigned char RCIE:1;
515 unsigned char ADIE:1;
519 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
521 #define TMR1IE PIE1_bits.TMR1IE
522 #define TMR2IE PIE1_bits.TMR2IE
523 #define CCP1IE PIE1_bits.CCP1IE
524 #define SSPIE PIE1_bits.SSPIE
525 #define TXIE PIE1_bits.TXIE
526 #define RCIE PIE1_bits.RCIE
527 #define ADIE PIE1_bits.ADIE
529 // ----- PIE2 bits --------------------
532 unsigned char CCP2IE:1;
542 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
544 #define CCP2IE PIE2_bits.CCP2IE
546 // ----- PIR1 bits --------------------
549 unsigned char TMR1IF:1;
550 unsigned char TMR2IF:1;
551 unsigned char CCP1IF:1;
552 unsigned char SSPIF:1;
553 unsigned char TXIF:1;
554 unsigned char RCIF:1;
555 unsigned char ADIF:1;
559 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
561 #define TMR1IF PIR1_bits.TMR1IF
562 #define TMR2IF PIR1_bits.TMR2IF
563 #define CCP1IF PIR1_bits.CCP1IF
564 #define SSPIF PIR1_bits.SSPIF
565 #define TXIF PIR1_bits.TXIF
566 #define RCIF PIR1_bits.RCIF
567 #define ADIF PIR1_bits.ADIF
569 // ----- PIR2 bits --------------------
572 unsigned char CCP2IF:1;
582 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
584 #define CCP2IF PIR2_bits.CCP2IF
586 // ----- PMCON1 bits --------------------
599 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
601 #define RD PMCON1_bits.RD
603 // ----- RCSTA bits --------------------
606 unsigned char RX9D:1;
607 unsigned char OERR:1;
608 unsigned char FERR:1;
610 unsigned char CREN:1;
611 unsigned char SREN:1;
613 unsigned char SPEN:1;
616 unsigned char RCD8:1;
632 unsigned char NOT_RC8:1;
642 unsigned char RC8_9:1;
646 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
648 #define RX9D RCSTA_bits.RX9D
649 #define RCD8 RCSTA_bits.RCD8
650 #define OERR RCSTA_bits.OERR
651 #define FERR RCSTA_bits.FERR
652 #define CREN RCSTA_bits.CREN
653 #define SREN RCSTA_bits.SREN
654 #define RX9 RCSTA_bits.RX9
655 #define RC9 RCSTA_bits.RC9
656 #define NOT_RC8 RCSTA_bits.NOT_RC8
657 #define RC8_9 RCSTA_bits.RC8_9
658 #define SPEN RCSTA_bits.SPEN
660 // ----- SSPCON bits --------------------
663 unsigned char SSPM0:1;
664 unsigned char SSPM1:1;
665 unsigned char SSPM2:1;
666 unsigned char SSPM3:1;
668 unsigned char SSPEN:1;
669 unsigned char SSPOV:1;
670 unsigned char WCOL:1;
673 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
675 #define SSPM0 SSPCON_bits.SSPM0
676 #define SSPM1 SSPCON_bits.SSPM1
677 #define SSPM2 SSPCON_bits.SSPM2
678 #define SSPM3 SSPCON_bits.SSPM3
679 #define CKP SSPCON_bits.CKP
680 #define SSPEN SSPCON_bits.SSPEN
681 #define SSPOV SSPCON_bits.SSPOV
682 #define WCOL SSPCON_bits.WCOL
684 // ----- SSPSTAT bits --------------------
699 unsigned char I2C_READ:1;
700 unsigned char I2C_START:1;
701 unsigned char I2C_STOP:1;
702 unsigned char I2C_DATA:1;
709 unsigned char NOT_W:1;
712 unsigned char NOT_A:1;
719 unsigned char NOT_WRITE:1;
722 unsigned char NOT_ADDRESS:1;
739 unsigned char READ_WRITE:1;
742 unsigned char DATA_ADDRESS:1;
747 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
749 #define BF SSPSTAT_bits.BF
750 #define UA SSPSTAT_bits.UA
751 #define R SSPSTAT_bits.R
752 #define I2C_READ SSPSTAT_bits.I2C_READ
753 #define NOT_W SSPSTAT_bits.NOT_W
754 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
755 #define R_W SSPSTAT_bits.R_W
756 #define READ_WRITE SSPSTAT_bits.READ_WRITE
757 #define S SSPSTAT_bits.S
758 #define I2C_START SSPSTAT_bits.I2C_START
759 #define P SSPSTAT_bits.P
760 #define I2C_STOP SSPSTAT_bits.I2C_STOP
761 #define D SSPSTAT_bits.D
762 #define I2C_DATA SSPSTAT_bits.I2C_DATA
763 #define NOT_A SSPSTAT_bits.NOT_A
764 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
765 #define D_A SSPSTAT_bits.D_A
766 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
767 #define CKE SSPSTAT_bits.CKE
768 #define SMP SSPSTAT_bits.SMP
770 // ----- STATUS bits --------------------
776 unsigned char NOT_PD:1;
777 unsigned char NOT_TO:1;
783 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
785 #define C STATUS_bits.C
786 #define DC STATUS_bits.DC
787 #define Z STATUS_bits.Z
788 #define NOT_PD STATUS_bits.NOT_PD
789 #define NOT_TO STATUS_bits.NOT_TO
790 #define RP0 STATUS_bits.RP0
791 #define RP1 STATUS_bits.RP1
792 #define IRP STATUS_bits.IRP
794 // ----- T1CON bits --------------------
797 unsigned char TMR1ON:1;
798 unsigned char TMR1CS:1;
799 unsigned char NOT_T1SYNC:1;
800 unsigned char T1OSCEN:1;
801 unsigned char T1CKPS0:1;
802 unsigned char T1CKPS1:1;
809 unsigned char T1INSYNC:1;
817 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
819 #define TMR1ON T1CON_bits.TMR1ON
820 #define TMR1CS T1CON_bits.TMR1CS
821 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
822 #define T1INSYNC T1CON_bits.T1INSYNC
823 #define T1OSCEN T1CON_bits.T1OSCEN
824 #define T1CKPS0 T1CON_bits.T1CKPS0
825 #define T1CKPS1 T1CON_bits.T1CKPS1
827 // ----- T2CON bits --------------------
830 unsigned char T2CKPS0:1;
831 unsigned char T2CKPS1:1;
832 unsigned char TMR2ON:1;
833 unsigned char TOUTPS0:1;
834 unsigned char TOUTPS1:1;
835 unsigned char TOUTPS2:1;
836 unsigned char TOUTPS3:1;
840 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
842 #define T2CKPS0 T2CON_bits.T2CKPS0
843 #define T2CKPS1 T2CON_bits.T2CKPS1
844 #define TMR2ON T2CON_bits.TMR2ON
845 #define TOUTPS0 T2CON_bits.TOUTPS0
846 #define TOUTPS1 T2CON_bits.TOUTPS1
847 #define TOUTPS2 T2CON_bits.TOUTPS2
848 #define TOUTPS3 T2CON_bits.TOUTPS3
850 // ----- TXSTA bits --------------------
853 unsigned char TX9D:1;
854 unsigned char TRMT:1;
855 unsigned char BRGH:1;
857 unsigned char SYNC:1;
858 unsigned char TXEN:1;
860 unsigned char CSRC:1;
863 unsigned char TXD8:1;
869 unsigned char NOT_TX8:1;
879 unsigned char TX8_9:1;
883 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
885 #define TX9D TXSTA_bits.TX9D
886 #define TXD8 TXSTA_bits.TXD8
887 #define TRMT TXSTA_bits.TRMT
888 #define BRGH TXSTA_bits.BRGH
889 #define SYNC TXSTA_bits.SYNC
890 #define TXEN TXSTA_bits.TXEN
891 #define TX9 TXSTA_bits.TX9
892 #define NOT_TX8 TXSTA_bits.NOT_TX8
893 #define TX8_9 TXSTA_bits.TX8_9
894 #define CSRC TXSTA_bits.CSRC