2 // Register Declarations for Microchip 16F72 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRES_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define TRISC_ADDR 0x0087
55 #define PIE1_ADDR 0x008C
56 #define PCON_ADDR 0x008E
57 #define PR2_ADDR 0x0092
58 #define SSPADD_ADDR 0x0093
59 #define SSPSTAT_ADDR 0x0094
60 #define ADCON1_ADDR 0x009F
61 #define PMDATL_ADDR 0x010C
62 #define PMADRL_ADDR 0x010D
63 #define PMDATH_ADDR 0x010E
64 #define PMADRH_ADDR 0x010F
65 #define PMCON1_ADDR 0x018C
68 // Memory organization.
71 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
72 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
73 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
74 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
75 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
76 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
77 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
78 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
79 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
80 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
81 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
82 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
83 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
84 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
85 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
86 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
87 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
88 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
89 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
90 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
91 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
92 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
93 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
94 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
95 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
96 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
97 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
98 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
99 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
100 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
101 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
102 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
103 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
104 #pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL
105 #pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL
106 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
107 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
108 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
112 // P16F72.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
115 // This header file defines configurations, registers, and other useful bits of
116 // information for the PIC16F72 microcontroller. These names are taken to match
117 // the data sheets as closely as possible.
119 // Note that the processor must be selected before this file is
120 // included. The processor may be selected the following ways:
122 // 1. Command line switch:
123 // C:\ MPASM MYFILE.ASM /PIC16F72
124 // 2. LIST directive in the source file
126 // 3. Processor Type entry in the MPASM full-screen interface
128 //==========================================================================
132 //==========================================================================
136 //1.00 03/22/02 Initial Release
138 //==========================================================================
142 //==========================================================================
145 // MESSG "Processor-header file mismatch. Verify selected processor."
148 //==========================================================================
150 // Register Definitions
152 //==========================================================================
157 //----- Register Files------------------------------------------------------
159 extern __data __at (INDF_ADDR) volatile char INDF;
160 extern __sfr __at (TMR0_ADDR) TMR0;
161 extern __data __at (PCL_ADDR) volatile char PCL;
162 extern __sfr __at (STATUS_ADDR) STATUS;
163 extern __sfr __at (FSR_ADDR) FSR;
164 extern __sfr __at (PORTA_ADDR) PORTA;
165 extern __sfr __at (PORTB_ADDR) PORTB;
166 extern __sfr __at (PORTC_ADDR) PORTC;
167 extern __sfr __at (PCLATH_ADDR) PCLATH;
168 extern __sfr __at (INTCON_ADDR) INTCON;
169 extern __sfr __at (PIR1_ADDR) PIR1;
170 extern __sfr __at (TMR1L_ADDR) TMR1L;
171 extern __sfr __at (TMR1H_ADDR) TMR1H;
172 extern __sfr __at (T1CON_ADDR) T1CON;
173 extern __sfr __at (TMR2_ADDR) TMR2;
174 extern __sfr __at (T2CON_ADDR) T2CON;
175 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
176 extern __sfr __at (SSPCON_ADDR) SSPCON;
177 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
178 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
179 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
180 extern __sfr __at (ADRES_ADDR) ADRES;
181 extern __sfr __at (ADCON0_ADDR) ADCON0;
182 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
183 extern __sfr __at (TRISA_ADDR) TRISA;
184 extern __sfr __at (TRISB_ADDR) TRISB;
185 extern __sfr __at (TRISC_ADDR) TRISC;
186 extern __sfr __at (PIE1_ADDR) PIE1;
187 extern __sfr __at (PCON_ADDR) PCON;
188 extern __sfr __at (PR2_ADDR) PR2;
189 extern __sfr __at (SSPADD_ADDR) SSPADD;
190 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
191 extern __sfr __at (ADCON1_ADDR) ADCON1;
193 extern __sfr __at (PMDATL_ADDR) PMDATL;
194 extern __sfr __at (PMADRL_ADDR) PMADRL;
195 extern __sfr __at (PMDATH_ADDR) PMDATH;
196 extern __sfr __at (PMADRH_ADDR) PMADRH;
198 extern __sfr __at (PMCON1_ADDR) PMCON1;
200 //----- STATUS Bits --------------------------------------------------------
203 //----- INTCON Bits --------------------------------------------------------
206 //----- PIR1 Bits ----------------------------------------------------------
209 //----- T1CON Bits ---------------------------------------------------------
212 //----- T2CON Bits ---------------------------------------------------------
215 //----- SSPCON Bits --------------------------------------------------------
218 //----- CCP1CON Bits -------------------------------------------------------
221 //----- ADCON0 Bits --------------------------------------------------------
224 //----- OPTION Bits --------------------------------------------------------
227 //----- PIE1 Bits ----------------------------------------------------------
230 //----- PCON Bits ----------------------------------------------------------
233 //----- SSPSTAT Bits -------------------------------------------------------
236 //----- ADCON1 Bits --------------------------------------------------------
239 //----- PMCON1 Bits --------------------------------------------------------
241 //==========================================================================
245 //==========================================================================
248 // __BADRAM H'08'-H'09', H'0D', H'18'-H'1D'
249 // __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E'
250 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
251 // __BADRAM H'185', H'187'-H'189', H'18D'-H'19F'
254 //==========================================================================
256 // Configuration Bits
258 //==========================================================================
260 #define _BOREN_ON 0x3FFF
261 #define _BODEN_ON 0x3FFF // Backward compatibility only
262 #define _BOREN_OFF 0x3FBF
263 #define _BODEN_OFF 0x3FBF // Backward compatibility only
264 #define _CP_ALL 0x3FEF
265 #define _CP_OFF 0x3FFF
266 #define _PWRTEN_OFF 0x3FFF
267 #define _PWRTE_OFF 0x3FFF // Backward compatibility only
268 #define _PWRTEN_ON 0x3FF7
269 #define _PWRTE_ON 0x3FF7 // Backward compatibility only
270 #define _WDTEN_ON 0x3FFF
271 #define _WDTEN_OFF 0x3FFB
272 #define _WDT_ON 0x3FFF // Backward compatibility only
273 #define _WDT_OFF 0x3FFB // Backward compatibility only
274 #define _LP_OSC 0x3FFC
275 #define _XT_OSC 0x3FFD
276 #define _HS_OSC 0x3FFE
277 #define _RC_OSC 0x3FFF
281 // ----- ADCON0 bits --------------------
284 unsigned char ADON:1;
287 unsigned char CHS0:1;
288 unsigned char CHS1:1;
289 unsigned char CHS2:1;
290 unsigned char ADCS0:1;
291 unsigned char ADCS1:1;
296 unsigned char NOT_DONE:1;
306 unsigned char GO_DONE:1;
314 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
316 #define ADON ADCON0_bits.ADON
317 #define GO ADCON0_bits.GO
318 #define NOT_DONE ADCON0_bits.NOT_DONE
319 #define GO_DONE ADCON0_bits.GO_DONE
320 #define CHS0 ADCON0_bits.CHS0
321 #define CHS1 ADCON0_bits.CHS1
322 #define CHS2 ADCON0_bits.CHS2
323 #define ADCS0 ADCON0_bits.ADCS0
324 #define ADCS1 ADCON0_bits.ADCS1
326 // ----- ADCON1 bits --------------------
329 unsigned char PCFG0:1;
330 unsigned char PCFG1:1;
331 unsigned char PCFG2:1;
339 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
341 #define PCFG0 ADCON1_bits.PCFG0
342 #define PCFG1 ADCON1_bits.PCFG1
343 #define PCFG2 ADCON1_bits.PCFG2
345 // ----- CCP1CON bits --------------------
348 unsigned char CCP1M0:1;
349 unsigned char CCP1M1:1;
350 unsigned char CCP1M2:1;
351 unsigned char CCP1M3:1;
352 unsigned char CCP1Y:1;
353 unsigned char CCP1X:1;
358 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
360 #define CCP1M0 CCP1CON_bits.CCP1M0
361 #define CCP1M1 CCP1CON_bits.CCP1M1
362 #define CCP1M2 CCP1CON_bits.CCP1M2
363 #define CCP1M3 CCP1CON_bits.CCP1M3
364 #define CCP1Y CCP1CON_bits.CCP1Y
365 #define CCP1X CCP1CON_bits.CCP1X
367 // ----- INTCON bits --------------------
370 unsigned char RBIF:1;
371 unsigned char INTF:1;
372 unsigned char TMR0IF:1;
373 unsigned char RBIE:1;
374 unsigned char INTE:1;
375 unsigned char TMR0IE:1;
376 unsigned char PEIE:1;
382 unsigned char T0IF:1;
385 unsigned char T0IE:1;
390 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
392 #define RBIF INTCON_bits.RBIF
393 #define INTF INTCON_bits.INTF
394 #define TMR0IF INTCON_bits.TMR0IF
395 #define T0IF INTCON_bits.T0IF
396 #define RBIE INTCON_bits.RBIE
397 #define INTE INTCON_bits.INTE
398 #define TMR0IE INTCON_bits.TMR0IE
399 #define T0IE INTCON_bits.T0IE
400 #define PEIE INTCON_bits.PEIE
401 #define GIE INTCON_bits.GIE
403 // ----- OPTION_REG bits --------------------
410 unsigned char T0SE:1;
411 unsigned char T0CS:1;
412 unsigned char INTEDG:1;
413 unsigned char NOT_RBPU:1;
415 } __OPTION_REG_bits_t;
416 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
418 #define PS0 OPTION_REG_bits.PS0
419 #define PS1 OPTION_REG_bits.PS1
420 #define PS2 OPTION_REG_bits.PS2
421 #define PSA OPTION_REG_bits.PSA
422 #define T0SE OPTION_REG_bits.T0SE
423 #define T0CS OPTION_REG_bits.T0CS
424 #define INTEDG OPTION_REG_bits.INTEDG
425 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
427 // ----- PCON bits --------------------
430 unsigned char NOT_BO:1;
431 unsigned char NOT_POR:1;
440 unsigned char NOT_BOR:1;
450 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
452 #define NOT_BO PCON_bits.NOT_BO
453 #define NOT_BOR PCON_bits.NOT_BOR
454 #define NOT_POR PCON_bits.NOT_POR
456 // ----- PIE1 bits --------------------
459 unsigned char TMR1IE:1;
460 unsigned char TMR2IE:1;
461 unsigned char CCP1IE:1;
462 unsigned char SSPIE:1;
465 unsigned char ADIE:1;
469 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
471 #define TMR1IE PIE1_bits.TMR1IE
472 #define TMR2IE PIE1_bits.TMR2IE
473 #define CCP1IE PIE1_bits.CCP1IE
474 #define SSPIE PIE1_bits.SSPIE
475 #define ADIE PIE1_bits.ADIE
477 // ----- PIR1 bits --------------------
480 unsigned char TMR1IF:1;
481 unsigned char TMR2IF:1;
482 unsigned char CCP1IF:1;
483 unsigned char SSPIF:1;
486 unsigned char ADIF:1;
490 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
492 #define TMR1IF PIR1_bits.TMR1IF
493 #define TMR2IF PIR1_bits.TMR2IF
494 #define CCP1IF PIR1_bits.CCP1IF
495 #define SSPIF PIR1_bits.SSPIF
496 #define ADIF PIR1_bits.ADIF
498 // ----- PMCON1 bits --------------------
511 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
513 #define RD PMCON1_bits.RD
515 // ----- SSPCON bits --------------------
518 unsigned char SSPM0:1;
519 unsigned char SSPM1:1;
520 unsigned char SSPM2:1;
521 unsigned char SSPM3:1;
523 unsigned char SSPEN:1;
524 unsigned char SSPOV:1;
525 unsigned char WCOL:1;
528 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
530 #define SSPM0 SSPCON_bits.SSPM0
531 #define SSPM1 SSPCON_bits.SSPM1
532 #define SSPM2 SSPCON_bits.SSPM2
533 #define SSPM3 SSPCON_bits.SSPM3
534 #define CKP SSPCON_bits.CKP
535 #define SSPEN SSPCON_bits.SSPEN
536 #define SSPOV SSPCON_bits.SSPOV
537 #define WCOL SSPCON_bits.WCOL
539 // ----- SSPSTAT bits --------------------
554 unsigned char I2C_READ:1;
555 unsigned char I2C_START:1;
556 unsigned char I2C_STOP:1;
557 unsigned char I2C_DATA:1;
564 unsigned char NOT_W:1;
567 unsigned char NOT_A:1;
574 unsigned char NOT_WRITE:1;
577 unsigned char NOT_ADDRESS:1;
594 unsigned char READ_WRITE:1;
597 unsigned char DATA_ADDRESS:1;
602 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
604 #define BF SSPSTAT_bits.BF
605 #define UA SSPSTAT_bits.UA
606 #define R SSPSTAT_bits.R
607 #define I2C_READ SSPSTAT_bits.I2C_READ
608 #define NOT_W SSPSTAT_bits.NOT_W
609 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
610 #define R_W SSPSTAT_bits.R_W
611 #define READ_WRITE SSPSTAT_bits.READ_WRITE
612 #define S SSPSTAT_bits.S
613 #define I2C_START SSPSTAT_bits.I2C_START
614 #define P SSPSTAT_bits.P
615 #define I2C_STOP SSPSTAT_bits.I2C_STOP
616 #define D SSPSTAT_bits.D
617 #define I2C_DATA SSPSTAT_bits.I2C_DATA
618 #define NOT_A SSPSTAT_bits.NOT_A
619 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
620 #define D_A SSPSTAT_bits.D_A
621 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
622 #define CKE SSPSTAT_bits.CKE
623 #define SMP SSPSTAT_bits.SMP
625 // ----- STATUS bits --------------------
631 unsigned char NOT_PD:1;
632 unsigned char NOT_TO:1;
638 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
640 #define C STATUS_bits.C
641 #define DC STATUS_bits.DC
642 #define Z STATUS_bits.Z
643 #define NOT_PD STATUS_bits.NOT_PD
644 #define NOT_TO STATUS_bits.NOT_TO
645 #define RP0 STATUS_bits.RP0
646 #define RP1 STATUS_bits.RP1
647 #define IRP STATUS_bits.IRP
649 // ----- T1CON bits --------------------
652 unsigned char TMR1ON:1;
653 unsigned char TMR1CS:1;
654 unsigned char NOT_T1SYNC:1;
655 unsigned char T1OSCEN:1;
656 unsigned char T1CKPS0:1;
657 unsigned char T1CKPS1:1;
664 unsigned char T1INSYNC:1;
672 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
674 #define TMR1ON T1CON_bits.TMR1ON
675 #define TMR1CS T1CON_bits.TMR1CS
676 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
677 #define T1INSYNC T1CON_bits.T1INSYNC
678 #define T1OSCEN T1CON_bits.T1OSCEN
679 #define T1CKPS0 T1CON_bits.T1CKPS0
680 #define T1CKPS1 T1CON_bits.T1CKPS1
682 // ----- T2CON bits --------------------
685 unsigned char T2CKPS0:1;
686 unsigned char T2CKPS1:1;
687 unsigned char TMR2ON:1;
688 unsigned char TOUTPS0:1;
689 unsigned char TOUTPS1:1;
690 unsigned char TOUTPS2:1;
691 unsigned char TOUTPS3:1;
695 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
697 #define T2CKPS0 T2CON_bits.T2CKPS0
698 #define T2CKPS1 T2CON_bits.T2CKPS1
699 #define TMR2ON T2CON_bits.TMR2ON
700 #define TOUTPS0 T2CON_bits.TOUTPS0
701 #define TOUTPS1 T2CON_bits.TOUTPS1
702 #define TOUTPS2 T2CON_bits.TOUTPS2
703 #define TOUTPS3 T2CON_bits.TOUTPS3