2 // Register Declarations for Microchip 16F716 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define DATACCP_ADDR 0x0006
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0015
45 #define CCPR1H_ADDR 0x0016
46 #define CCP1CON_ADDR 0x0017
47 #define PWM1CON_ADDR 0x0018
48 #define ECCPAS_ADDR 0x0019
49 #define ADRES_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define TRISCP_ADDR 0x0086
55 #define PIE1_ADDR 0x008C
56 #define PCON_ADDR 0x008E
57 #define PR2_ADDR 0x0092
58 #define ADCON1_ADDR 0x009F
61 // Memory organization.
67 // P16F716.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
70 // This header file defines configurations, registers, and other useful bits of
71 // information for the PIC16F716 microcontroller. These names are taken to match
72 // the data sheets as closely as possible.
74 // Note that the processor must be selected before this file is
75 // included. The processor may be selected the following ways:
77 // 1. Command line switch:
78 // C:\ MPASM MYFILE.ASM /PIC16F716
79 // 2. LIST directive in the source file
81 // 3. Processor Type entry in the MPASM full-screen interface
83 //==========================================================================
87 //==========================================================================
91 //1.00 16 Apr 2003 Initial Release
92 //1.01 30 Apr 2003 Added references for backward compatibility to PIC16C716
94 //==========================================================================
98 //==========================================================================
101 // MESSG "Processor-header file mismatch. Verify selected processor."
104 //==========================================================================
106 // Register Definitions
108 //==========================================================================
113 //----- Register Files------------------------------------------------------
115 extern __sfr __at (INDF_ADDR) INDF;
116 extern __sfr __at (TMR0_ADDR) TMR0;
117 extern __sfr __at (PCL_ADDR) PCL;
118 extern __sfr __at (STATUS_ADDR) STATUS;
119 extern __sfr __at (FSR_ADDR) FSR;
120 extern __sfr __at (PORTA_ADDR) PORTA;
121 extern __sfr __at (PORTB_ADDR) PORTB;
122 extern __sfr __at (DATACCP_ADDR) DATACCP; // C712/C716 compatibility
124 extern __sfr __at (PCLATH_ADDR) PCLATH;
125 extern __sfr __at (INTCON_ADDR) INTCON;
126 extern __sfr __at (PIR1_ADDR) PIR1;
127 extern __sfr __at (TMR1L_ADDR) TMR1L;
128 extern __sfr __at (TMR1H_ADDR) TMR1H;
129 extern __sfr __at (T1CON_ADDR) T1CON;
130 extern __sfr __at (TMR2_ADDR) TMR2;
131 extern __sfr __at (T2CON_ADDR) T2CON;
132 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
133 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
134 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
135 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
136 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
137 extern __sfr __at (ADRES_ADDR) ADRES;
138 extern __sfr __at (ADCON0_ADDR) ADCON0;
140 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
141 extern __sfr __at (TRISA_ADDR) TRISA;
142 extern __sfr __at (TRISB_ADDR) TRISB;
143 extern __sfr __at (TRISCP_ADDR) TRISCP; // C712/C716 compatibility
145 extern __sfr __at (PIE1_ADDR) PIE1;
146 extern __sfr __at (PCON_ADDR) PCON;
147 extern __sfr __at (PR2_ADDR) PR2;
148 extern __sfr __at (ADCON1_ADDR) ADCON1;
150 //----- STATUS Bits --------------------------------------------------------
153 //----- PORTB Bits --------------------------------------------------------
156 //----- INTCON Bits --------------------------------------------------------
159 //----- PIR1 Bits ----------------------------------------------------------
162 //----- T1CON Bits ---------------------------------------------------------
165 //----- T2CON Bits ---------------------------------------------------------
169 //----- CCP1CON Bits -------------------------------------------------------
172 //----- PWM1CON Bits -------------------------------------------------------
175 //----- ECCPAS Bits --------------------------------------------------------
179 //----- ADCON0 Bits --------------------------------------------------------
182 //----- OPTION Bits --------------------------------------------------------
185 //----- TRISB Bits --------------------------------------------------------
189 //----- PIE1 Bits ----------------------------------------------------------
192 //----- PCON Bits ----------------------------------------------------------
196 //----- ADCON1 Bits --------------------------------------------------------
199 //==========================================================================
203 //==========================================================================
206 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1A'-H'1D'
207 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E'
209 //==========================================================================
211 // Configuration Bits
213 //==========================================================================
215 #define _BODEN_ON 0x3FFF // C712/C716 compatibility
216 #define _BODEN_OFF 0x3FBF // C712/C716 compatibility
217 #define _BOREN_ON 0x3FFF
218 #define _BOREN_OFF 0x3FBF
219 #define _VBOR_25 0x3F7F
220 #define _VBOR_40 0x3FFF
221 #define _CP_ON 0x1FFF
222 #define _CP_ALL 0x1FFF // C712/C716 compatibility
223 #define _CP_OFF 0x3FFF
224 #define _PWRTE_OFF 0x3FFF
225 #define _PWRTE_ON 0x3FF7
226 #define _WDT_ON 0x3FFF
227 #define _WDT_OFF 0x3FFB
228 #define _LP_OSC 0x3FFC
229 #define _XT_OSC 0x3FFD
230 #define _HS_OSC 0x3FFE
231 #define _RC_OSC 0x3FFF
235 // ----- ADCON0 bits --------------------
238 unsigned char ADON:1;
241 unsigned char CHS0:1;
242 unsigned char CHS1:1;
243 unsigned char CHS2:1;
244 unsigned char ADCS0:1;
245 unsigned char ADCS1:1;
250 unsigned char NOT_DONE:1;
260 unsigned char GO_DONE:1;
268 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
270 #ifndef NO_BIT_DEFINES
271 #define ADON ADCON0_bits.ADON
272 #define GO ADCON0_bits.GO
273 #define NOT_DONE ADCON0_bits.NOT_DONE
274 #define GO_DONE ADCON0_bits.GO_DONE
275 #define CHS0 ADCON0_bits.CHS0
276 #define CHS1 ADCON0_bits.CHS1
277 #define CHS2 ADCON0_bits.CHS2
278 #define ADCS0 ADCON0_bits.ADCS0
279 #define ADCS1 ADCON0_bits.ADCS1
280 #endif /* NO_BIT_DEFINES */
282 // ----- ADCON1 bits --------------------
285 unsigned char PCFG0:1;
286 unsigned char PCFG1:1;
287 unsigned char PCFG2:1;
295 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
297 #ifndef NO_BIT_DEFINES
298 #define PCFG0 ADCON1_bits.PCFG0
299 #define PCFG1 ADCON1_bits.PCFG1
300 #define PCFG2 ADCON1_bits.PCFG2
301 #endif /* NO_BIT_DEFINES */
303 // ----- CCP1CON bits --------------------
306 unsigned char CCP1M0:1;
307 unsigned char CCP1M1:1;
308 unsigned char CCP1M2:1;
309 unsigned char CCP1M3:1;
310 unsigned char DC1B0:1;
311 unsigned char DC1B1:1;
312 unsigned char P1M0:1;
313 unsigned char P1M1:1;
316 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
318 #ifndef NO_BIT_DEFINES
319 #define CCP1M0 CCP1CON_bits.CCP1M0
320 #define CCP1M1 CCP1CON_bits.CCP1M1
321 #define CCP1M2 CCP1CON_bits.CCP1M2
322 #define CCP1M3 CCP1CON_bits.CCP1M3
323 #define DC1B0 CCP1CON_bits.DC1B0
324 #define DC1B1 CCP1CON_bits.DC1B1
325 #define P1M0 CCP1CON_bits.P1M0
326 #define P1M1 CCP1CON_bits.P1M1
327 #endif /* NO_BIT_DEFINES */
329 // ----- ECCPAS bits --------------------
332 unsigned char PSSBD0:1;
333 unsigned char PSSBD1:1;
334 unsigned char PSSAC0:1;
335 unsigned char PSSAC1:1;
336 unsigned char ECCPAS0:1;
337 unsigned char ECCPAS1:1;
339 unsigned char ECCPASE:1;
342 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
344 #ifndef NO_BIT_DEFINES
345 #define PSSBD0 ECCPAS_bits.PSSBD0
346 #define PSSBD1 ECCPAS_bits.PSSBD1
347 #define PSSAC0 ECCPAS_bits.PSSAC0
348 #define PSSAC1 ECCPAS_bits.PSSAC1
349 #define ECCPAS0 ECCPAS_bits.ECCPAS0
350 #define ECCPAS1 ECCPAS_bits.ECCPAS1
351 #define ECCPASE ECCPAS_bits.ECCPASE
352 #endif /* NO_BIT_DEFINES */
354 // ----- INTCON bits --------------------
357 unsigned char RBIF:1;
358 unsigned char INTF:1;
359 unsigned char T0IF:1;
360 unsigned char RBIE:1;
361 unsigned char INTE:1;
362 unsigned char T0IE:1;
363 unsigned char PEIE:1;
367 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
369 #ifndef NO_BIT_DEFINES
370 #define RBIF INTCON_bits.RBIF
371 #define INTF INTCON_bits.INTF
372 #define T0IF INTCON_bits.T0IF
373 #define RBIE INTCON_bits.RBIE
374 #define INTE INTCON_bits.INTE
375 #define T0IE INTCON_bits.T0IE
376 #define PEIE INTCON_bits.PEIE
377 #define GIE INTCON_bits.GIE
378 #endif /* NO_BIT_DEFINES */
380 // ----- OPTION_REG bits --------------------
387 unsigned char T0SE:1;
388 unsigned char T0CS:1;
389 unsigned char INTEDG:1;
390 unsigned char NOT_RBPU:1;
392 } __OPTION_REG_bits_t;
393 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
395 #ifndef NO_BIT_DEFINES
396 #define PS0 OPTION_REG_bits.PS0
397 #define PS1 OPTION_REG_bits.PS1
398 #define PS2 OPTION_REG_bits.PS2
399 #define PSA OPTION_REG_bits.PSA
400 #define T0SE OPTION_REG_bits.T0SE
401 #define T0CS OPTION_REG_bits.T0CS
402 #define INTEDG OPTION_REG_bits.INTEDG
403 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
404 #endif /* NO_BIT_DEFINES */
406 // ----- PCON bits --------------------
409 unsigned char NOT_BO:1;
410 unsigned char NOT_POR:1;
419 unsigned char NOT_BOD:1;
429 unsigned char NOT_BOR:1;
439 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
441 #ifndef NO_BIT_DEFINES
442 #define NOT_BO PCON_bits.NOT_BO
443 #define NOT_BOD PCON_bits.NOT_BOD
444 #define NOT_BOR PCON_bits.NOT_BOR
445 #define NOT_POR PCON_bits.NOT_POR
446 #endif /* NO_BIT_DEFINES */
448 // ----- PIE1 bits --------------------
451 unsigned char TMR1IE:1;
452 unsigned char TMR2IE:1;
453 unsigned char CCP1IE:1;
457 unsigned char ADIE:1;
461 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
463 #ifndef NO_BIT_DEFINES
464 #define TMR1IE PIE1_bits.TMR1IE
465 #define TMR2IE PIE1_bits.TMR2IE
466 #define CCP1IE PIE1_bits.CCP1IE
467 #define ADIE PIE1_bits.ADIE
468 #endif /* NO_BIT_DEFINES */
470 // ----- PIR1 bits --------------------
473 unsigned char TMR1IF:1;
474 unsigned char TMR2IF:1;
475 unsigned char CCP1IF:1;
479 unsigned char ADIF:1;
483 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
485 #ifndef NO_BIT_DEFINES
486 #define TMR1IF PIR1_bits.TMR1IF
487 #define TMR2IF PIR1_bits.TMR2IF
488 #define CCP1IF PIR1_bits.CCP1IF
489 #define ADIF PIR1_bits.ADIF
490 #endif /* NO_BIT_DEFINES */
492 // ----- PORTA bits --------------------
505 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
507 #ifndef NO_BIT_DEFINES
508 #define RA0 PORTA_bits.RA0
509 #define RA1 PORTA_bits.RA1
510 #define RA2 PORTA_bits.RA2
511 #define RA3 PORTA_bits.RA3
512 #define RA4 PORTA_bits.RA4
513 #define RA5 PORTA_bits.RA5
514 #endif /* NO_BIT_DEFINES */
516 // ----- PORTB bits --------------------
520 unsigned char DT1CK:1;
522 unsigned char DCCP:1;
529 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
531 #ifndef NO_BIT_DEFINES
532 #define DT1CK PORTB_bits.DT1CK
533 #define DCCP PORTB_bits.DCCP
534 #endif /* NO_BIT_DEFINES */
536 // ----- PWM1CON bits --------------------
539 unsigned char PDC0:1;
540 unsigned char PDC1:1;
541 unsigned char PDC2:1;
542 unsigned char PDC3:1;
543 unsigned char PDC4:1;
544 unsigned char PDC5:1;
545 unsigned char PDC6:1;
546 unsigned char PRSEN:1;
549 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
551 #ifndef NO_BIT_DEFINES
552 #define PDC0 PWM1CON_bits.PDC0
553 #define PDC1 PWM1CON_bits.PDC1
554 #define PDC2 PWM1CON_bits.PDC2
555 #define PDC3 PWM1CON_bits.PDC3
556 #define PDC4 PWM1CON_bits.PDC4
557 #define PDC5 PWM1CON_bits.PDC5
558 #define PDC6 PWM1CON_bits.PDC6
559 #define PRSEN PWM1CON_bits.PRSEN
560 #endif /* NO_BIT_DEFINES */
562 // ----- STATUS bits --------------------
568 unsigned char NOT_PD:1;
569 unsigned char NOT_TO:1;
575 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
577 #ifndef NO_BIT_DEFINES
578 #define C STATUS_bits.C
579 #define DC STATUS_bits.DC
580 #define Z STATUS_bits.Z
581 #define NOT_PD STATUS_bits.NOT_PD
582 #define NOT_TO STATUS_bits.NOT_TO
583 #define RP0 STATUS_bits.RP0
584 #define RP1 STATUS_bits.RP1
585 #define IRP STATUS_bits.IRP
586 #endif /* NO_BIT_DEFINES */
588 // ----- T1CON bits --------------------
591 unsigned char TMR1ON:1;
592 unsigned char TMR1CS:1;
593 unsigned char T1SYNC:1;
594 unsigned char T1OSCEN:1;
595 unsigned char T1CKPS0:1;
596 unsigned char T1CKPS1:1;
603 unsigned char NOT_T1SYNC:1;
611 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
613 #ifndef NO_BIT_DEFINES
614 #define TMR1ON T1CON_bits.TMR1ON
615 #define TMR1CS T1CON_bits.TMR1CS
616 #define T1SYNC T1CON_bits.T1SYNC
617 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
618 #define T1OSCEN T1CON_bits.T1OSCEN
619 #define T1CKPS0 T1CON_bits.T1CKPS0
620 #define T1CKPS1 T1CON_bits.T1CKPS1
621 #endif /* NO_BIT_DEFINES */
623 // ----- T2CON bits --------------------
626 unsigned char T2CKPS0:1;
627 unsigned char T2CKPS1:1;
628 unsigned char TMR2ON:1;
629 unsigned char TOUTPS0:1;
630 unsigned char TOUTPS1:1;
631 unsigned char TOUTPS2:1;
632 unsigned char TOUTPS3:1;
636 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
638 #ifndef NO_BIT_DEFINES
639 #define T2CKPS0 T2CON_bits.T2CKPS0
640 #define T2CKPS1 T2CON_bits.T2CKPS1
641 #define TMR2ON T2CON_bits.TMR2ON
642 #define TOUTPS0 T2CON_bits.TOUTPS0
643 #define TOUTPS1 T2CON_bits.TOUTPS1
644 #define TOUTPS2 T2CON_bits.TOUTPS2
645 #define TOUTPS3 T2CON_bits.TOUTPS3
646 #endif /* NO_BIT_DEFINES */
648 // ----- TRISA bits --------------------
651 unsigned char TRISA0:1;
652 unsigned char TRISA1:1;
653 unsigned char TRISA2:1;
654 unsigned char TRISA3:1;
655 unsigned char TRISA4:1;
656 unsigned char TRISA5:1;
661 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
663 #ifndef NO_BIT_DEFINES
664 #define TRISA0 TRISA_bits.TRISA0
665 #define TRISA1 TRISA_bits.TRISA1
666 #define TRISA2 TRISA_bits.TRISA2
667 #define TRISA3 TRISA_bits.TRISA3
668 #define TRISA4 TRISA_bits.TRISA4
669 #define TRISA5 TRISA_bits.TRISA5
670 #endif /* NO_BIT_DEFINES */
672 // ----- TRISB bits --------------------
676 unsigned char TT1CK:1;
678 unsigned char TCCP:1;
685 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
687 #ifndef NO_BIT_DEFINES
688 #define TT1CK TRISB_bits.TT1CK
689 #define TCCP TRISB_bits.TCCP
690 #endif /* NO_BIT_DEFINES */