2 // Register Declarations for Microchip 16F716 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define DATACCP_ADDR 0x0006
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define CCPR1L_ADDR 0x0015
45 #define CCPR1H_ADDR 0x0016
46 #define CCP1CON_ADDR 0x0017
47 #define PWM1CON_ADDR 0x0018
48 #define ECCPAS_ADDR 0x0019
49 #define ADRES_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define TRISCP_ADDR 0x0086
55 #define PIE1_ADDR 0x008C
56 #define PCON_ADDR 0x008E
57 #define PR2_ADDR 0x0092
58 #define ADCON1_ADDR 0x009F
61 // Memory organization.
64 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
65 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
66 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
67 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
68 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
69 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
70 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
71 #pragma memmap DATACCP_ADDR DATACCP_ADDR SFR 0x000 // DATACCP
72 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
73 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
74 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
75 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
76 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
77 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
78 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
79 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
80 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
81 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
82 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
83 #pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON
84 #pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS
85 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
86 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
87 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
88 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
89 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
90 #pragma memmap TRISCP_ADDR TRISCP_ADDR SFR 0x000 // TRISCP
91 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
92 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
93 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
94 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
98 // P16F716.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
101 // This header file defines configurations, registers, and other useful bits of
102 // information for the PIC16F716 microcontroller. These names are taken to match
103 // the data sheets as closely as possible.
105 // Note that the processor must be selected before this file is
106 // included. The processor may be selected the following ways:
108 // 1. Command line switch:
109 // C:\ MPASM MYFILE.ASM /PIC16F716
110 // 2. LIST directive in the source file
112 // 3. Processor Type entry in the MPASM full-screen interface
114 //==========================================================================
118 //==========================================================================
122 //1.00 16 Apr 2003 Initial Release
123 //1.01 30 Apr 2003 Added references for backward compatibility to PIC16C716
125 //==========================================================================
129 //==========================================================================
132 // MESSG "Processor-header file mismatch. Verify selected processor."
135 //==========================================================================
137 // Register Definitions
139 //==========================================================================
144 //----- Register Files------------------------------------------------------
146 extern __data __at (INDF_ADDR) volatile char INDF;
147 extern __sfr __at (TMR0_ADDR) TMR0;
148 extern __data __at (PCL_ADDR) volatile char PCL;
149 extern __sfr __at (STATUS_ADDR) STATUS;
150 extern __sfr __at (FSR_ADDR) FSR;
151 extern __sfr __at (PORTA_ADDR) PORTA;
152 extern __sfr __at (PORTB_ADDR) PORTB;
153 extern __sfr __at (DATACCP_ADDR) DATACCP; // C712/C716 compatibility
155 extern __sfr __at (PCLATH_ADDR) PCLATH;
156 extern __sfr __at (INTCON_ADDR) INTCON;
157 extern __sfr __at (PIR1_ADDR) PIR1;
158 extern __sfr __at (TMR1L_ADDR) TMR1L;
159 extern __sfr __at (TMR1H_ADDR) TMR1H;
160 extern __sfr __at (T1CON_ADDR) T1CON;
161 extern __sfr __at (TMR2_ADDR) TMR2;
162 extern __sfr __at (T2CON_ADDR) T2CON;
163 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
164 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
165 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
166 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
167 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
168 extern __sfr __at (ADRES_ADDR) ADRES;
169 extern __sfr __at (ADCON0_ADDR) ADCON0;
171 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
172 extern __sfr __at (TRISA_ADDR) TRISA;
173 extern __sfr __at (TRISB_ADDR) TRISB;
174 extern __sfr __at (TRISCP_ADDR) TRISCP; // C712/C716 compatibility
176 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (PR2_ADDR) PR2;
179 extern __sfr __at (ADCON1_ADDR) ADCON1;
181 //----- STATUS Bits --------------------------------------------------------
184 //----- PORTB Bits --------------------------------------------------------
187 //----- INTCON Bits --------------------------------------------------------
190 //----- PIR1 Bits ----------------------------------------------------------
193 //----- T1CON Bits ---------------------------------------------------------
196 //----- T2CON Bits ---------------------------------------------------------
200 //----- CCP1CON Bits -------------------------------------------------------
203 //----- PWM1CON Bits -------------------------------------------------------
206 //----- ECCPAS Bits --------------------------------------------------------
210 //----- ADCON0 Bits --------------------------------------------------------
213 //----- OPTION Bits --------------------------------------------------------
216 //----- TRISB Bits --------------------------------------------------------
220 //----- PIE1 Bits ----------------------------------------------------------
223 //----- PCON Bits ----------------------------------------------------------
227 //----- ADCON1 Bits --------------------------------------------------------
230 //==========================================================================
234 //==========================================================================
237 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1A'-H'1D'
238 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E'
240 //==========================================================================
242 // Configuration Bits
244 //==========================================================================
246 #define _BODEN_ON 0x3FFF // C712/C716 compatibility
247 #define _BODEN_OFF 0x3FBF // C712/C716 compatibility
248 #define _BOREN_ON 0x3FFF
249 #define _BOREN_OFF 0x3FBF
250 #define _VBOR_25 0x3F7F
251 #define _VBOR_40 0x3FFF
252 #define _CP_ON 0x1FFF
253 #define _CP_ALL 0x1FFF // C712/C716 compatibility
254 #define _CP_OFF 0x3FFF
255 #define _PWRTE_OFF 0x3FFF
256 #define _PWRTE_ON 0x3FF7
257 #define _WDT_ON 0x3FFF
258 #define _WDT_OFF 0x3FFB
259 #define _LP_OSC 0x3FFC
260 #define _XT_OSC 0x3FFD
261 #define _HS_OSC 0x3FFE
262 #define _RC_OSC 0x3FFF
266 // ----- ADCON0 bits --------------------
269 unsigned char ADON:1;
272 unsigned char CHS0:1;
273 unsigned char CHS1:1;
274 unsigned char CHS2:1;
275 unsigned char ADCS0:1;
276 unsigned char ADCS1:1;
281 unsigned char NOT_DONE:1;
291 unsigned char GO_DONE:1;
299 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
301 #define ADON ADCON0_bits.ADON
302 #define GO ADCON0_bits.GO
303 #define NOT_DONE ADCON0_bits.NOT_DONE
304 #define GO_DONE ADCON0_bits.GO_DONE
305 #define CHS0 ADCON0_bits.CHS0
306 #define CHS1 ADCON0_bits.CHS1
307 #define CHS2 ADCON0_bits.CHS2
308 #define ADCS0 ADCON0_bits.ADCS0
309 #define ADCS1 ADCON0_bits.ADCS1
311 // ----- ADCON1 bits --------------------
314 unsigned char PCFG0:1;
315 unsigned char PCFG1:1;
316 unsigned char PCFG2:1;
324 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
326 #define PCFG0 ADCON1_bits.PCFG0
327 #define PCFG1 ADCON1_bits.PCFG1
328 #define PCFG2 ADCON1_bits.PCFG2
330 // ----- CCP1CON bits --------------------
333 unsigned char CCP1M0:1;
334 unsigned char CCP1M1:1;
335 unsigned char CCP1M2:1;
336 unsigned char CCP1M3:1;
337 unsigned char DC1B0:1;
338 unsigned char DC1B1:1;
339 unsigned char P1M0:1;
340 unsigned char P1M1:1;
343 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
345 #define CCP1M0 CCP1CON_bits.CCP1M0
346 #define CCP1M1 CCP1CON_bits.CCP1M1
347 #define CCP1M2 CCP1CON_bits.CCP1M2
348 #define CCP1M3 CCP1CON_bits.CCP1M3
349 #define DC1B0 CCP1CON_bits.DC1B0
350 #define DC1B1 CCP1CON_bits.DC1B1
351 #define P1M0 CCP1CON_bits.P1M0
352 #define P1M1 CCP1CON_bits.P1M1
354 // ----- ECCPAS bits --------------------
357 unsigned char PSSBD0:1;
358 unsigned char PSSBD1:1;
359 unsigned char PSSAC0:1;
360 unsigned char PSSAC1:1;
361 unsigned char ECCPAS0:1;
362 unsigned char ECCPAS1:1;
364 unsigned char ECCPASE:1;
367 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
369 #define PSSBD0 ECCPAS_bits.PSSBD0
370 #define PSSBD1 ECCPAS_bits.PSSBD1
371 #define PSSAC0 ECCPAS_bits.PSSAC0
372 #define PSSAC1 ECCPAS_bits.PSSAC1
373 #define ECCPAS0 ECCPAS_bits.ECCPAS0
374 #define ECCPAS1 ECCPAS_bits.ECCPAS1
375 #define ECCPASE ECCPAS_bits.ECCPASE
377 // ----- INTCON bits --------------------
380 unsigned char RBIF:1;
381 unsigned char INTF:1;
382 unsigned char T0IF:1;
383 unsigned char RBIE:1;
384 unsigned char INTE:1;
385 unsigned char T0IE:1;
386 unsigned char PEIE:1;
390 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
392 #define RBIF INTCON_bits.RBIF
393 #define INTF INTCON_bits.INTF
394 #define T0IF INTCON_bits.T0IF
395 #define RBIE INTCON_bits.RBIE
396 #define INTE INTCON_bits.INTE
397 #define T0IE INTCON_bits.T0IE
398 #define PEIE INTCON_bits.PEIE
399 #define GIE INTCON_bits.GIE
401 // ----- OPTION_REG bits --------------------
408 unsigned char T0SE:1;
409 unsigned char T0CS:1;
410 unsigned char INTEDG:1;
411 unsigned char NOT_RBPU:1;
413 } __OPTION_REG_bits_t;
414 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
416 #define PS0 OPTION_REG_bits.PS0
417 #define PS1 OPTION_REG_bits.PS1
418 #define PS2 OPTION_REG_bits.PS2
419 #define PSA OPTION_REG_bits.PSA
420 #define T0SE OPTION_REG_bits.T0SE
421 #define T0CS OPTION_REG_bits.T0CS
422 #define INTEDG OPTION_REG_bits.INTEDG
423 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
425 // ----- PCON bits --------------------
428 unsigned char NOT_BO:1;
429 unsigned char NOT_POR:1;
438 unsigned char NOT_BOD:1;
448 unsigned char NOT_BOR:1;
458 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
460 #define NOT_BO PCON_bits.NOT_BO
461 #define NOT_BOD PCON_bits.NOT_BOD
462 #define NOT_BOR PCON_bits.NOT_BOR
463 #define NOT_POR PCON_bits.NOT_POR
465 // ----- PIE1 bits --------------------
468 unsigned char TMR1IE:1;
469 unsigned char TMR2IE:1;
470 unsigned char CCP1IE:1;
474 unsigned char ADIE:1;
478 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
480 #define TMR1IE PIE1_bits.TMR1IE
481 #define TMR2IE PIE1_bits.TMR2IE
482 #define CCP1IE PIE1_bits.CCP1IE
483 #define ADIE PIE1_bits.ADIE
485 // ----- PIR1 bits --------------------
488 unsigned char TMR1IF:1;
489 unsigned char TMR2IF:1;
490 unsigned char CCP1IF:1;
494 unsigned char ADIF:1;
498 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
500 #define TMR1IF PIR1_bits.TMR1IF
501 #define TMR2IF PIR1_bits.TMR2IF
502 #define CCP1IF PIR1_bits.CCP1IF
503 #define ADIF PIR1_bits.ADIF
505 // ----- PORTB bits --------------------
509 unsigned char DT1CK:1;
511 unsigned char DCCP:1;
518 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
520 #define DT1CK PORTB_bits.DT1CK
521 #define DCCP PORTB_bits.DCCP
523 // ----- PWM1CON bits --------------------
526 unsigned char PDC0:1;
527 unsigned char PDC1:1;
528 unsigned char PDC2:1;
529 unsigned char PDC3:1;
530 unsigned char PDC4:1;
531 unsigned char PDC5:1;
532 unsigned char PDC6:1;
533 unsigned char PRSEN:1;
536 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
538 #define PDC0 PWM1CON_bits.PDC0
539 #define PDC1 PWM1CON_bits.PDC1
540 #define PDC2 PWM1CON_bits.PDC2
541 #define PDC3 PWM1CON_bits.PDC3
542 #define PDC4 PWM1CON_bits.PDC4
543 #define PDC5 PWM1CON_bits.PDC5
544 #define PDC6 PWM1CON_bits.PDC6
545 #define PRSEN PWM1CON_bits.PRSEN
547 // ----- STATUS bits --------------------
553 unsigned char NOT_PD:1;
554 unsigned char NOT_TO:1;
560 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
562 #define C STATUS_bits.C
563 #define DC STATUS_bits.DC
564 #define Z STATUS_bits.Z
565 #define NOT_PD STATUS_bits.NOT_PD
566 #define NOT_TO STATUS_bits.NOT_TO
567 #define RP0 STATUS_bits.RP0
568 #define RP1 STATUS_bits.RP1
569 #define IRP STATUS_bits.IRP
571 // ----- T1CON bits --------------------
574 unsigned char TMR1ON:1;
575 unsigned char TMR1CS:1;
576 unsigned char T1SYNC:1;
577 unsigned char T1OSCEN:1;
578 unsigned char T1CKPS0:1;
579 unsigned char T1CKPS1:1;
586 unsigned char NOT_T1SYNC:1;
594 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
596 #define TMR1ON T1CON_bits.TMR1ON
597 #define TMR1CS T1CON_bits.TMR1CS
598 #define T1SYNC T1CON_bits.T1SYNC
599 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
600 #define T1OSCEN T1CON_bits.T1OSCEN
601 #define T1CKPS0 T1CON_bits.T1CKPS0
602 #define T1CKPS1 T1CON_bits.T1CKPS1
604 // ----- T2CON bits --------------------
607 unsigned char T2CKPS0:1;
608 unsigned char T2CKPS1:1;
609 unsigned char TMR2ON:1;
610 unsigned char TOUTPS0:1;
611 unsigned char TOUTPS1:1;
612 unsigned char TOUTPS2:1;
613 unsigned char TOUTPS3:1;
617 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
619 #define T2CKPS0 T2CON_bits.T2CKPS0
620 #define T2CKPS1 T2CON_bits.T2CKPS1
621 #define TMR2ON T2CON_bits.TMR2ON
622 #define TOUTPS0 T2CON_bits.TOUTPS0
623 #define TOUTPS1 T2CON_bits.TOUTPS1
624 #define TOUTPS2 T2CON_bits.TOUTPS2
625 #define TOUTPS3 T2CON_bits.TOUTPS3
627 // ----- TRISB bits --------------------
631 unsigned char TT1CK:1;
633 unsigned char TCCP:1;
640 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
642 #define TT1CK TRISB_bits.TT1CK
643 #define TCCP TRISB_bits.TCCP