2 // Register Declarations for Microchip 16F690 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define PWM1CON_ADDR 0x001C
54 #define ECCPAS_ADDR 0x001D
55 #define ADRESH_ADDR 0x001E
56 #define ADCON0_ADDR 0x001F
57 #define OPTION_REG_ADDR 0x0081
58 #define TRISA_ADDR 0x0085
59 #define TRISB_ADDR 0x0086
60 #define TRISC_ADDR 0x0087
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define MSK_ADDR 0x0093
69 #define SSPMSK_ADDR 0x0093
70 #define SSPSTAT_ADDR 0x0094
71 #define WPU_ADDR 0x0095
72 #define WPUA_ADDR 0x0095
73 #define IOC_ADDR 0x0096
74 #define IOCA_ADDR 0x0096
75 #define WDTCON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define SPBRGH_ADDR 0x009A
79 #define BAUDCTL_ADDR 0x009B
80 #define ADRESL_ADDR 0x009E
81 #define ADCON1_ADDR 0x009F
82 #define EEDAT_ADDR 0x010C
83 #define EEDATA_ADDR 0x010C
84 #define EEADR_ADDR 0x010D
85 #define EEDATH_ADDR 0x010E
86 #define EEADRH_ADDR 0x010F
87 #define WPUB_ADDR 0x0115
88 #define IOCB_ADDR 0x0116
89 #define VRCON_ADDR 0x0118
90 #define CM1CON0_ADDR 0x0119
91 #define CM2CON0_ADDR 0x011A
92 #define CM2CON1_ADDR 0x011B
93 #define ANSEL_ADDR 0x011E
94 #define ANSELH_ADDR 0x011F
95 #define EECON1_ADDR 0x018C
96 #define EECON2_ADDR 0x018D
97 #define PSTRCON_ADDR 0x019D
98 #define SRCON_ADDR 0x019E
101 // Memory organization.
107 // P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
110 // This header file defines configurations, registers, and other useful bits of
111 // information for the PIC16F690 microcontroller. These names are taken to match
112 // the data sheets as closely as possible.
114 // Note that the processor must be selected before this file is
115 // included. The processor may be selected the following ways:
117 // 1. Command line switch:
118 // C:\ MPASM MYFILE.ASM /PIC16F690
119 // 2. LIST directive in the source file
121 // 3. Processor Type entry in the MPASM full-screen interface
123 //==========================================================================
127 //==========================================================================
128 //1.00 10/12/04 Original
129 //==========================================================================
133 //==========================================================================
136 // MESSG "Processor-header file mismatch. Verify selected processor."
139 //==========================================================================
141 // Register Definitions
143 //==========================================================================
148 //----- Register Files------------------------------------------------------
150 extern __sfr __at (INDF_ADDR) INDF;
151 extern __sfr __at (TMR0_ADDR) TMR0;
152 extern __sfr __at (PCL_ADDR) PCL;
153 extern __sfr __at (STATUS_ADDR) STATUS;
154 extern __sfr __at (FSR_ADDR) FSR;
155 extern __sfr __at (PORTA_ADDR) PORTA;
156 extern __sfr __at (PORTB_ADDR) PORTB;
157 extern __sfr __at (PORTC_ADDR) PORTC;
159 extern __sfr __at (PCLATH_ADDR) PCLATH;
160 extern __sfr __at (INTCON_ADDR) INTCON;
161 extern __sfr __at (PIR1_ADDR) PIR1;
162 extern __sfr __at (PIR2_ADDR) PIR2;
163 extern __sfr __at (TMR1L_ADDR) TMR1L;
164 extern __sfr __at (TMR1H_ADDR) TMR1H;
165 extern __sfr __at (T1CON_ADDR) T1CON;
166 extern __sfr __at (TMR2_ADDR) TMR2;
167 extern __sfr __at (T2CON_ADDR) T2CON;
168 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
169 extern __sfr __at (SSPCON_ADDR) SSPCON;
170 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
171 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
172 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
173 extern __sfr __at (RCSTA_ADDR) RCSTA;
174 extern __sfr __at (TXREG_ADDR) TXREG;
175 extern __sfr __at (RCREG_ADDR) RCREG;
177 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
178 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
179 extern __sfr __at (ADRESH_ADDR) ADRESH;
180 extern __sfr __at (ADCON0_ADDR) ADCON0;
183 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
185 extern __sfr __at (TRISA_ADDR) TRISA;
186 extern __sfr __at (TRISB_ADDR) TRISB;
187 extern __sfr __at (TRISC_ADDR) TRISC;
189 extern __sfr __at (PIE1_ADDR) PIE1;
190 extern __sfr __at (PIE2_ADDR) PIE2;
191 extern __sfr __at (PCON_ADDR) PCON;
192 extern __sfr __at (OSCCON_ADDR) OSCCON;
193 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
195 extern __sfr __at (PR2_ADDR) PR2;
196 extern __sfr __at (SSPADD_ADDR) SSPADD;
197 extern __sfr __at (MSK_ADDR) MSK;
198 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
199 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
200 extern __sfr __at (WPU_ADDR) WPU;
201 extern __sfr __at (WPUA_ADDR) WPUA;
202 extern __sfr __at (IOC_ADDR) IOC;
203 extern __sfr __at (IOCA_ADDR) IOCA;
204 extern __sfr __at (WDTCON_ADDR) WDTCON;
205 extern __sfr __at (TXSTA_ADDR) TXSTA;
206 extern __sfr __at (SPBRG_ADDR) SPBRG;
207 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
208 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
211 extern __sfr __at (ADRESL_ADDR) ADRESL;
212 extern __sfr __at (ADCON1_ADDR) ADCON1;
215 extern __sfr __at (EEDAT_ADDR) EEDAT;
216 extern __sfr __at (EEDATA_ADDR) EEDATA;
217 extern __sfr __at (EEADR_ADDR) EEADR;
218 extern __sfr __at (EEDATH_ADDR) EEDATH;
219 extern __sfr __at (EEADRH_ADDR) EEADRH;
222 extern __sfr __at (WPUB_ADDR) WPUB;
223 extern __sfr __at (IOCB_ADDR) IOCB;
225 extern __sfr __at (VRCON_ADDR) VRCON;
226 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
227 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
228 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
230 extern __sfr __at (ANSEL_ADDR) ANSEL;
231 extern __sfr __at (ANSELH_ADDR) ANSELH;
233 extern __sfr __at (EECON1_ADDR) EECON1;
234 extern __sfr __at (EECON2_ADDR) EECON2;
237 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
238 extern __sfr __at (SRCON_ADDR) SRCON;
242 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
243 //----- STATUS Bits --------------------------------------------------------
246 //----- INTCON Bits --------------------------------------------------------
249 //----- PIR1 Bits ----------------------------------------------------------
252 //----- PIR2 Bits ----------------------------------------------------------
255 //----- T1CON Bits ---------------------------------------------------------
258 //----- T2CON Bits ---------------------------------------------------------
261 //----- SSPCON Bits -------------------------------------------------------
264 //----- CCP1CON Bits -------------------------------------------------------
267 //----- RCSTA Bits ---------------------------------------------------------
270 //----- PWM1CON Bits -------------------------------------------------------
273 //----- ECCPAS Bits --------------------------------------------------------
276 //----- ADCON0 Bits --------------------------------------------------------
279 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
280 //----- OPTION Bits --------------------------------------------------------
283 //----- TRISA Bits --------------------------------------------------------
286 //----- TRISB Bits --------------------------------------------------------
289 //----- TRISC Bits --------------------------------------------------------
292 //----- PIE1 Bits ----------------------------------------------------------
295 //----- PIE2 Bits ----------------------------------------------------------
298 //----- PCON Bits ----------------------------------------------------------
301 //----- OSCCON Bits --------------------------------------------------------
304 //----- OSCTUNE Bits -------------------------------------------------------
307 //----- SSPSTAT Bits --------------------------------------------------------
310 //----- WPUA --------------------------------------------------------------
314 //----- IOC --------------------------------------------------------------
317 //----- IOCA --------------------------------------------------------------
320 //----- WDTCON Bits --------------------------------------------------------
323 //----- TXSTA Bits -------------------------------------------------------
326 //----- SPBRG Bits -------------------------------------------------------
329 //----- SPBRGH Bits -------------------------------------------------------
332 //----- BAUDCTL Bits -------------------------------------------------------
337 //----- ADCON1 -------------------------------------------------------------
340 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
341 //----- WPUB Bits ----------------------------------------------------------
344 //----- IOCB --------------------------------------------------------------
347 //----- VRCON Bits ---------------------------------------------------------
350 //----- CM1CON0 Bits -------------------------------------------------------
354 //----- CM2CON0 Bits -------------------------------------------------------
358 //----- CM2CON1 Bits -------------------------------------------------------
361 //----- ANSELH -------------------------------------------------------------
364 //----- ANSEL --------------------------------------------------------------
367 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
368 //----- EECON1 -------------------------------------------------------------
371 //----- PSTRCON -------------------------------------------------------------
374 //----- SRCON ---------------------------------------------------------------
377 //==========================================================================
381 //==========================================================================
384 // __BADRAM H'08'-H'09', H'1B'
385 // __BADRAM H'88'-H'89', H'91', H'9C'-H'9D'
386 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
387 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
389 //==========================================================================
391 // Configuration Bits
393 //==========================================================================
395 #define _FCMEN_ON 0x3FFF
396 #define _FCMEN_OFF 0x37FF
397 #define _IESO_ON 0x3FFF
398 #define _IESO_OFF 0x3BFF
399 #define _BOR_ON 0x3FFF
400 #define _BOR_NSLEEP 0x3EFF
401 #define _BOR_SBODEN 0x3DFF
402 #define _BOR_OFF 0x3CFF
403 #define _CPD_ON 0x3F7F
404 #define _CPD_OFF 0x3FFF
405 #define _CP_ON 0x3FBF
406 #define _CP_OFF 0x3FFF
407 #define _MCLRE_ON 0x3FFF
408 #define _MCLRE_OFF 0x3FDF
409 #define _PWRTE_OFF 0x3FFF
410 #define _PWRTE_ON 0x3FEF
411 #define _WDT_ON 0x3FFF
412 #define _WDT_OFF 0x3FF7
413 #define _LP_OSC 0x3FF8
414 #define _XT_OSC 0x3FF9
415 #define _HS_OSC 0x3FFA
416 #define _EC_OSC 0x3FFB
417 #define _INTRC_OSC_NOCLKOUT 0x3FFC
418 #define _INTRC_OSC_CLKOUT 0x3FFD
419 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
420 #define _EXTRC_OSC_CLKOUT 0x3FFF
421 #define _INTOSCIO 0x3FFC
422 #define _INTOSC 0x3FFD
423 #define _EXTRCIO 0x3FFE
424 #define _EXTRC 0x3FFF
428 // ----- ADCON0 bits --------------------
431 unsigned char ADON:1;
433 unsigned char CHS0:1;
434 unsigned char CHS1:1;
435 unsigned char CHS2:1;
436 unsigned char CHS3:1;
437 unsigned char VCFG:1;
438 unsigned char ADFM:1;
442 unsigned char NOT_DONE:1;
452 unsigned char GO_DONE:1;
461 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
463 #ifndef NO_BIT_DEFINES
464 #define ADON ADCON0_bits.ADON
465 #define GO ADCON0_bits.GO
466 #define NOT_DONE ADCON0_bits.NOT_DONE
467 #define GO_DONE ADCON0_bits.GO_DONE
468 #define CHS0 ADCON0_bits.CHS0
469 #define CHS1 ADCON0_bits.CHS1
470 #define CHS2 ADCON0_bits.CHS2
471 #define CHS3 ADCON0_bits.CHS3
472 #define VCFG ADCON0_bits.VCFG
473 #define ADFM ADCON0_bits.ADFM
474 #endif /* NO_BIT_DEFINES */
476 // ----- ADCON1 bits --------------------
483 unsigned char ADCS0:1;
484 unsigned char ADCS1:1;
485 unsigned char ADCS2:1;
489 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
491 #ifndef NO_BIT_DEFINES
492 #define ADCS0 ADCON1_bits.ADCS0
493 #define ADCS1 ADCON1_bits.ADCS1
494 #define ADCS2 ADCON1_bits.ADCS2
495 #endif /* NO_BIT_DEFINES */
497 // ----- ANSEL bits --------------------
500 unsigned char ANS0:1;
501 unsigned char ANS1:1;
502 unsigned char ANS2:1;
503 unsigned char ANS3:1;
504 unsigned char ANS4:1;
505 unsigned char ANS5:1;
506 unsigned char ANS6:1;
507 unsigned char ANS7:1;
510 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
512 #ifndef NO_BIT_DEFINES
513 #define ANS0 ANSEL_bits.ANS0
514 #define ANS1 ANSEL_bits.ANS1
515 #define ANS2 ANSEL_bits.ANS2
516 #define ANS3 ANSEL_bits.ANS3
517 #define ANS4 ANSEL_bits.ANS4
518 #define ANS5 ANSEL_bits.ANS5
519 #define ANS6 ANSEL_bits.ANS6
520 #define ANS7 ANSEL_bits.ANS7
521 #endif /* NO_BIT_DEFINES */
523 // ----- ANSELH bits --------------------
526 unsigned char ANS8:1;
527 unsigned char ANS9:1;
528 unsigned char ANS10:1;
529 unsigned char ANS11:1;
536 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
538 #ifndef NO_BIT_DEFINES
539 #define ANS8 ANSELH_bits.ANS8
540 #define ANS9 ANSELH_bits.ANS9
541 #define ANS10 ANSELH_bits.ANS10
542 #define ANS11 ANSELH_bits.ANS11
543 #endif /* NO_BIT_DEFINES */
545 // ----- BAUDCTL bits --------------------
548 unsigned char ABDEN:1;
551 unsigned char BRG16:1;
552 unsigned char SCKP:1;
554 unsigned char RCIDL:1;
555 unsigned char ABDOVF:1;
558 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
560 #ifndef NO_BIT_DEFINES
561 #define ABDEN BAUDCTL_bits.ABDEN
562 #define WUE BAUDCTL_bits.WUE
563 #define BRG16 BAUDCTL_bits.BRG16
564 #define SCKP BAUDCTL_bits.SCKP
565 #define RCIDL BAUDCTL_bits.RCIDL
566 #define ABDOVF BAUDCTL_bits.ABDOVF
567 #endif /* NO_BIT_DEFINES */
569 // ----- CCP1CON bits --------------------
572 unsigned char CCP1M0:1;
573 unsigned char CCP1M1:1;
574 unsigned char CCP1M2:1;
575 unsigned char CCP1M3:1;
576 unsigned char DC1B0:1;
577 unsigned char DC1B1:1;
578 unsigned char P1M0:1;
579 unsigned char P1M1:1;
582 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
584 #ifndef NO_BIT_DEFINES
585 #define CCP1M0 CCP1CON_bits.CCP1M0
586 #define CCP1M1 CCP1CON_bits.CCP1M1
587 #define CCP1M2 CCP1CON_bits.CCP1M2
588 #define CCP1M3 CCP1CON_bits.CCP1M3
589 #define DC1B0 CCP1CON_bits.DC1B0
590 #define DC1B1 CCP1CON_bits.DC1B1
591 #define P1M0 CCP1CON_bits.P1M0
592 #define P1M1 CCP1CON_bits.P1M1
593 #endif /* NO_BIT_DEFINES */
595 // ----- CM1CON0 bits --------------------
598 unsigned char C1CH0:1;
599 unsigned char C1CH1:1;
602 unsigned char C1POL:1;
603 unsigned char C1OE:1;
604 unsigned char C1OUT:1;
605 unsigned char C1ON:1;
608 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
610 #ifndef NO_BIT_DEFINES
611 #define C1CH0 CM1CON0_bits.C1CH0
612 #define C1CH1 CM1CON0_bits.C1CH1
613 #define C1R CM1CON0_bits.C1R
614 #define C1POL CM1CON0_bits.C1POL
615 #define C1OE CM1CON0_bits.C1OE
616 #define C1OUT CM1CON0_bits.C1OUT
617 #define C1ON CM1CON0_bits.C1ON
618 #endif /* NO_BIT_DEFINES */
620 // ----- CM2CON0 bits --------------------
623 unsigned char C2CH0:1;
624 unsigned char C2CH1:1;
627 unsigned char C2POL:1;
628 unsigned char C2OE:1;
629 unsigned char C2OUT:1;
630 unsigned char C2ON:1;
633 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
635 #ifndef NO_BIT_DEFINES
636 #define C2CH0 CM2CON0_bits.C2CH0
637 #define C2CH1 CM2CON0_bits.C2CH1
638 #define C2R CM2CON0_bits.C2R
639 #define C2POL CM2CON0_bits.C2POL
640 #define C2OE CM2CON0_bits.C2OE
641 #define C2OUT CM2CON0_bits.C2OUT
642 #define C2ON CM2CON0_bits.C2ON
643 #endif /* NO_BIT_DEFINES */
645 // ----- CM2CON1 bits --------------------
648 unsigned char C2SYNC:1;
649 unsigned char T1GSS:1;
654 unsigned char MC2OUT:1;
655 unsigned char MC1OUT:1;
658 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
660 #ifndef NO_BIT_DEFINES
661 #define C2SYNC CM2CON1_bits.C2SYNC
662 #define T1GSS CM2CON1_bits.T1GSS
663 #define MC2OUT CM2CON1_bits.MC2OUT
664 #define MC1OUT CM2CON1_bits.MC1OUT
665 #endif /* NO_BIT_DEFINES */
667 // ----- ECCPAS bits --------------------
670 unsigned char PSSBD0:1;
671 unsigned char PSSBD1:1;
672 unsigned char PSSAC0:1;
673 unsigned char PSSAC1:1;
674 unsigned char ECCPAS0:1;
675 unsigned char ECCPAS1:1;
676 unsigned char ECCPAS2:1;
677 unsigned char ECCPASE:1;
680 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
682 #ifndef NO_BIT_DEFINES
683 #define PSSBD0 ECCPAS_bits.PSSBD0
684 #define PSSBD1 ECCPAS_bits.PSSBD1
685 #define PSSAC0 ECCPAS_bits.PSSAC0
686 #define PSSAC1 ECCPAS_bits.PSSAC1
687 #define ECCPAS0 ECCPAS_bits.ECCPAS0
688 #define ECCPAS1 ECCPAS_bits.ECCPAS1
689 #define ECCPAS2 ECCPAS_bits.ECCPAS2
690 #define ECCPASE ECCPAS_bits.ECCPASE
691 #endif /* NO_BIT_DEFINES */
693 // ----- EECON1 bits --------------------
698 unsigned char WREN:1;
699 unsigned char WRERR:1;
703 unsigned char EEPGD:1;
706 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
708 #ifndef NO_BIT_DEFINES
709 #define RD EECON1_bits.RD
710 #define WR EECON1_bits.WR
711 #define WREN EECON1_bits.WREN
712 #define WRERR EECON1_bits.WRERR
713 #define EEPGD EECON1_bits.EEPGD
714 #endif /* NO_BIT_DEFINES */
716 // ----- INTCON bits --------------------
719 unsigned char RABIF:1;
720 unsigned char INTF:1;
721 unsigned char T0IF:1;
722 unsigned char RABIE:1;
723 unsigned char INTE:1;
724 unsigned char T0IE:1;
725 unsigned char PEIE:1;
729 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
731 #ifndef NO_BIT_DEFINES
732 #define RABIF INTCON_bits.RABIF
733 #define INTF INTCON_bits.INTF
734 #define T0IF INTCON_bits.T0IF
735 #define RABIE INTCON_bits.RABIE
736 #define INTE INTCON_bits.INTE
737 #define T0IE INTCON_bits.T0IE
738 #define PEIE INTCON_bits.PEIE
739 #define GIE INTCON_bits.GIE
740 #endif /* NO_BIT_DEFINES */
742 // ----- IOC bits --------------------
745 unsigned char IOC0:1;
746 unsigned char IOC1:1;
747 unsigned char IOC2:1;
748 unsigned char IOC3:1;
749 unsigned char IOC4:1;
750 unsigned char IOC5:1;
755 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
757 #ifndef NO_BIT_DEFINES
758 #define IOC0 IOC_bits.IOC0
759 #define IOC1 IOC_bits.IOC1
760 #define IOC2 IOC_bits.IOC2
761 #define IOC3 IOC_bits.IOC3
762 #define IOC4 IOC_bits.IOC4
763 #define IOC5 IOC_bits.IOC5
764 #endif /* NO_BIT_DEFINES */
766 // ----- IOCA bits --------------------
769 unsigned char IOCA0:1;
770 unsigned char IOCA1:1;
771 unsigned char IOCA2:1;
772 unsigned char IOCA3:1;
773 unsigned char IOCA4:1;
774 unsigned char IOCA5:1;
779 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
781 #ifndef NO_BIT_DEFINES
782 #define IOCA0 IOCA_bits.IOCA0
783 #define IOCA1 IOCA_bits.IOCA1
784 #define IOCA2 IOCA_bits.IOCA2
785 #define IOCA3 IOCA_bits.IOCA3
786 #define IOCA4 IOCA_bits.IOCA4
787 #define IOCA5 IOCA_bits.IOCA5
788 #endif /* NO_BIT_DEFINES */
790 // ----- IOCB bits --------------------
797 unsigned char IOCB4:1;
798 unsigned char IOCB5:1;
799 unsigned char IOCB6:1;
800 unsigned char IOCB7:1;
803 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
805 #ifndef NO_BIT_DEFINES
806 #define IOCB4 IOCB_bits.IOCB4
807 #define IOCB5 IOCB_bits.IOCB5
808 #define IOCB6 IOCB_bits.IOCB6
809 #define IOCB7 IOCB_bits.IOCB7
810 #endif /* NO_BIT_DEFINES */
812 // ----- OPTION_REG bits --------------------
819 unsigned char T0SE:1;
820 unsigned char T0CS:1;
821 unsigned char INTEDG:1;
822 unsigned char NOT_RABPU:1;
824 } __OPTION_REG_bits_t;
825 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
827 #ifndef NO_BIT_DEFINES
828 #define PS0 OPTION_REG_bits.PS0
829 #define PS1 OPTION_REG_bits.PS1
830 #define PS2 OPTION_REG_bits.PS2
831 #define PSA OPTION_REG_bits.PSA
832 #define T0SE OPTION_REG_bits.T0SE
833 #define T0CS OPTION_REG_bits.T0CS
834 #define INTEDG OPTION_REG_bits.INTEDG
835 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
836 #endif /* NO_BIT_DEFINES */
838 // ----- OSCCON bits --------------------
844 unsigned char OSTS:1;
845 unsigned char IRCF0:1;
846 unsigned char IRCF1:1;
847 unsigned char IRCF2:1;
851 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
853 #ifndef NO_BIT_DEFINES
854 #define SCS OSCCON_bits.SCS
855 #define LTS OSCCON_bits.LTS
856 #define HTS OSCCON_bits.HTS
857 #define OSTS OSCCON_bits.OSTS
858 #define IRCF0 OSCCON_bits.IRCF0
859 #define IRCF1 OSCCON_bits.IRCF1
860 #define IRCF2 OSCCON_bits.IRCF2
861 #endif /* NO_BIT_DEFINES */
863 // ----- OSCTUNE bits --------------------
866 unsigned char TUN0:1;
867 unsigned char TUN1:1;
868 unsigned char TUN2:1;
869 unsigned char TUN3:1;
870 unsigned char TUN4:1;
876 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
878 #ifndef NO_BIT_DEFINES
879 #define TUN0 OSCTUNE_bits.TUN0
880 #define TUN1 OSCTUNE_bits.TUN1
881 #define TUN2 OSCTUNE_bits.TUN2
882 #define TUN3 OSCTUNE_bits.TUN3
883 #define TUN4 OSCTUNE_bits.TUN4
884 #endif /* NO_BIT_DEFINES */
886 // ----- PCON bits --------------------
889 unsigned char NOT_BOR:1;
890 unsigned char NOT_POR:1;
893 unsigned char SBOREN:1;
894 unsigned char ULPWUE:1;
899 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
901 #ifndef NO_BIT_DEFINES
902 #define NOT_BOR PCON_bits.NOT_BOR
903 #define NOT_POR PCON_bits.NOT_POR
904 #define SBOREN PCON_bits.SBOREN
905 #define ULPWUE PCON_bits.ULPWUE
906 #endif /* NO_BIT_DEFINES */
908 // ----- PIE1 bits --------------------
911 unsigned char T1IE:1;
912 unsigned char T2IE:1;
913 unsigned char CCP1IE:1;
914 unsigned char SSPIE:1;
915 unsigned char TXIE:1;
916 unsigned char RCIE:1;
917 unsigned char ADIE:1;
921 unsigned char TMR1IE:1;
922 unsigned char TMR2IE:1;
931 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
933 #ifndef NO_BIT_DEFINES
934 #define T1IE PIE1_bits.T1IE
935 #define TMR1IE PIE1_bits.TMR1IE
936 #define T2IE PIE1_bits.T2IE
937 #define TMR2IE PIE1_bits.TMR2IE
938 #define CCP1IE PIE1_bits.CCP1IE
939 #define SSPIE PIE1_bits.SSPIE
940 #define TXIE PIE1_bits.TXIE
941 #define RCIE PIE1_bits.RCIE
942 #define ADIE PIE1_bits.ADIE
943 #endif /* NO_BIT_DEFINES */
945 // ----- PIE2 bits --------------------
952 unsigned char EEIE:1;
953 unsigned char C1IE:1;
954 unsigned char C2IE:1;
955 unsigned char OSFIE:1;
958 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
960 #ifndef NO_BIT_DEFINES
961 #define EEIE PIE2_bits.EEIE
962 #define C1IE PIE2_bits.C1IE
963 #define C2IE PIE2_bits.C2IE
964 #define OSFIE PIE2_bits.OSFIE
965 #endif /* NO_BIT_DEFINES */
967 // ----- PIR1 bits --------------------
970 unsigned char T1IF:1;
971 unsigned char T2IF:1;
972 unsigned char CCP1IF:1;
973 unsigned char SSPIF:1;
974 unsigned char TXIF:1;
975 unsigned char RCIF:1;
976 unsigned char ADIF:1;
980 unsigned char TMR1IF:1;
981 unsigned char TMR2IF:1;
990 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
992 #ifndef NO_BIT_DEFINES
993 #define T1IF PIR1_bits.T1IF
994 #define TMR1IF PIR1_bits.TMR1IF
995 #define T2IF PIR1_bits.T2IF
996 #define TMR2IF PIR1_bits.TMR2IF
997 #define CCP1IF PIR1_bits.CCP1IF
998 #define SSPIF PIR1_bits.SSPIF
999 #define TXIF PIR1_bits.TXIF
1000 #define RCIF PIR1_bits.RCIF
1001 #define ADIF PIR1_bits.ADIF
1002 #endif /* NO_BIT_DEFINES */
1004 // ----- PIR2 bits --------------------
1011 unsigned char EEIF:1;
1012 unsigned char C1IF:1;
1013 unsigned char C2IF:1;
1014 unsigned char OSFIF:1;
1017 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
1019 #ifndef NO_BIT_DEFINES
1020 #define EEIF PIR2_bits.EEIF
1021 #define C1IF PIR2_bits.C1IF
1022 #define C2IF PIR2_bits.C2IF
1023 #define OSFIF PIR2_bits.OSFIF
1024 #endif /* NO_BIT_DEFINES */
1026 // ----- PORTA bits --------------------
1029 unsigned char RA0:1;
1030 unsigned char RA1:1;
1031 unsigned char RA2:1;
1032 unsigned char RA3:1;
1033 unsigned char RA4:1;
1034 unsigned char RA5:1;
1039 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
1041 #ifndef NO_BIT_DEFINES
1042 #define RA0 PORTA_bits.RA0
1043 #define RA1 PORTA_bits.RA1
1044 #define RA2 PORTA_bits.RA2
1045 #define RA3 PORTA_bits.RA3
1046 #define RA4 PORTA_bits.RA4
1047 #define RA5 PORTA_bits.RA5
1048 #endif /* NO_BIT_DEFINES */
1050 // ----- PORTB bits --------------------
1053 unsigned char RB0:1;
1054 unsigned char RB1:1;
1055 unsigned char RB2:1;
1056 unsigned char RB3:1;
1057 unsigned char RB4:1;
1058 unsigned char RB5:1;
1059 unsigned char RB6:1;
1060 unsigned char RB7:1;
1063 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1065 #ifndef NO_BIT_DEFINES
1066 #define RB0 PORTB_bits.RB0
1067 #define RB1 PORTB_bits.RB1
1068 #define RB2 PORTB_bits.RB2
1069 #define RB3 PORTB_bits.RB3
1070 #define RB4 PORTB_bits.RB4
1071 #define RB5 PORTB_bits.RB5
1072 #define RB6 PORTB_bits.RB6
1073 #define RB7 PORTB_bits.RB7
1074 #endif /* NO_BIT_DEFINES */
1076 // ----- PORTC bits --------------------
1079 unsigned char RC0:1;
1080 unsigned char RC1:1;
1081 unsigned char RC2:1;
1082 unsigned char RC3:1;
1083 unsigned char RC4:1;
1084 unsigned char RC5:1;
1085 unsigned char RC6:1;
1086 unsigned char RC7:1;
1089 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1091 #ifndef NO_BIT_DEFINES
1092 #define RC0 PORTC_bits.RC0
1093 #define RC1 PORTC_bits.RC1
1094 #define RC2 PORTC_bits.RC2
1095 #define RC3 PORTC_bits.RC3
1096 #define RC4 PORTC_bits.RC4
1097 #define RC5 PORTC_bits.RC5
1098 #define RC6 PORTC_bits.RC6
1099 #define RC7 PORTC_bits.RC7
1100 #endif /* NO_BIT_DEFINES */
1102 // ----- PSTRCON bits --------------------
1105 unsigned char STRA:1;
1106 unsigned char STRB:1;
1107 unsigned char STRC:1;
1108 unsigned char STRD:1;
1109 unsigned char STRSYNC:1;
1115 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1117 #ifndef NO_BIT_DEFINES
1118 #define STRA PSTRCON_bits.STRA
1119 #define STRB PSTRCON_bits.STRB
1120 #define STRC PSTRCON_bits.STRC
1121 #define STRD PSTRCON_bits.STRD
1122 #define STRSYNC PSTRCON_bits.STRSYNC
1123 #endif /* NO_BIT_DEFINES */
1125 // ----- PWM1CON bits --------------------
1128 unsigned char PDC0:1;
1129 unsigned char PDC1:1;
1130 unsigned char PDC2:1;
1131 unsigned char PDC3:1;
1132 unsigned char PDC4:1;
1133 unsigned char PDC5:1;
1134 unsigned char PDC6:1;
1135 unsigned char PRSEN:1;
1138 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1140 #ifndef NO_BIT_DEFINES
1141 #define PDC0 PWM1CON_bits.PDC0
1142 #define PDC1 PWM1CON_bits.PDC1
1143 #define PDC2 PWM1CON_bits.PDC2
1144 #define PDC3 PWM1CON_bits.PDC3
1145 #define PDC4 PWM1CON_bits.PDC4
1146 #define PDC5 PWM1CON_bits.PDC5
1147 #define PDC6 PWM1CON_bits.PDC6
1148 #define PRSEN PWM1CON_bits.PRSEN
1149 #endif /* NO_BIT_DEFINES */
1151 // ----- RCSTA bits --------------------
1154 unsigned char RX9D:1;
1155 unsigned char OERR:1;
1156 unsigned char FERR:1;
1157 unsigned char ADDEN:1;
1158 unsigned char CREN:1;
1159 unsigned char SREN:1;
1160 unsigned char RX9:1;
1161 unsigned char SPEN:1;
1164 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1166 #ifndef NO_BIT_DEFINES
1167 #define RX9D RCSTA_bits.RX9D
1168 #define OERR RCSTA_bits.OERR
1169 #define FERR RCSTA_bits.FERR
1170 #define ADDEN RCSTA_bits.ADDEN
1171 #define CREN RCSTA_bits.CREN
1172 #define SREN RCSTA_bits.SREN
1173 #define RX9 RCSTA_bits.RX9
1174 #define SPEN RCSTA_bits.SPEN
1175 #endif /* NO_BIT_DEFINES */
1177 // ----- SPBRG bits --------------------
1180 unsigned char BRG0:1;
1181 unsigned char BRG1:1;
1182 unsigned char BRG2:1;
1183 unsigned char BRG3:1;
1184 unsigned char BRG4:1;
1185 unsigned char BRG5:1;
1186 unsigned char BRG6:1;
1187 unsigned char BRG7:1;
1190 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1192 #ifndef NO_BIT_DEFINES
1193 #define BRG0 SPBRG_bits.BRG0
1194 #define BRG1 SPBRG_bits.BRG1
1195 #define BRG2 SPBRG_bits.BRG2
1196 #define BRG3 SPBRG_bits.BRG3
1197 #define BRG4 SPBRG_bits.BRG4
1198 #define BRG5 SPBRG_bits.BRG5
1199 #define BRG6 SPBRG_bits.BRG6
1200 #define BRG7 SPBRG_bits.BRG7
1201 #endif /* NO_BIT_DEFINES */
1203 // ----- SPBRGH bits --------------------
1206 unsigned char BRG8:1;
1207 unsigned char BRG9:1;
1208 unsigned char BRG10:1;
1209 unsigned char BRG11:1;
1210 unsigned char BRG12:1;
1211 unsigned char BRG13:1;
1212 unsigned char BRG14:1;
1213 unsigned char BRG15:1;
1216 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1218 #ifndef NO_BIT_DEFINES
1219 #define BRG8 SPBRGH_bits.BRG8
1220 #define BRG9 SPBRGH_bits.BRG9
1221 #define BRG10 SPBRGH_bits.BRG10
1222 #define BRG11 SPBRGH_bits.BRG11
1223 #define BRG12 SPBRGH_bits.BRG12
1224 #define BRG13 SPBRGH_bits.BRG13
1225 #define BRG14 SPBRGH_bits.BRG14
1226 #define BRG15 SPBRGH_bits.BRG15
1227 #endif /* NO_BIT_DEFINES */
1229 // ----- SRCON bits --------------------
1234 unsigned char PULSR:1;
1235 unsigned char PULSS:1;
1236 unsigned char C2REN:1;
1237 unsigned char C1SEN:1;
1238 unsigned char SR0:1;
1239 unsigned char SR1:1;
1242 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1244 #ifndef NO_BIT_DEFINES
1245 #define PULSR SRCON_bits.PULSR
1246 #define PULSS SRCON_bits.PULSS
1247 #define C2REN SRCON_bits.C2REN
1248 #define C1SEN SRCON_bits.C1SEN
1249 #define SR0 SRCON_bits.SR0
1250 #define SR1 SRCON_bits.SR1
1251 #endif /* NO_BIT_DEFINES */
1253 // ----- SSPCON bits --------------------
1256 unsigned char SSPM0:1;
1257 unsigned char SSPM1:1;
1258 unsigned char SSPM2:1;
1259 unsigned char SSPM3:1;
1260 unsigned char CKP:1;
1261 unsigned char SSPEN:1;
1262 unsigned char SSPOV:1;
1263 unsigned char WCOL:1;
1266 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1268 #ifndef NO_BIT_DEFINES
1269 #define SSPM0 SSPCON_bits.SSPM0
1270 #define SSPM1 SSPCON_bits.SSPM1
1271 #define SSPM2 SSPCON_bits.SSPM2
1272 #define SSPM3 SSPCON_bits.SSPM3
1273 #define CKP SSPCON_bits.CKP
1274 #define SSPEN SSPCON_bits.SSPEN
1275 #define SSPOV SSPCON_bits.SSPOV
1276 #define WCOL SSPCON_bits.WCOL
1277 #endif /* NO_BIT_DEFINES */
1279 // ----- SSPSTAT bits --------------------
1288 unsigned char CKE:1;
1289 unsigned char SMP:1;
1294 unsigned char I2C_READ:1;
1295 unsigned char I2C_START:1;
1296 unsigned char I2C_STOP:1;
1297 unsigned char I2C_DATA:1;
1304 unsigned char NOT_W:1;
1307 unsigned char NOT_A:1;
1314 unsigned char NOT_WRITE:1;
1317 unsigned char NOT_ADDRESS:1;
1324 unsigned char R_W:1;
1327 unsigned char D_A:1;
1334 unsigned char READ_WRITE:1;
1337 unsigned char DATA_ADDRESS:1;
1342 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1344 #ifndef NO_BIT_DEFINES
1345 #define BF SSPSTAT_bits.BF
1346 #define UA SSPSTAT_bits.UA
1347 #define R SSPSTAT_bits.R
1348 #define I2C_READ SSPSTAT_bits.I2C_READ
1349 #define NOT_W SSPSTAT_bits.NOT_W
1350 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1351 #define R_W SSPSTAT_bits.R_W
1352 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1353 #define S SSPSTAT_bits.S
1354 #define I2C_START SSPSTAT_bits.I2C_START
1355 #define P SSPSTAT_bits.P
1356 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1357 #define D SSPSTAT_bits.D
1358 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1359 #define NOT_A SSPSTAT_bits.NOT_A
1360 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1361 #define D_A SSPSTAT_bits.D_A
1362 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1363 #define CKE SSPSTAT_bits.CKE
1364 #define SMP SSPSTAT_bits.SMP
1365 #endif /* NO_BIT_DEFINES */
1367 // ----- STATUS bits --------------------
1373 unsigned char NOT_PD:1;
1374 unsigned char NOT_TO:1;
1375 unsigned char RP0:1;
1376 unsigned char RP1:1;
1377 unsigned char IRP:1;
1380 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1382 #ifndef NO_BIT_DEFINES
1383 #define C STATUS_bits.C
1384 #define DC STATUS_bits.DC
1385 #define Z STATUS_bits.Z
1386 #define NOT_PD STATUS_bits.NOT_PD
1387 #define NOT_TO STATUS_bits.NOT_TO
1388 #define RP0 STATUS_bits.RP0
1389 #define RP1 STATUS_bits.RP1
1390 #define IRP STATUS_bits.IRP
1391 #endif /* NO_BIT_DEFINES */
1393 // ----- T1CON bits --------------------
1396 unsigned char TMR1ON:1;
1397 unsigned char TMR1CS:1;
1398 unsigned char NOT_T1SYNC:1;
1399 unsigned char T1OSCEN:1;
1400 unsigned char T1CKPS0:1;
1401 unsigned char T1CKPS1:1;
1402 unsigned char TMR1GE:1;
1403 unsigned char T1GINV:1;
1406 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1408 #ifndef NO_BIT_DEFINES
1409 #define TMR1ON T1CON_bits.TMR1ON
1410 #define TMR1CS T1CON_bits.TMR1CS
1411 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1412 #define T1OSCEN T1CON_bits.T1OSCEN
1413 #define T1CKPS0 T1CON_bits.T1CKPS0
1414 #define T1CKPS1 T1CON_bits.T1CKPS1
1415 #define TMR1GE T1CON_bits.TMR1GE
1416 #define T1GINV T1CON_bits.T1GINV
1417 #endif /* NO_BIT_DEFINES */
1419 // ----- T2CON bits --------------------
1422 unsigned char T2CKPS0:1;
1423 unsigned char T2CKPS1:1;
1424 unsigned char TMR2ON:1;
1425 unsigned char TOUTPS0:1;
1426 unsigned char TOUTPS1:1;
1427 unsigned char TOUTPS2:1;
1428 unsigned char TOUTPS3:1;
1432 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1434 #ifndef NO_BIT_DEFINES
1435 #define T2CKPS0 T2CON_bits.T2CKPS0
1436 #define T2CKPS1 T2CON_bits.T2CKPS1
1437 #define TMR2ON T2CON_bits.TMR2ON
1438 #define TOUTPS0 T2CON_bits.TOUTPS0
1439 #define TOUTPS1 T2CON_bits.TOUTPS1
1440 #define TOUTPS2 T2CON_bits.TOUTPS2
1441 #define TOUTPS3 T2CON_bits.TOUTPS3
1442 #endif /* NO_BIT_DEFINES */
1444 // ----- TRISA bits --------------------
1447 unsigned char TRISA0:1;
1448 unsigned char TRISA1:1;
1449 unsigned char TRISA2:1;
1450 unsigned char TRISA3:1;
1451 unsigned char TRISA4:1;
1452 unsigned char TRISA5:1;
1457 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1459 #ifndef NO_BIT_DEFINES
1460 #define TRISA0 TRISA_bits.TRISA0
1461 #define TRISA1 TRISA_bits.TRISA1
1462 #define TRISA2 TRISA_bits.TRISA2
1463 #define TRISA3 TRISA_bits.TRISA3
1464 #define TRISA4 TRISA_bits.TRISA4
1465 #define TRISA5 TRISA_bits.TRISA5
1466 #endif /* NO_BIT_DEFINES */
1468 // ----- TRISB bits --------------------
1475 unsigned char TRISB4:1;
1476 unsigned char TRISB5:1;
1477 unsigned char TRISB6:1;
1478 unsigned char TRISB7:1;
1481 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1483 #ifndef NO_BIT_DEFINES
1484 #define TRISB4 TRISB_bits.TRISB4
1485 #define TRISB5 TRISB_bits.TRISB5
1486 #define TRISB6 TRISB_bits.TRISB6
1487 #define TRISB7 TRISB_bits.TRISB7
1488 #endif /* NO_BIT_DEFINES */
1490 // ----- TRISC bits --------------------
1493 unsigned char TRISC0:1;
1494 unsigned char TRISC1:1;
1495 unsigned char TRISC2:1;
1496 unsigned char TRISC3:1;
1497 unsigned char TRISC4:1;
1498 unsigned char TRISC5:1;
1499 unsigned char TRISC6:1;
1500 unsigned char TRISC7:1;
1503 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1505 #ifndef NO_BIT_DEFINES
1506 #define TRISC0 TRISC_bits.TRISC0
1507 #define TRISC1 TRISC_bits.TRISC1
1508 #define TRISC2 TRISC_bits.TRISC2
1509 #define TRISC3 TRISC_bits.TRISC3
1510 #define TRISC4 TRISC_bits.TRISC4
1511 #define TRISC5 TRISC_bits.TRISC5
1512 #define TRISC6 TRISC_bits.TRISC6
1513 #define TRISC7 TRISC_bits.TRISC7
1514 #endif /* NO_BIT_DEFINES */
1516 // ----- TXSTA bits --------------------
1519 unsigned char TX9D:1;
1520 unsigned char TRMT:1;
1521 unsigned char BRGH:1;
1522 unsigned char SENB:1;
1523 unsigned char SYNC:1;
1524 unsigned char TXEN:1;
1525 unsigned char TX9:1;
1526 unsigned char CSRC:1;
1529 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1531 #ifndef NO_BIT_DEFINES
1532 #define TX9D TXSTA_bits.TX9D
1533 #define TRMT TXSTA_bits.TRMT
1534 #define BRGH TXSTA_bits.BRGH
1535 #define SENB TXSTA_bits.SENB
1536 #define SYNC TXSTA_bits.SYNC
1537 #define TXEN TXSTA_bits.TXEN
1538 #define TX9 TXSTA_bits.TX9
1539 #define CSRC TXSTA_bits.CSRC
1540 #endif /* NO_BIT_DEFINES */
1542 // ----- VRCON bits --------------------
1545 unsigned char VR0:1;
1546 unsigned char VR1:1;
1547 unsigned char VR2:1;
1548 unsigned char VR3:1;
1549 unsigned char VP6EN:1;
1550 unsigned char VRR:1;
1551 unsigned char C2VREN:1;
1552 unsigned char C1VREN:1;
1555 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1557 #ifndef NO_BIT_DEFINES
1558 #define VR0 VRCON_bits.VR0
1559 #define VR1 VRCON_bits.VR1
1560 #define VR2 VRCON_bits.VR2
1561 #define VR3 VRCON_bits.VR3
1562 #define VP6EN VRCON_bits.VP6EN
1563 #define VRR VRCON_bits.VRR
1564 #define C2VREN VRCON_bits.C2VREN
1565 #define C1VREN VRCON_bits.C1VREN
1566 #endif /* NO_BIT_DEFINES */
1568 // ----- WDTCON bits --------------------
1571 unsigned char SWDTEN:1;
1572 unsigned char WDTPS0:1;
1573 unsigned char WDTPS1:1;
1574 unsigned char WDTPS2:1;
1575 unsigned char WDTPS3:1;
1581 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1583 #ifndef NO_BIT_DEFINES
1584 #define SWDTEN WDTCON_bits.SWDTEN
1585 #define WDTPS0 WDTCON_bits.WDTPS0
1586 #define WDTPS1 WDTCON_bits.WDTPS1
1587 #define WDTPS2 WDTCON_bits.WDTPS2
1588 #define WDTPS3 WDTCON_bits.WDTPS3
1589 #endif /* NO_BIT_DEFINES */
1591 // ----- WPUA bits --------------------
1594 unsigned char WPUA0:1;
1595 unsigned char WPUA1:1;
1596 unsigned char WPUA2:1;
1598 unsigned char WPUA4:1;
1599 unsigned char WPUA5:1;
1604 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1606 #ifndef NO_BIT_DEFINES
1607 #define WPUA0 WPUA_bits.WPUA0
1608 #define WPUA1 WPUA_bits.WPUA1
1609 #define WPUA2 WPUA_bits.WPUA2
1610 #define WPUA4 WPUA_bits.WPUA4
1611 #define WPUA5 WPUA_bits.WPUA5
1612 #endif /* NO_BIT_DEFINES */
1614 // ----- WPUB bits --------------------
1621 unsigned char WPUB4:1;
1622 unsigned char WPUB5:1;
1623 unsigned char WPUB6:1;
1624 unsigned char WPUB7:1;
1627 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1629 #ifndef NO_BIT_DEFINES
1630 #define WPUB4 WPUB_bits.WPUB4
1631 #define WPUB5 WPUB_bits.WPUB5
1632 #define WPUB6 WPUB_bits.WPUB6
1633 #define WPUB7 WPUB_bits.WPUB7
1634 #endif /* NO_BIT_DEFINES */