2 // Register Declarations for Microchip 16F690 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define PWM1CON_ADDR 0x001C
54 #define ECCPAS_ADDR 0x001D
55 #define ADRESH_ADDR 0x001E
56 #define ADCON0_ADDR 0x001F
57 #define OPTION_REG_ADDR 0x0081
58 #define TRISA_ADDR 0x0085
59 #define TRISB_ADDR 0x0086
60 #define TRISC_ADDR 0x0087
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define MSK_ADDR 0x0093
69 #define SSPMSK_ADDR 0x0093
70 #define SSPSTAT_ADDR 0x0094
71 #define WPU_ADDR 0x0095
72 #define WPUA_ADDR 0x0095
73 #define IOC_ADDR 0x0096
74 #define IOCA_ADDR 0x0096
75 #define WDTCON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define SPBRGH_ADDR 0x009A
79 #define BAUDCTL_ADDR 0x009B
80 #define ADRESL_ADDR 0x009E
81 #define ADCON1_ADDR 0x009F
82 #define EEDATA_ADDR 0x010C
83 #define EEADR_ADDR 0x010D
84 #define EEDATH_ADDR 0x010E
85 #define EEADRH_ADDR 0x010F
86 #define WPUB_ADDR 0x0115
87 #define IOCB_ADDR 0x0116
88 #define VRCON_ADDR 0x0118
89 #define CM1CON0_ADDR 0x0119
90 #define CM2CON0_ADDR 0x011A
91 #define CM2CON1_ADDR 0x011B
92 #define ANSEL_ADDR 0x011E
93 #define ANSELH_ADDR 0x011F
94 #define EECON1_ADDR 0x018C
95 #define EECON2_ADDR 0x018D
96 #define PSTRCON_ADDR 0x019D
97 #define SRCON_ADDR 0x019E
100 // Memory organization.
103 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
104 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
105 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
106 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
107 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
108 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
109 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
110 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
111 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
112 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
113 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
114 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
115 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
116 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
117 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
118 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
119 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
120 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
121 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
122 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
123 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
124 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
125 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
126 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
127 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
128 #pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON
129 #pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS
130 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
131 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
132 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
133 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
134 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
135 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
136 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
137 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
138 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
139 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
140 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
141 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
142 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
143 #pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK
144 #pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK
145 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
146 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
147 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
148 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
149 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
150 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
151 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
152 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
153 #pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH
154 #pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL
155 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
156 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
157 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
158 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
159 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
160 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
161 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
162 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
163 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
164 #pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
165 #pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
166 #pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
167 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
168 #pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH
169 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
170 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
171 #pragma memmap PSTRCON_ADDR PSTRCON_ADDR SFR 0x000 // PSTRCON
172 #pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON
176 // P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
179 // This header file defines configurations, registers, and other useful bits of
180 // information for the PIC16F690 microcontroller. These names are taken to match
181 // the data sheets as closely as possible.
183 // Note that the processor must be selected before this file is
184 // included. The processor may be selected the following ways:
186 // 1. Command line switch:
187 // C:\ MPASM MYFILE.ASM /PIC16F690
188 // 2. LIST directive in the source file
190 // 3. Processor Type entry in the MPASM full-screen interface
192 //==========================================================================
196 //==========================================================================
197 //1.00 10/12/04 Original
198 //==========================================================================
202 //==========================================================================
205 // MESSG "Processor-header file mismatch. Verify selected processor."
208 //==========================================================================
210 // Register Definitions
212 //==========================================================================
217 //----- Register Files------------------------------------------------------
219 extern __data __at (INDF_ADDR) volatile char INDF;
220 extern __sfr __at (TMR0_ADDR) TMR0;
221 extern __data __at (PCL_ADDR) volatile char PCL;
222 extern __sfr __at (STATUS_ADDR) STATUS;
223 extern __sfr __at (FSR_ADDR) FSR;
224 extern __sfr __at (PORTA_ADDR) PORTA;
225 extern __sfr __at (PORTB_ADDR) PORTB;
226 extern __sfr __at (PORTC_ADDR) PORTC;
228 extern __sfr __at (PCLATH_ADDR) PCLATH;
229 extern __sfr __at (INTCON_ADDR) INTCON;
230 extern __sfr __at (PIR1_ADDR) PIR1;
231 extern __sfr __at (PIR2_ADDR) PIR2;
232 extern __sfr __at (TMR1L_ADDR) TMR1L;
233 extern __sfr __at (TMR1H_ADDR) TMR1H;
234 extern __sfr __at (T1CON_ADDR) T1CON;
235 extern __sfr __at (TMR2_ADDR) TMR2;
236 extern __sfr __at (T2CON_ADDR) T2CON;
237 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
238 extern __sfr __at (SSPCON_ADDR) SSPCON;
239 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
240 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
241 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
242 extern __sfr __at (RCSTA_ADDR) RCSTA;
243 extern __sfr __at (TXREG_ADDR) TXREG;
244 extern __sfr __at (RCREG_ADDR) RCREG;
246 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
247 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
248 extern __sfr __at (ADRESH_ADDR) ADRESH;
249 extern __sfr __at (ADCON0_ADDR) ADCON0;
252 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
254 extern __sfr __at (TRISA_ADDR) TRISA;
255 extern __sfr __at (TRISB_ADDR) TRISB;
256 extern __sfr __at (TRISC_ADDR) TRISC;
258 extern __sfr __at (PIE1_ADDR) PIE1;
259 extern __sfr __at (PIE2_ADDR) PIE2;
260 extern __sfr __at (PCON_ADDR) PCON;
261 extern __sfr __at (OSCCON_ADDR) OSCCON;
262 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
264 extern __sfr __at (PR2_ADDR) PR2;
265 extern __sfr __at (SSPADD_ADDR) SSPADD;
266 extern __sfr __at (MSK_ADDR) MSK;
267 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
268 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
269 extern __sfr __at (WPU_ADDR) WPU;
270 extern __sfr __at (WPUA_ADDR) WPUA;
271 extern __sfr __at (IOC_ADDR) IOC;
272 extern __sfr __at (IOCA_ADDR) IOCA;
273 extern __sfr __at (WDTCON_ADDR) WDTCON;
274 extern __sfr __at (TXSTA_ADDR) TXSTA;
275 extern __sfr __at (SPBRG_ADDR) SPBRG;
276 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
277 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
280 extern __sfr __at (ADRESL_ADDR) ADRESL;
281 extern __sfr __at (ADCON1_ADDR) ADCON1;
285 extern __sfr __at (EEDATA_ADDR) EEDATA;
286 extern __sfr __at (EEADR_ADDR) EEADR;
287 extern __sfr __at (EEDATH_ADDR) EEDATH;
288 extern __sfr __at (EEADRH_ADDR) EEADRH;
291 extern __sfr __at (WPUB_ADDR) WPUB;
292 extern __sfr __at (IOCB_ADDR) IOCB;
294 extern __sfr __at (VRCON_ADDR) VRCON;
295 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
296 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
297 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
299 extern __sfr __at (ANSEL_ADDR) ANSEL;
300 extern __sfr __at (ANSELH_ADDR) ANSELH;
302 extern __sfr __at (EECON1_ADDR) EECON1;
303 extern __sfr __at (EECON2_ADDR) EECON2;
306 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
307 extern __sfr __at (SRCON_ADDR) SRCON;
311 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
312 //----- STATUS Bits --------------------------------------------------------
315 //----- INTCON Bits --------------------------------------------------------
318 //----- PIR1 Bits ----------------------------------------------------------
321 //----- PIR2 Bits ----------------------------------------------------------
324 //----- T1CON Bits ---------------------------------------------------------
327 //----- T2CON Bits ---------------------------------------------------------
330 //----- SSPCON Bits -------------------------------------------------------
333 //----- CCP1CON Bits -------------------------------------------------------
336 //----- RCSTA Bits ---------------------------------------------------------
339 //----- PWM1CON Bits -------------------------------------------------------
342 //----- ECCPAS Bits --------------------------------------------------------
345 //----- ADCON0 Bits --------------------------------------------------------
348 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
349 //----- OPTION Bits --------------------------------------------------------
352 //----- TRISA Bits --------------------------------------------------------
355 //----- TRISB Bits --------------------------------------------------------
358 //----- TRISC Bits --------------------------------------------------------
361 //----- PIE1 Bits ----------------------------------------------------------
364 //----- PIE2 Bits ----------------------------------------------------------
367 //----- PCON Bits ----------------------------------------------------------
370 //----- OSCCON Bits --------------------------------------------------------
373 //----- OSCTUNE Bits -------------------------------------------------------
376 //----- SSPSTAT Bits --------------------------------------------------------
379 //----- WPUA --------------------------------------------------------------
383 //----- IOC --------------------------------------------------------------
386 //----- IOCA --------------------------------------------------------------
389 //----- WDTCON Bits --------------------------------------------------------
392 //----- TXSTA Bits -------------------------------------------------------
395 //----- SPBRG Bits -------------------------------------------------------
398 //----- SPBRGH Bits -------------------------------------------------------
401 //----- BAUDCTL Bits -------------------------------------------------------
406 //----- ADCON1 -------------------------------------------------------------
409 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
410 //----- WPUB Bits ----------------------------------------------------------
413 //----- IOCB --------------------------------------------------------------
416 //----- VRCON Bits ---------------------------------------------------------
419 //----- CM1CON0 Bits -------------------------------------------------------
423 //----- CM2CON0 Bits -------------------------------------------------------
427 //----- CM2CON1 Bits -------------------------------------------------------
430 //----- ANSEL --------------------------------------------------------------
433 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
434 //----- EECON1 -------------------------------------------------------------
437 //----- PSTRCON -------------------------------------------------------------
440 //----- SRCON ---------------------------------------------------------------
443 //==========================================================================
447 //==========================================================================
450 // __BADRAM H'08'-H'09', H'1B'
451 // __BADRAM H'88'-H'89', H'91', H'9C'-H'9D'
452 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
453 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
455 //==========================================================================
457 // Configuration Bits
459 //==========================================================================
461 #define _FCMEN_ON 0x3FFF
462 #define _FCMEN_OFF 0x37FF
463 #define _IESO_ON 0x3FFF
464 #define _IESO_OFF 0x3BFF
465 #define _BOD_ON 0x3FFF
466 #define _BOD_NSLEEP 0x3EFF
467 #define _BOD_SBODEN 0x3DFF
468 #define _BOD_OFF 0x3CFF
469 #define _CPD_ON 0x3F7F
470 #define _CPD_OFF 0x3FFF
471 #define _CP_ON 0x3FBF
472 #define _CP_OFF 0x3FFF
473 #define _MCLRE_ON 0x3FFF
474 #define _MCLRE_OFF 0x3FDF
475 #define _PWRTE_OFF 0x3FFF
476 #define _PWRTE_ON 0x3FEF
477 #define _WDT_ON 0x3FFF
478 #define _WDT_OFF 0x3FF7
479 #define _LP_OSC 0x3FF8
480 #define _XT_OSC 0x3FF9
481 #define _HS_OSC 0x3FFA
482 #define _EC_OSC 0x3FFB
483 #define _INTRC_OSC_NOCLKOUT 0x3FFC
484 #define _INTRC_OSC_CLKOUT 0x3FFD
485 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
486 #define _EXTRC_OSC_CLKOUT 0x3FFF
487 #define _INTOSCIO 0x3FFC
488 #define _INTOSC 0x3FFD
489 #define _EXTRCIO 0x3FFE
490 #define _EXTRC 0x3FFF
494 // ----- ADCON0 bits --------------------
497 unsigned char ADON:1;
499 unsigned char CHS0:1;
500 unsigned char CHS1:1;
501 unsigned char CHS2:1;
502 unsigned char CHS3:1;
503 unsigned char VCFG:1;
504 unsigned char ADFM:1;
508 unsigned char NOT_DONE:1;
518 unsigned char GO_DONE:1;
527 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
529 #define ADON ADCON0_bits.ADON
530 #define GO ADCON0_bits.GO
531 #define NOT_DONE ADCON0_bits.NOT_DONE
532 #define GO_DONE ADCON0_bits.GO_DONE
533 #define CHS0 ADCON0_bits.CHS0
534 #define CHS1 ADCON0_bits.CHS1
535 #define CHS2 ADCON0_bits.CHS2
536 #define CHS3 ADCON0_bits.CHS3
537 #define VCFG ADCON0_bits.VCFG
538 #define ADFM ADCON0_bits.ADFM
540 // ----- BAUDCTL bits --------------------
543 unsigned char ABDEN:1;
546 unsigned char BRG16:1;
547 unsigned char CKTXP:1;
548 unsigned char ADCS1:1;
549 unsigned char RCIDL:1;
550 unsigned char ABDOVF:1;
557 unsigned char ADCS0:1;
559 unsigned char ADCS2:1;
563 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
565 #define ABDEN BAUDCTL_bits.ABDEN
566 #define WUE BAUDCTL_bits.WUE
567 #define BRG16 BAUDCTL_bits.BRG16
568 #define CKTXP BAUDCTL_bits.CKTXP
569 #define ADCS0 BAUDCTL_bits.ADCS0
570 #define ADCS1 BAUDCTL_bits.ADCS1
571 #define RCIDL BAUDCTL_bits.RCIDL
572 #define ADCS2 BAUDCTL_bits.ADCS2
573 #define ABDOVF BAUDCTL_bits.ABDOVF
575 // ----- CCP1CON bits --------------------
578 unsigned char CCP1M0:1;
579 unsigned char CCP1M1:1;
580 unsigned char CCP1M2:1;
581 unsigned char CCP1M3:1;
582 unsigned char DC1B0:1;
583 unsigned char DC1B1:1;
584 unsigned char P1M0:1;
585 unsigned char P1M1:1;
588 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
590 #define CCP1M0 CCP1CON_bits.CCP1M0
591 #define CCP1M1 CCP1CON_bits.CCP1M1
592 #define CCP1M2 CCP1CON_bits.CCP1M2
593 #define CCP1M3 CCP1CON_bits.CCP1M3
594 #define DC1B0 CCP1CON_bits.DC1B0
595 #define DC1B1 CCP1CON_bits.DC1B1
596 #define P1M0 CCP1CON_bits.P1M0
597 #define P1M1 CCP1CON_bits.P1M1
599 // ----- CM1CON0 bits --------------------
602 unsigned char C1CH0:1;
603 unsigned char C1CH1:1;
606 unsigned char C1POL:1;
607 unsigned char C1OE:1;
608 unsigned char C1OUT:1;
609 unsigned char C1ON:1;
612 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
614 #define C1CH0 CM1CON0_bits.C1CH0
615 #define C1CH1 CM1CON0_bits.C1CH1
616 #define C1R CM1CON0_bits.C1R
617 #define C1POL CM1CON0_bits.C1POL
618 #define C1OE CM1CON0_bits.C1OE
619 #define C1OUT CM1CON0_bits.C1OUT
620 #define C1ON CM1CON0_bits.C1ON
622 // ----- CM2CON0 bits --------------------
625 unsigned char C2CH0:1;
626 unsigned char C2CH1:1;
629 unsigned char C2POL:1;
630 unsigned char C2OE:1;
631 unsigned char C2OUT:1;
632 unsigned char C2ON:1;
635 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
637 #define C2CH0 CM2CON0_bits.C2CH0
638 #define C2CH1 CM2CON0_bits.C2CH1
639 #define C2R CM2CON0_bits.C2R
640 #define C2POL CM2CON0_bits.C2POL
641 #define C2OE CM2CON0_bits.C2OE
642 #define C2OUT CM2CON0_bits.C2OUT
643 #define C2ON CM2CON0_bits.C2ON
645 // ----- CM2CON1 bits --------------------
648 unsigned char C2SYNC:1;
649 unsigned char T1GSS:1;
650 unsigned char ANS2:1;
651 unsigned char ANS3:1;
652 unsigned char ANS4:1;
653 unsigned char ANS5:1;
654 unsigned char MC2OUT:1;
655 unsigned char MC1OUT:1;
658 unsigned char ANS0:1;
659 unsigned char ANS1:1;
660 unsigned char WREN:1;
661 unsigned char WRERR:1;
662 unsigned char STRSYNC:1;
663 unsigned char C1SEN:1;
664 unsigned char ANS6:1;
665 unsigned char ANS7:1;
670 unsigned char STRC:1;
671 unsigned char STRD:1;
672 unsigned char C2REN:1;
675 unsigned char EEPGD:1;
678 unsigned char STRA:1;
679 unsigned char STRB:1;
680 unsigned char PULSR:1;
681 unsigned char PULSS:1;
688 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
690 #define C2SYNC CM2CON1_bits.C2SYNC
691 #define ANS0 CM2CON1_bits.ANS0
692 #define RD CM2CON1_bits.RD
693 #define STRA CM2CON1_bits.STRA
694 #define T1GSS CM2CON1_bits.T1GSS
695 #define ANS1 CM2CON1_bits.ANS1
696 #define WR CM2CON1_bits.WR
697 #define STRB CM2CON1_bits.STRB
698 #define ANS2 CM2CON1_bits.ANS2
699 #define WREN CM2CON1_bits.WREN
700 #define STRC CM2CON1_bits.STRC
701 #define PULSR CM2CON1_bits.PULSR
702 #define ANS3 CM2CON1_bits.ANS3
703 #define WRERR CM2CON1_bits.WRERR
704 #define STRD CM2CON1_bits.STRD
705 #define PULSS CM2CON1_bits.PULSS
706 #define ANS4 CM2CON1_bits.ANS4
707 #define STRSYNC CM2CON1_bits.STRSYNC
708 #define C2REN CM2CON1_bits.C2REN
709 #define ANS5 CM2CON1_bits.ANS5
710 #define C1SEN CM2CON1_bits.C1SEN
711 #define MC2OUT CM2CON1_bits.MC2OUT
712 #define ANS6 CM2CON1_bits.ANS6
713 #define SR0 CM2CON1_bits.SR0
714 #define MC1OUT CM2CON1_bits.MC1OUT
715 #define ANS7 CM2CON1_bits.ANS7
716 #define EEPGD CM2CON1_bits.EEPGD
717 #define SR1 CM2CON1_bits.SR1
719 // ----- ECCPAS bits --------------------
722 unsigned char PSSBD0:1;
723 unsigned char PSSBD1:1;
724 unsigned char PSSAC0:1;
725 unsigned char PSSAC1:1;
726 unsigned char ECCPAS0:1;
727 unsigned char ECCPAS1:1;
728 unsigned char ECCPAS2:1;
729 unsigned char ECCPASE:1;
732 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
734 #define PSSBD0 ECCPAS_bits.PSSBD0
735 #define PSSBD1 ECCPAS_bits.PSSBD1
736 #define PSSAC0 ECCPAS_bits.PSSAC0
737 #define PSSAC1 ECCPAS_bits.PSSAC1
738 #define ECCPAS0 ECCPAS_bits.ECCPAS0
739 #define ECCPAS1 ECCPAS_bits.ECCPAS1
740 #define ECCPAS2 ECCPAS_bits.ECCPAS2
741 #define ECCPASE ECCPAS_bits.ECCPASE
743 // ----- INTCON bits --------------------
746 unsigned char RABIF:1;
747 unsigned char INTF:1;
748 unsigned char T0IF:1;
749 unsigned char RABIE:1;
750 unsigned char INTE:1;
751 unsigned char T0IE:1;
752 unsigned char PEIE:1;
756 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
758 #define RABIF INTCON_bits.RABIF
759 #define INTF INTCON_bits.INTF
760 #define T0IF INTCON_bits.T0IF
761 #define RABIE INTCON_bits.RABIE
762 #define INTE INTCON_bits.INTE
763 #define T0IE INTCON_bits.T0IE
764 #define PEIE INTCON_bits.PEIE
765 #define GIE INTCON_bits.GIE
767 // ----- OPTION_REG bits --------------------
774 unsigned char T0SE:1;
775 unsigned char T0CS:1;
776 unsigned char INTEDG:1;
777 unsigned char NOT_RABPU:1;
779 } __OPTION_REG_bits_t;
780 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
782 #define PS0 OPTION_REG_bits.PS0
783 #define PS1 OPTION_REG_bits.PS1
784 #define PS2 OPTION_REG_bits.PS2
785 #define PSA OPTION_REG_bits.PSA
786 #define T0SE OPTION_REG_bits.T0SE
787 #define T0CS OPTION_REG_bits.T0CS
788 #define INTEDG OPTION_REG_bits.INTEDG
789 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
791 // ----- OSCCON bits --------------------
797 unsigned char OSTS:1;
798 unsigned char IRCF0:1;
799 unsigned char IRCF1:1;
800 unsigned char IRCF2:1;
804 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
806 #define SCS OSCCON_bits.SCS
807 #define LTS OSCCON_bits.LTS
808 #define HTS OSCCON_bits.HTS
809 #define OSTS OSCCON_bits.OSTS
810 #define IRCF0 OSCCON_bits.IRCF0
811 #define IRCF1 OSCCON_bits.IRCF1
812 #define IRCF2 OSCCON_bits.IRCF2
814 // ----- OSCTUNE bits --------------------
817 unsigned char TUN0:1;
818 unsigned char TUN1:1;
819 unsigned char TUN2:1;
820 unsigned char TUN3:1;
821 unsigned char TUN4:1;
827 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
829 #define TUN0 OSCTUNE_bits.TUN0
830 #define TUN1 OSCTUNE_bits.TUN1
831 #define TUN2 OSCTUNE_bits.TUN2
832 #define TUN3 OSCTUNE_bits.TUN3
833 #define TUN4 OSCTUNE_bits.TUN4
835 // ----- PCON bits --------------------
838 unsigned char NOT_BOD:1;
839 unsigned char NOT_POR:1;
842 unsigned char SBODEN:1;
843 unsigned char ULPWUE:1;
848 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
850 #define NOT_BOD PCON_bits.NOT_BOD
851 #define NOT_POR PCON_bits.NOT_POR
852 #define SBODEN PCON_bits.SBODEN
853 #define ULPWUE PCON_bits.ULPWUE
855 // ----- PIE1 bits --------------------
858 unsigned char T1IE:1;
859 unsigned char T2IE:1;
860 unsigned char CCPIE:1;
861 unsigned char SSPIE:1;
862 unsigned char TXIE:1;
863 unsigned char RCIE:1;
864 unsigned char ADIE:1;
868 unsigned char TMR1IE:1;
869 unsigned char TMR2IE:1;
878 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
880 #define T1IE PIE1_bits.T1IE
881 #define TMR1IE PIE1_bits.TMR1IE
882 #define T2IE PIE1_bits.T2IE
883 #define TMR2IE PIE1_bits.TMR2IE
884 #define CCPIE PIE1_bits.CCPIE
885 #define SSPIE PIE1_bits.SSPIE
886 #define TXIE PIE1_bits.TXIE
887 #define RCIE PIE1_bits.RCIE
888 #define ADIE PIE1_bits.ADIE
890 // ----- PIE2 bits --------------------
897 unsigned char EEIE:1;
898 unsigned char C1IE:1;
899 unsigned char C2IE:1;
900 unsigned char OSFIE:1;
903 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
905 #define EEIE PIE2_bits.EEIE
906 #define C1IE PIE2_bits.C1IE
907 #define C2IE PIE2_bits.C2IE
908 #define OSFIE PIE2_bits.OSFIE
910 // ----- PIR1 bits --------------------
913 unsigned char T1IF:1;
914 unsigned char T2IF:1;
915 unsigned char CCP1IF:1;
916 unsigned char SSPIF:1;
917 unsigned char TXIF:1;
918 unsigned char RCIF:1;
919 unsigned char ADIF:1;
923 unsigned char TMR1IF:1;
924 unsigned char TMR2IF:1;
933 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
935 #define T1IF PIR1_bits.T1IF
936 #define TMR1IF PIR1_bits.TMR1IF
937 #define T2IF PIR1_bits.T2IF
938 #define TMR2IF PIR1_bits.TMR2IF
939 #define CCP1IF PIR1_bits.CCP1IF
940 #define SSPIF PIR1_bits.SSPIF
941 #define TXIF PIR1_bits.TXIF
942 #define RCIF PIR1_bits.RCIF
943 #define ADIF PIR1_bits.ADIF
945 // ----- PIR2 bits --------------------
952 unsigned char EEIF:1;
953 unsigned char C1IF:1;
954 unsigned char C2IF:1;
955 unsigned char OSFIF:1;
958 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
960 #define EEIF PIR2_bits.EEIF
961 #define C1IF PIR2_bits.C1IF
962 #define C2IF PIR2_bits.C2IF
963 #define OSFIF PIR2_bits.OSFIF
965 // ----- PWM1CON bits --------------------
968 unsigned char PDC0:1;
969 unsigned char PDC1:1;
970 unsigned char PDC2:1;
971 unsigned char PDC3:1;
972 unsigned char PDC4:1;
973 unsigned char PDC5:1;
974 unsigned char PDC6:1;
975 unsigned char PRSEN:1;
978 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
980 #define PDC0 PWM1CON_bits.PDC0
981 #define PDC1 PWM1CON_bits.PDC1
982 #define PDC2 PWM1CON_bits.PDC2
983 #define PDC3 PWM1CON_bits.PDC3
984 #define PDC4 PWM1CON_bits.PDC4
985 #define PDC5 PWM1CON_bits.PDC5
986 #define PDC6 PWM1CON_bits.PDC6
987 #define PRSEN PWM1CON_bits.PRSEN
989 // ----- RCSTA bits --------------------
992 unsigned char RX9D:1;
993 unsigned char OERR:1;
994 unsigned char FERR:1;
995 unsigned char ADDEN:1;
996 unsigned char CREN:1;
997 unsigned char SREN:1;
999 unsigned char SPEN:1;
1002 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
1004 #define RX9D RCSTA_bits.RX9D
1005 #define OERR RCSTA_bits.OERR
1006 #define FERR RCSTA_bits.FERR
1007 #define ADDEN RCSTA_bits.ADDEN
1008 #define CREN RCSTA_bits.CREN
1009 #define SREN RCSTA_bits.SREN
1010 #define RX9 RCSTA_bits.RX9
1011 #define SPEN RCSTA_bits.SPEN
1013 // ----- SPBRG bits --------------------
1016 unsigned char BRG0:1;
1017 unsigned char BRG1:1;
1018 unsigned char BRG2:1;
1019 unsigned char BRG3:1;
1020 unsigned char BRG4:1;
1021 unsigned char BRG5:1;
1022 unsigned char BRG6:1;
1023 unsigned char BRG7:1;
1026 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1028 #define BRG0 SPBRG_bits.BRG0
1029 #define BRG1 SPBRG_bits.BRG1
1030 #define BRG2 SPBRG_bits.BRG2
1031 #define BRG3 SPBRG_bits.BRG3
1032 #define BRG4 SPBRG_bits.BRG4
1033 #define BRG5 SPBRG_bits.BRG5
1034 #define BRG6 SPBRG_bits.BRG6
1035 #define BRG7 SPBRG_bits.BRG7
1037 // ----- SPBRGH bits --------------------
1040 unsigned char BRG8:1;
1041 unsigned char BRG9:1;
1042 unsigned char BRG10:1;
1043 unsigned char BRG11:1;
1044 unsigned char BRG12:1;
1045 unsigned char BRG13:1;
1046 unsigned char BRG14:1;
1047 unsigned char BRG15:1;
1050 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1052 #define BRG8 SPBRGH_bits.BRG8
1053 #define BRG9 SPBRGH_bits.BRG9
1054 #define BRG10 SPBRGH_bits.BRG10
1055 #define BRG11 SPBRGH_bits.BRG11
1056 #define BRG12 SPBRGH_bits.BRG12
1057 #define BRG13 SPBRGH_bits.BRG13
1058 #define BRG14 SPBRGH_bits.BRG14
1059 #define BRG15 SPBRGH_bits.BRG15
1061 // ----- SSPCON bits --------------------
1064 unsigned char SSPM0:1;
1065 unsigned char SSPM1:1;
1066 unsigned char SSPM2:1;
1067 unsigned char SSPM3:1;
1068 unsigned char CKP:1;
1069 unsigned char SSPEN:1;
1070 unsigned char SSPOV:1;
1071 unsigned char WCOL:1;
1074 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1076 #define SSPM0 SSPCON_bits.SSPM0
1077 #define SSPM1 SSPCON_bits.SSPM1
1078 #define SSPM2 SSPCON_bits.SSPM2
1079 #define SSPM3 SSPCON_bits.SSPM3
1080 #define CKP SSPCON_bits.CKP
1081 #define SSPEN SSPCON_bits.SSPEN
1082 #define SSPOV SSPCON_bits.SSPOV
1083 #define WCOL SSPCON_bits.WCOL
1085 // ----- SSPSTAT bits --------------------
1090 unsigned char R_W_NOT:1;
1093 unsigned char D_A_NOT:1;
1094 unsigned char CKE:1;
1095 unsigned char SMP:1;
1098 unsigned char WPUA0:1;
1099 unsigned char WPUA1:1;
1100 unsigned char WPUA2:1;
1101 unsigned char IOC3:1;
1102 unsigned char WPUA4:1;
1103 unsigned char WPUA5:1;
1108 unsigned char IOC0:1;
1109 unsigned char IOC1:1;
1110 unsigned char IOC2:1;
1111 unsigned char IOCA3:1;
1112 unsigned char IOC4:1;
1113 unsigned char IOC5:1;
1118 unsigned char IOCA0:1;
1119 unsigned char IOCA1:1;
1120 unsigned char IOCA2:1;
1122 unsigned char IOCA4:1;
1123 unsigned char IOCA5:1;
1128 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1130 #define BF SSPSTAT_bits.BF
1131 #define WPUA0 SSPSTAT_bits.WPUA0
1132 #define IOC0 SSPSTAT_bits.IOC0
1133 #define IOCA0 SSPSTAT_bits.IOCA0
1134 #define UA SSPSTAT_bits.UA
1135 #define WPUA1 SSPSTAT_bits.WPUA1
1136 #define IOC1 SSPSTAT_bits.IOC1
1137 #define IOCA1 SSPSTAT_bits.IOCA1
1138 #define R_W_NOT SSPSTAT_bits.R_W_NOT
1139 #define WPUA2 SSPSTAT_bits.WPUA2
1140 #define IOC2 SSPSTAT_bits.IOC2
1141 #define IOCA2 SSPSTAT_bits.IOCA2
1142 #define S SSPSTAT_bits.S
1143 #define IOC3 SSPSTAT_bits.IOC3
1144 #define IOCA3 SSPSTAT_bits.IOCA3
1145 #define P SSPSTAT_bits.P
1146 #define WPUA4 SSPSTAT_bits.WPUA4
1147 #define IOC4 SSPSTAT_bits.IOC4
1148 #define IOCA4 SSPSTAT_bits.IOCA4
1149 #define D_A_NOT SSPSTAT_bits.D_A_NOT
1150 #define WPUA5 SSPSTAT_bits.WPUA5
1151 #define IOC5 SSPSTAT_bits.IOC5
1152 #define IOCA5 SSPSTAT_bits.IOCA5
1153 #define CKE SSPSTAT_bits.CKE
1154 #define SMP SSPSTAT_bits.SMP
1156 // ----- STATUS bits --------------------
1162 unsigned char NOT_PD:1;
1163 unsigned char NOT_TO:1;
1164 unsigned char RP0:1;
1165 unsigned char RP1:1;
1166 unsigned char IRP:1;
1169 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1171 #define C STATUS_bits.C
1172 #define DC STATUS_bits.DC
1173 #define Z STATUS_bits.Z
1174 #define NOT_PD STATUS_bits.NOT_PD
1175 #define NOT_TO STATUS_bits.NOT_TO
1176 #define RP0 STATUS_bits.RP0
1177 #define RP1 STATUS_bits.RP1
1178 #define IRP STATUS_bits.IRP
1180 // ----- T1CON bits --------------------
1183 unsigned char TMR1ON:1;
1184 unsigned char TMR1CS:1;
1185 unsigned char NOT_T1SYNC:1;
1186 unsigned char T1OSCEN:1;
1187 unsigned char T1CKPS0:1;
1188 unsigned char T1CKPS1:1;
1189 unsigned char TMR1GE:1;
1190 unsigned char T1GINV:1;
1193 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1195 #define TMR1ON T1CON_bits.TMR1ON
1196 #define TMR1CS T1CON_bits.TMR1CS
1197 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1198 #define T1OSCEN T1CON_bits.T1OSCEN
1199 #define T1CKPS0 T1CON_bits.T1CKPS0
1200 #define T1CKPS1 T1CON_bits.T1CKPS1
1201 #define TMR1GE T1CON_bits.TMR1GE
1202 #define T1GINV T1CON_bits.T1GINV
1204 // ----- T2CON bits --------------------
1207 unsigned char T2CKPS0:1;
1208 unsigned char T2CKPS1:1;
1209 unsigned char TMR2ON:1;
1210 unsigned char TOUTPS0:1;
1211 unsigned char TOUTPS1:1;
1212 unsigned char TOUTPS2:1;
1213 unsigned char TOUTPS3:1;
1217 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1219 #define T2CKPS0 T2CON_bits.T2CKPS0
1220 #define T2CKPS1 T2CON_bits.T2CKPS1
1221 #define TMR2ON T2CON_bits.TMR2ON
1222 #define TOUTPS0 T2CON_bits.TOUTPS0
1223 #define TOUTPS1 T2CON_bits.TOUTPS1
1224 #define TOUTPS2 T2CON_bits.TOUTPS2
1225 #define TOUTPS3 T2CON_bits.TOUTPS3
1227 // ----- TRISA bits --------------------
1230 unsigned char TRISA0:1;
1231 unsigned char TRISA1:1;
1232 unsigned char TRISA2:1;
1233 unsigned char TRISA3:1;
1234 unsigned char TRISA4:1;
1235 unsigned char TRISA5:1;
1240 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1242 #define TRISA0 TRISA_bits.TRISA0
1243 #define TRISA1 TRISA_bits.TRISA1
1244 #define TRISA2 TRISA_bits.TRISA2
1245 #define TRISA3 TRISA_bits.TRISA3
1246 #define TRISA4 TRISA_bits.TRISA4
1247 #define TRISA5 TRISA_bits.TRISA5
1249 // ----- TRISB bits --------------------
1256 unsigned char TRISB4:1;
1257 unsigned char TRISB5:1;
1258 unsigned char TRISB6:1;
1259 unsigned char TRISB7:1;
1262 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1264 #define TRISB4 TRISB_bits.TRISB4
1265 #define TRISB5 TRISB_bits.TRISB5
1266 #define TRISB6 TRISB_bits.TRISB6
1267 #define TRISB7 TRISB_bits.TRISB7
1269 // ----- TRISC bits --------------------
1272 unsigned char TRISC0:1;
1273 unsigned char TRISC1:1;
1274 unsigned char TRISC2:1;
1275 unsigned char TRISC3:1;
1276 unsigned char TRISC4:1;
1277 unsigned char TRISC5:1;
1278 unsigned char TRISC6:1;
1279 unsigned char TRISC7:1;
1282 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1284 #define TRISC0 TRISC_bits.TRISC0
1285 #define TRISC1 TRISC_bits.TRISC1
1286 #define TRISC2 TRISC_bits.TRISC2
1287 #define TRISC3 TRISC_bits.TRISC3
1288 #define TRISC4 TRISC_bits.TRISC4
1289 #define TRISC5 TRISC_bits.TRISC5
1290 #define TRISC6 TRISC_bits.TRISC6
1291 #define TRISC7 TRISC_bits.TRISC7
1293 // ----- TXSTA bits --------------------
1296 unsigned char TX9D:1;
1297 unsigned char TRMT:1;
1298 unsigned char BRGH:1;
1299 unsigned char SENB:1;
1300 unsigned char SYNC:1;
1301 unsigned char TXEN:1;
1302 unsigned char TX9:1;
1303 unsigned char CSRC:1;
1306 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1308 #define TX9D TXSTA_bits.TX9D
1309 #define TRMT TXSTA_bits.TRMT
1310 #define BRGH TXSTA_bits.BRGH
1311 #define SENB TXSTA_bits.SENB
1312 #define SYNC TXSTA_bits.SYNC
1313 #define TXEN TXSTA_bits.TXEN
1314 #define TX9 TXSTA_bits.TX9
1315 #define CSRC TXSTA_bits.CSRC
1317 // ----- VRCON bits --------------------
1320 unsigned char VR0:1;
1321 unsigned char VR1:1;
1322 unsigned char VR2:1;
1323 unsigned char VR3:1;
1324 unsigned char VP6EN:1;
1325 unsigned char VRR:1;
1326 unsigned char C2VREN:1;
1327 unsigned char C1VREN:1;
1330 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1332 #define VR0 VRCON_bits.VR0
1333 #define VR1 VRCON_bits.VR1
1334 #define VR2 VRCON_bits.VR2
1335 #define VR3 VRCON_bits.VR3
1336 #define VP6EN VRCON_bits.VP6EN
1337 #define VRR VRCON_bits.VRR
1338 #define C2VREN VRCON_bits.C2VREN
1339 #define C1VREN VRCON_bits.C1VREN
1341 // ----- WDTCON bits --------------------
1344 unsigned char SWDTEN:1;
1345 unsigned char WDTPS0:1;
1346 unsigned char WDTPS1:1;
1347 unsigned char WDTPS2:1;
1348 unsigned char WDTPS3:1;
1354 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1356 #define SWDTEN WDTCON_bits.SWDTEN
1357 #define WDTPS0 WDTCON_bits.WDTPS0
1358 #define WDTPS1 WDTCON_bits.WDTPS1
1359 #define WDTPS2 WDTCON_bits.WDTPS2
1360 #define WDTPS3 WDTCON_bits.WDTPS3
1362 // ----- WPUB bits --------------------
1369 unsigned char WPUB4:1;
1370 unsigned char WPUB5:1;
1371 unsigned char WPUB6:1;
1372 unsigned char WPUB7:1;
1379 unsigned char IOCB4:1;
1380 unsigned char IOCB5:1;
1381 unsigned char IOCB6:1;
1382 unsigned char IOCB7:1;
1385 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1387 #define WPUB4 WPUB_bits.WPUB4
1388 #define IOCB4 WPUB_bits.IOCB4
1389 #define WPUB5 WPUB_bits.WPUB5
1390 #define IOCB5 WPUB_bits.IOCB5
1391 #define WPUB6 WPUB_bits.WPUB6
1392 #define IOCB6 WPUB_bits.IOCB6
1393 #define WPUB7 WPUB_bits.WPUB7
1394 #define IOCB7 WPUB_bits.IOCB7