2 // Register Declarations for Microchip 16F690 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define PWM1CON_ADDR 0x001C
54 #define ECCPAS_ADDR 0x001D
55 #define ADRESH_ADDR 0x001E
56 #define ADCON0_ADDR 0x001F
57 #define OPTION_REG_ADDR 0x0081
58 #define TRISA_ADDR 0x0085
59 #define TRISB_ADDR 0x0086
60 #define TRISC_ADDR 0x0087
61 #define PIE1_ADDR 0x008C
62 #define PIE2_ADDR 0x008D
63 #define PCON_ADDR 0x008E
64 #define OSCCON_ADDR 0x008F
65 #define OSCTUNE_ADDR 0x0090
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define MSK_ADDR 0x0093
69 #define SSPMSK_ADDR 0x0093
70 #define SSPSTAT_ADDR 0x0094
71 #define WPU_ADDR 0x0095
72 #define WPUA_ADDR 0x0095
73 #define IOC_ADDR 0x0096
74 #define IOCA_ADDR 0x0096
75 #define WDTCON_ADDR 0x0097
76 #define TXSTA_ADDR 0x0098
77 #define SPBRG_ADDR 0x0099
78 #define SPBRGH_ADDR 0x009A
79 #define BAUDCTL_ADDR 0x009B
80 #define ADRESL_ADDR 0x009E
81 #define ADCON1_ADDR 0x009F
82 #define EEDATA_ADDR 0x010C
83 #define EEADR_ADDR 0x010D
84 #define EEDATH_ADDR 0x010E
85 #define EEADRH_ADDR 0x010F
86 #define WPUB_ADDR 0x0115
87 #define IOCB_ADDR 0x0116
88 #define VRCON_ADDR 0x0118
89 #define CM1CON0_ADDR 0x0119
90 #define CM2CON0_ADDR 0x011A
91 #define CM2CON1_ADDR 0x011B
92 #define ANSEL_ADDR 0x011E
93 #define ANSELH_ADDR 0x011F
94 #define EECON1_ADDR 0x018C
95 #define EECON2_ADDR 0x018D
96 #define PSTRCON_ADDR 0x019D
97 #define SRCON_ADDR 0x019E
100 // Memory organization.
106 // P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
109 // This header file defines configurations, registers, and other useful bits of
110 // information for the PIC16F690 microcontroller. These names are taken to match
111 // the data sheets as closely as possible.
113 // Note that the processor must be selected before this file is
114 // included. The processor may be selected the following ways:
116 // 1. Command line switch:
117 // C:\ MPASM MYFILE.ASM /PIC16F690
118 // 2. LIST directive in the source file
120 // 3. Processor Type entry in the MPASM full-screen interface
122 //==========================================================================
126 //==========================================================================
127 //1.00 10/12/04 Original
128 //==========================================================================
132 //==========================================================================
135 // MESSG "Processor-header file mismatch. Verify selected processor."
138 //==========================================================================
140 // Register Definitions
142 //==========================================================================
147 //----- Register Files------------------------------------------------------
149 extern __data __at (INDF_ADDR) volatile char INDF;
150 extern __sfr __at (TMR0_ADDR) TMR0;
151 extern __data __at (PCL_ADDR) volatile char PCL;
152 extern __sfr __at (STATUS_ADDR) STATUS;
153 extern __sfr __at (FSR_ADDR) FSR;
154 extern __sfr __at (PORTA_ADDR) PORTA;
155 extern __sfr __at (PORTB_ADDR) PORTB;
156 extern __sfr __at (PORTC_ADDR) PORTC;
158 extern __sfr __at (PCLATH_ADDR) PCLATH;
159 extern __sfr __at (INTCON_ADDR) INTCON;
160 extern __sfr __at (PIR1_ADDR) PIR1;
161 extern __sfr __at (PIR2_ADDR) PIR2;
162 extern __sfr __at (TMR1L_ADDR) TMR1L;
163 extern __sfr __at (TMR1H_ADDR) TMR1H;
164 extern __sfr __at (T1CON_ADDR) T1CON;
165 extern __sfr __at (TMR2_ADDR) TMR2;
166 extern __sfr __at (T2CON_ADDR) T2CON;
167 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
168 extern __sfr __at (SSPCON_ADDR) SSPCON;
169 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
170 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
171 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
172 extern __sfr __at (RCSTA_ADDR) RCSTA;
173 extern __sfr __at (TXREG_ADDR) TXREG;
174 extern __sfr __at (RCREG_ADDR) RCREG;
176 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
177 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
178 extern __sfr __at (ADRESH_ADDR) ADRESH;
179 extern __sfr __at (ADCON0_ADDR) ADCON0;
182 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
184 extern __sfr __at (TRISA_ADDR) TRISA;
185 extern __sfr __at (TRISB_ADDR) TRISB;
186 extern __sfr __at (TRISC_ADDR) TRISC;
188 extern __sfr __at (PIE1_ADDR) PIE1;
189 extern __sfr __at (PIE2_ADDR) PIE2;
190 extern __sfr __at (PCON_ADDR) PCON;
191 extern __sfr __at (OSCCON_ADDR) OSCCON;
192 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
194 extern __sfr __at (PR2_ADDR) PR2;
195 extern __sfr __at (SSPADD_ADDR) SSPADD;
196 extern __sfr __at (MSK_ADDR) MSK;
197 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
198 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
199 extern __sfr __at (WPU_ADDR) WPU;
200 extern __sfr __at (WPUA_ADDR) WPUA;
201 extern __sfr __at (IOC_ADDR) IOC;
202 extern __sfr __at (IOCA_ADDR) IOCA;
203 extern __sfr __at (WDTCON_ADDR) WDTCON;
204 extern __sfr __at (TXSTA_ADDR) TXSTA;
205 extern __sfr __at (SPBRG_ADDR) SPBRG;
206 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
207 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
210 extern __sfr __at (ADRESL_ADDR) ADRESL;
211 extern __sfr __at (ADCON1_ADDR) ADCON1;
215 extern __sfr __at (EEDATA_ADDR) EEDATA;
216 extern __sfr __at (EEADR_ADDR) EEADR;
217 extern __sfr __at (EEDATH_ADDR) EEDATH;
218 extern __sfr __at (EEADRH_ADDR) EEADRH;
221 extern __sfr __at (WPUB_ADDR) WPUB;
222 extern __sfr __at (IOCB_ADDR) IOCB;
224 extern __sfr __at (VRCON_ADDR) VRCON;
225 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
226 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
227 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
229 extern __sfr __at (ANSEL_ADDR) ANSEL;
230 extern __sfr __at (ANSELH_ADDR) ANSELH;
232 extern __sfr __at (EECON1_ADDR) EECON1;
233 extern __sfr __at (EECON2_ADDR) EECON2;
236 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
237 extern __sfr __at (SRCON_ADDR) SRCON;
241 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
242 //----- STATUS Bits --------------------------------------------------------
245 //----- INTCON Bits --------------------------------------------------------
248 //----- PIR1 Bits ----------------------------------------------------------
251 //----- PIR2 Bits ----------------------------------------------------------
254 //----- T1CON Bits ---------------------------------------------------------
257 //----- T2CON Bits ---------------------------------------------------------
260 //----- SSPCON Bits -------------------------------------------------------
263 //----- CCP1CON Bits -------------------------------------------------------
266 //----- RCSTA Bits ---------------------------------------------------------
269 //----- PWM1CON Bits -------------------------------------------------------
272 //----- ECCPAS Bits --------------------------------------------------------
275 //----- ADCON0 Bits --------------------------------------------------------
278 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
279 //----- OPTION Bits --------------------------------------------------------
282 //----- TRISA Bits --------------------------------------------------------
285 //----- TRISB Bits --------------------------------------------------------
288 //----- TRISC Bits --------------------------------------------------------
291 //----- PIE1 Bits ----------------------------------------------------------
294 //----- PIE2 Bits ----------------------------------------------------------
297 //----- PCON Bits ----------------------------------------------------------
300 //----- OSCCON Bits --------------------------------------------------------
303 //----- OSCTUNE Bits -------------------------------------------------------
306 //----- SSPSTAT Bits --------------------------------------------------------
309 //----- WPUA --------------------------------------------------------------
313 //----- IOC --------------------------------------------------------------
316 //----- IOCA --------------------------------------------------------------
319 //----- WDTCON Bits --------------------------------------------------------
322 //----- TXSTA Bits -------------------------------------------------------
325 //----- SPBRG Bits -------------------------------------------------------
328 //----- SPBRGH Bits -------------------------------------------------------
331 //----- BAUDCTL Bits -------------------------------------------------------
336 //----- ADCON1 -------------------------------------------------------------
339 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
340 //----- WPUB Bits ----------------------------------------------------------
343 //----- IOCB --------------------------------------------------------------
346 //----- VRCON Bits ---------------------------------------------------------
349 //----- CM1CON0 Bits -------------------------------------------------------
353 //----- CM2CON0 Bits -------------------------------------------------------
357 //----- CM2CON1 Bits -------------------------------------------------------
360 //----- ANSEL --------------------------------------------------------------
363 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
364 //----- EECON1 -------------------------------------------------------------
367 //----- PSTRCON -------------------------------------------------------------
370 //----- SRCON ---------------------------------------------------------------
373 //==========================================================================
377 //==========================================================================
380 // __BADRAM H'08'-H'09', H'1B'
381 // __BADRAM H'88'-H'89', H'91', H'9C'-H'9D'
382 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
383 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
385 //==========================================================================
387 // Configuration Bits
389 //==========================================================================
391 #define _FCMEN_ON 0x3FFF
392 #define _FCMEN_OFF 0x37FF
393 #define _IESO_ON 0x3FFF
394 #define _IESO_OFF 0x3BFF
395 #define _BOD_ON 0x3FFF
396 #define _BOD_NSLEEP 0x3EFF
397 #define _BOD_SBODEN 0x3DFF
398 #define _BOD_OFF 0x3CFF
399 #define _CPD_ON 0x3F7F
400 #define _CPD_OFF 0x3FFF
401 #define _CP_ON 0x3FBF
402 #define _CP_OFF 0x3FFF
403 #define _MCLRE_ON 0x3FFF
404 #define _MCLRE_OFF 0x3FDF
405 #define _PWRTE_OFF 0x3FFF
406 #define _PWRTE_ON 0x3FEF
407 #define _WDT_ON 0x3FFF
408 #define _WDT_OFF 0x3FF7
409 #define _LP_OSC 0x3FF8
410 #define _XT_OSC 0x3FF9
411 #define _HS_OSC 0x3FFA
412 #define _EC_OSC 0x3FFB
413 #define _INTRC_OSC_NOCLKOUT 0x3FFC
414 #define _INTRC_OSC_CLKOUT 0x3FFD
415 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
416 #define _EXTRC_OSC_CLKOUT 0x3FFF
417 #define _INTOSCIO 0x3FFC
418 #define _INTOSC 0x3FFD
419 #define _EXTRCIO 0x3FFE
420 #define _EXTRC 0x3FFF
424 // ----- ADCON0 bits --------------------
427 unsigned char ADON:1;
429 unsigned char CHS0:1;
430 unsigned char CHS1:1;
431 unsigned char CHS2:1;
432 unsigned char CHS3:1;
433 unsigned char VCFG:1;
434 unsigned char ADFM:1;
438 unsigned char NOT_DONE:1;
448 unsigned char GO_DONE:1;
457 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
459 #define ADON ADCON0_bits.ADON
460 #define GO ADCON0_bits.GO
461 #define NOT_DONE ADCON0_bits.NOT_DONE
462 #define GO_DONE ADCON0_bits.GO_DONE
463 #define CHS0 ADCON0_bits.CHS0
464 #define CHS1 ADCON0_bits.CHS1
465 #define CHS2 ADCON0_bits.CHS2
466 #define CHS3 ADCON0_bits.CHS3
467 #define VCFG ADCON0_bits.VCFG
468 #define ADFM ADCON0_bits.ADFM
470 // ----- BAUDCTL bits --------------------
473 unsigned char ABDEN:1;
476 unsigned char BRG16:1;
477 unsigned char CKTXP:1;
478 unsigned char ADCS1:1;
479 unsigned char RCIDL:1;
480 unsigned char ABDOVF:1;
487 unsigned char ADCS0:1;
489 unsigned char ADCS2:1;
493 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
495 #define ABDEN BAUDCTL_bits.ABDEN
496 #define WUE BAUDCTL_bits.WUE
497 #define BRG16 BAUDCTL_bits.BRG16
498 #define CKTXP BAUDCTL_bits.CKTXP
499 #define ADCS0 BAUDCTL_bits.ADCS0
500 #define ADCS1 BAUDCTL_bits.ADCS1
501 #define RCIDL BAUDCTL_bits.RCIDL
502 #define ADCS2 BAUDCTL_bits.ADCS2
503 #define ABDOVF BAUDCTL_bits.ABDOVF
505 // ----- CCP1CON bits --------------------
508 unsigned char CCP1M0:1;
509 unsigned char CCP1M1:1;
510 unsigned char CCP1M2:1;
511 unsigned char CCP1M3:1;
512 unsigned char DC1B0:1;
513 unsigned char DC1B1:1;
514 unsigned char P1M0:1;
515 unsigned char P1M1:1;
518 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
520 #define CCP1M0 CCP1CON_bits.CCP1M0
521 #define CCP1M1 CCP1CON_bits.CCP1M1
522 #define CCP1M2 CCP1CON_bits.CCP1M2
523 #define CCP1M3 CCP1CON_bits.CCP1M3
524 #define DC1B0 CCP1CON_bits.DC1B0
525 #define DC1B1 CCP1CON_bits.DC1B1
526 #define P1M0 CCP1CON_bits.P1M0
527 #define P1M1 CCP1CON_bits.P1M1
529 // ----- CM1CON0 bits --------------------
532 unsigned char C1CH0:1;
533 unsigned char C1CH1:1;
536 unsigned char C1POL:1;
537 unsigned char C1OE:1;
538 unsigned char C1OUT:1;
539 unsigned char C1ON:1;
542 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
544 #define C1CH0 CM1CON0_bits.C1CH0
545 #define C1CH1 CM1CON0_bits.C1CH1
546 #define C1R CM1CON0_bits.C1R
547 #define C1POL CM1CON0_bits.C1POL
548 #define C1OE CM1CON0_bits.C1OE
549 #define C1OUT CM1CON0_bits.C1OUT
550 #define C1ON CM1CON0_bits.C1ON
552 // ----- CM2CON0 bits --------------------
555 unsigned char C2CH0:1;
556 unsigned char C2CH1:1;
559 unsigned char C2POL:1;
560 unsigned char C2OE:1;
561 unsigned char C2OUT:1;
562 unsigned char C2ON:1;
565 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
567 #define C2CH0 CM2CON0_bits.C2CH0
568 #define C2CH1 CM2CON0_bits.C2CH1
569 #define C2R CM2CON0_bits.C2R
570 #define C2POL CM2CON0_bits.C2POL
571 #define C2OE CM2CON0_bits.C2OE
572 #define C2OUT CM2CON0_bits.C2OUT
573 #define C2ON CM2CON0_bits.C2ON
575 // ----- CM2CON1 bits --------------------
578 unsigned char C2SYNC:1;
579 unsigned char T1GSS:1;
580 unsigned char ANS2:1;
581 unsigned char ANS3:1;
582 unsigned char ANS4:1;
583 unsigned char ANS5:1;
584 unsigned char MC2OUT:1;
585 unsigned char MC1OUT:1;
588 unsigned char ANS0:1;
589 unsigned char ANS1:1;
590 unsigned char WREN:1;
591 unsigned char WRERR:1;
592 unsigned char STRSYNC:1;
593 unsigned char C1SEN:1;
594 unsigned char ANS6:1;
595 unsigned char ANS7:1;
600 unsigned char STRC:1;
601 unsigned char STRD:1;
602 unsigned char C2REN:1;
605 unsigned char EEPGD:1;
608 unsigned char STRA:1;
609 unsigned char STRB:1;
610 unsigned char PULSR:1;
611 unsigned char PULSS:1;
618 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
620 #define C2SYNC CM2CON1_bits.C2SYNC
621 #define ANS0 CM2CON1_bits.ANS0
622 #define RD CM2CON1_bits.RD
623 #define STRA CM2CON1_bits.STRA
624 #define T1GSS CM2CON1_bits.T1GSS
625 #define ANS1 CM2CON1_bits.ANS1
626 #define WR CM2CON1_bits.WR
627 #define STRB CM2CON1_bits.STRB
628 #define ANS2 CM2CON1_bits.ANS2
629 #define WREN CM2CON1_bits.WREN
630 #define STRC CM2CON1_bits.STRC
631 #define PULSR CM2CON1_bits.PULSR
632 #define ANS3 CM2CON1_bits.ANS3
633 #define WRERR CM2CON1_bits.WRERR
634 #define STRD CM2CON1_bits.STRD
635 #define PULSS CM2CON1_bits.PULSS
636 #define ANS4 CM2CON1_bits.ANS4
637 #define STRSYNC CM2CON1_bits.STRSYNC
638 #define C2REN CM2CON1_bits.C2REN
639 #define ANS5 CM2CON1_bits.ANS5
640 #define C1SEN CM2CON1_bits.C1SEN
641 #define MC2OUT CM2CON1_bits.MC2OUT
642 #define ANS6 CM2CON1_bits.ANS6
643 #define SR0 CM2CON1_bits.SR0
644 #define MC1OUT CM2CON1_bits.MC1OUT
645 #define ANS7 CM2CON1_bits.ANS7
646 #define EEPGD CM2CON1_bits.EEPGD
647 #define SR1 CM2CON1_bits.SR1
649 // ----- ECCPAS bits --------------------
652 unsigned char PSSBD0:1;
653 unsigned char PSSBD1:1;
654 unsigned char PSSAC0:1;
655 unsigned char PSSAC1:1;
656 unsigned char ECCPAS0:1;
657 unsigned char ECCPAS1:1;
658 unsigned char ECCPAS2:1;
659 unsigned char ECCPASE:1;
662 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
664 #define PSSBD0 ECCPAS_bits.PSSBD0
665 #define PSSBD1 ECCPAS_bits.PSSBD1
666 #define PSSAC0 ECCPAS_bits.PSSAC0
667 #define PSSAC1 ECCPAS_bits.PSSAC1
668 #define ECCPAS0 ECCPAS_bits.ECCPAS0
669 #define ECCPAS1 ECCPAS_bits.ECCPAS1
670 #define ECCPAS2 ECCPAS_bits.ECCPAS2
671 #define ECCPASE ECCPAS_bits.ECCPASE
673 // ----- INTCON bits --------------------
676 unsigned char RABIF:1;
677 unsigned char INTF:1;
678 unsigned char T0IF:1;
679 unsigned char RABIE:1;
680 unsigned char INTE:1;
681 unsigned char T0IE:1;
682 unsigned char PEIE:1;
686 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
688 #define RABIF INTCON_bits.RABIF
689 #define INTF INTCON_bits.INTF
690 #define T0IF INTCON_bits.T0IF
691 #define RABIE INTCON_bits.RABIE
692 #define INTE INTCON_bits.INTE
693 #define T0IE INTCON_bits.T0IE
694 #define PEIE INTCON_bits.PEIE
695 #define GIE INTCON_bits.GIE
697 // ----- OPTION_REG bits --------------------
704 unsigned char T0SE:1;
705 unsigned char T0CS:1;
706 unsigned char INTEDG:1;
707 unsigned char NOT_RABPU:1;
709 } __OPTION_REG_bits_t;
710 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
712 #define PS0 OPTION_REG_bits.PS0
713 #define PS1 OPTION_REG_bits.PS1
714 #define PS2 OPTION_REG_bits.PS2
715 #define PSA OPTION_REG_bits.PSA
716 #define T0SE OPTION_REG_bits.T0SE
717 #define T0CS OPTION_REG_bits.T0CS
718 #define INTEDG OPTION_REG_bits.INTEDG
719 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
721 // ----- OSCCON bits --------------------
727 unsigned char OSTS:1;
728 unsigned char IRCF0:1;
729 unsigned char IRCF1:1;
730 unsigned char IRCF2:1;
734 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
736 #define SCS OSCCON_bits.SCS
737 #define LTS OSCCON_bits.LTS
738 #define HTS OSCCON_bits.HTS
739 #define OSTS OSCCON_bits.OSTS
740 #define IRCF0 OSCCON_bits.IRCF0
741 #define IRCF1 OSCCON_bits.IRCF1
742 #define IRCF2 OSCCON_bits.IRCF2
744 // ----- OSCTUNE bits --------------------
747 unsigned char TUN0:1;
748 unsigned char TUN1:1;
749 unsigned char TUN2:1;
750 unsigned char TUN3:1;
751 unsigned char TUN4:1;
757 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
759 #define TUN0 OSCTUNE_bits.TUN0
760 #define TUN1 OSCTUNE_bits.TUN1
761 #define TUN2 OSCTUNE_bits.TUN2
762 #define TUN3 OSCTUNE_bits.TUN3
763 #define TUN4 OSCTUNE_bits.TUN4
765 // ----- PCON bits --------------------
768 unsigned char NOT_BOD:1;
769 unsigned char NOT_POR:1;
772 unsigned char SBODEN:1;
773 unsigned char ULPWUE:1;
778 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
780 #define NOT_BOD PCON_bits.NOT_BOD
781 #define NOT_POR PCON_bits.NOT_POR
782 #define SBODEN PCON_bits.SBODEN
783 #define ULPWUE PCON_bits.ULPWUE
785 // ----- PIE1 bits --------------------
788 unsigned char T1IE:1;
789 unsigned char T2IE:1;
790 unsigned char CCPIE:1;
791 unsigned char SSPIE:1;
792 unsigned char TXIE:1;
793 unsigned char RCIE:1;
794 unsigned char ADIE:1;
798 unsigned char TMR1IE:1;
799 unsigned char TMR2IE:1;
808 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
810 #define T1IE PIE1_bits.T1IE
811 #define TMR1IE PIE1_bits.TMR1IE
812 #define T2IE PIE1_bits.T2IE
813 #define TMR2IE PIE1_bits.TMR2IE
814 #define CCPIE PIE1_bits.CCPIE
815 #define SSPIE PIE1_bits.SSPIE
816 #define TXIE PIE1_bits.TXIE
817 #define RCIE PIE1_bits.RCIE
818 #define ADIE PIE1_bits.ADIE
820 // ----- PIE2 bits --------------------
827 unsigned char EEIE:1;
828 unsigned char C1IE:1;
829 unsigned char C2IE:1;
830 unsigned char OSFIE:1;
833 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
835 #define EEIE PIE2_bits.EEIE
836 #define C1IE PIE2_bits.C1IE
837 #define C2IE PIE2_bits.C2IE
838 #define OSFIE PIE2_bits.OSFIE
840 // ----- PIR1 bits --------------------
843 unsigned char T1IF:1;
844 unsigned char T2IF:1;
845 unsigned char CCP1IF:1;
846 unsigned char SSPIF:1;
847 unsigned char TXIF:1;
848 unsigned char RCIF:1;
849 unsigned char ADIF:1;
853 unsigned char TMR1IF:1;
854 unsigned char TMR2IF:1;
863 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
865 #define T1IF PIR1_bits.T1IF
866 #define TMR1IF PIR1_bits.TMR1IF
867 #define T2IF PIR1_bits.T2IF
868 #define TMR2IF PIR1_bits.TMR2IF
869 #define CCP1IF PIR1_bits.CCP1IF
870 #define SSPIF PIR1_bits.SSPIF
871 #define TXIF PIR1_bits.TXIF
872 #define RCIF PIR1_bits.RCIF
873 #define ADIF PIR1_bits.ADIF
875 // ----- PIR2 bits --------------------
882 unsigned char EEIF:1;
883 unsigned char C1IF:1;
884 unsigned char C2IF:1;
885 unsigned char OSFIF:1;
888 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
890 #define EEIF PIR2_bits.EEIF
891 #define C1IF PIR2_bits.C1IF
892 #define C2IF PIR2_bits.C2IF
893 #define OSFIF PIR2_bits.OSFIF
895 // ----- PWM1CON bits --------------------
898 unsigned char PDC0:1;
899 unsigned char PDC1:1;
900 unsigned char PDC2:1;
901 unsigned char PDC3:1;
902 unsigned char PDC4:1;
903 unsigned char PDC5:1;
904 unsigned char PDC6:1;
905 unsigned char PRSEN:1;
908 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
910 #define PDC0 PWM1CON_bits.PDC0
911 #define PDC1 PWM1CON_bits.PDC1
912 #define PDC2 PWM1CON_bits.PDC2
913 #define PDC3 PWM1CON_bits.PDC3
914 #define PDC4 PWM1CON_bits.PDC4
915 #define PDC5 PWM1CON_bits.PDC5
916 #define PDC6 PWM1CON_bits.PDC6
917 #define PRSEN PWM1CON_bits.PRSEN
919 // ----- RCSTA bits --------------------
922 unsigned char RX9D:1;
923 unsigned char OERR:1;
924 unsigned char FERR:1;
925 unsigned char ADDEN:1;
926 unsigned char CREN:1;
927 unsigned char SREN:1;
929 unsigned char SPEN:1;
932 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
934 #define RX9D RCSTA_bits.RX9D
935 #define OERR RCSTA_bits.OERR
936 #define FERR RCSTA_bits.FERR
937 #define ADDEN RCSTA_bits.ADDEN
938 #define CREN RCSTA_bits.CREN
939 #define SREN RCSTA_bits.SREN
940 #define RX9 RCSTA_bits.RX9
941 #define SPEN RCSTA_bits.SPEN
943 // ----- SPBRG bits --------------------
946 unsigned char BRG0:1;
947 unsigned char BRG1:1;
948 unsigned char BRG2:1;
949 unsigned char BRG3:1;
950 unsigned char BRG4:1;
951 unsigned char BRG5:1;
952 unsigned char BRG6:1;
953 unsigned char BRG7:1;
956 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
958 #define BRG0 SPBRG_bits.BRG0
959 #define BRG1 SPBRG_bits.BRG1
960 #define BRG2 SPBRG_bits.BRG2
961 #define BRG3 SPBRG_bits.BRG3
962 #define BRG4 SPBRG_bits.BRG4
963 #define BRG5 SPBRG_bits.BRG5
964 #define BRG6 SPBRG_bits.BRG6
965 #define BRG7 SPBRG_bits.BRG7
967 // ----- SPBRGH bits --------------------
970 unsigned char BRG8:1;
971 unsigned char BRG9:1;
972 unsigned char BRG10:1;
973 unsigned char BRG11:1;
974 unsigned char BRG12:1;
975 unsigned char BRG13:1;
976 unsigned char BRG14:1;
977 unsigned char BRG15:1;
980 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
982 #define BRG8 SPBRGH_bits.BRG8
983 #define BRG9 SPBRGH_bits.BRG9
984 #define BRG10 SPBRGH_bits.BRG10
985 #define BRG11 SPBRGH_bits.BRG11
986 #define BRG12 SPBRGH_bits.BRG12
987 #define BRG13 SPBRGH_bits.BRG13
988 #define BRG14 SPBRGH_bits.BRG14
989 #define BRG15 SPBRGH_bits.BRG15
991 // ----- SSPCON bits --------------------
994 unsigned char SSPM0:1;
995 unsigned char SSPM1:1;
996 unsigned char SSPM2:1;
997 unsigned char SSPM3:1;
999 unsigned char SSPEN:1;
1000 unsigned char SSPOV:1;
1001 unsigned char WCOL:1;
1004 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1006 #define SSPM0 SSPCON_bits.SSPM0
1007 #define SSPM1 SSPCON_bits.SSPM1
1008 #define SSPM2 SSPCON_bits.SSPM2
1009 #define SSPM3 SSPCON_bits.SSPM3
1010 #define CKP SSPCON_bits.CKP
1011 #define SSPEN SSPCON_bits.SSPEN
1012 #define SSPOV SSPCON_bits.SSPOV
1013 #define WCOL SSPCON_bits.WCOL
1015 // ----- SSPSTAT bits --------------------
1020 unsigned char R_W_NOT:1;
1023 unsigned char D_A_NOT:1;
1024 unsigned char CKE:1;
1025 unsigned char SMP:1;
1028 unsigned char WPUA0:1;
1029 unsigned char WPUA1:1;
1030 unsigned char WPUA2:1;
1031 unsigned char IOC3:1;
1032 unsigned char WPUA4:1;
1033 unsigned char WPUA5:1;
1038 unsigned char IOC0:1;
1039 unsigned char IOC1:1;
1040 unsigned char IOC2:1;
1041 unsigned char IOCA3:1;
1042 unsigned char IOC4:1;
1043 unsigned char IOC5:1;
1048 unsigned char IOCA0:1;
1049 unsigned char IOCA1:1;
1050 unsigned char IOCA2:1;
1052 unsigned char IOCA4:1;
1053 unsigned char IOCA5:1;
1058 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1060 #define BF SSPSTAT_bits.BF
1061 #define WPUA0 SSPSTAT_bits.WPUA0
1062 #define IOC0 SSPSTAT_bits.IOC0
1063 #define IOCA0 SSPSTAT_bits.IOCA0
1064 #define UA SSPSTAT_bits.UA
1065 #define WPUA1 SSPSTAT_bits.WPUA1
1066 #define IOC1 SSPSTAT_bits.IOC1
1067 #define IOCA1 SSPSTAT_bits.IOCA1
1068 #define R_W_NOT SSPSTAT_bits.R_W_NOT
1069 #define WPUA2 SSPSTAT_bits.WPUA2
1070 #define IOC2 SSPSTAT_bits.IOC2
1071 #define IOCA2 SSPSTAT_bits.IOCA2
1072 #define S SSPSTAT_bits.S
1073 #define IOC3 SSPSTAT_bits.IOC3
1074 #define IOCA3 SSPSTAT_bits.IOCA3
1075 #define P SSPSTAT_bits.P
1076 #define WPUA4 SSPSTAT_bits.WPUA4
1077 #define IOC4 SSPSTAT_bits.IOC4
1078 #define IOCA4 SSPSTAT_bits.IOCA4
1079 #define D_A_NOT SSPSTAT_bits.D_A_NOT
1080 #define WPUA5 SSPSTAT_bits.WPUA5
1081 #define IOC5 SSPSTAT_bits.IOC5
1082 #define IOCA5 SSPSTAT_bits.IOCA5
1083 #define CKE SSPSTAT_bits.CKE
1084 #define SMP SSPSTAT_bits.SMP
1086 // ----- STATUS bits --------------------
1092 unsigned char NOT_PD:1;
1093 unsigned char NOT_TO:1;
1094 unsigned char RP0:1;
1095 unsigned char RP1:1;
1096 unsigned char IRP:1;
1099 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1101 #define C STATUS_bits.C
1102 #define DC STATUS_bits.DC
1103 #define Z STATUS_bits.Z
1104 #define NOT_PD STATUS_bits.NOT_PD
1105 #define NOT_TO STATUS_bits.NOT_TO
1106 #define RP0 STATUS_bits.RP0
1107 #define RP1 STATUS_bits.RP1
1108 #define IRP STATUS_bits.IRP
1110 // ----- T1CON bits --------------------
1113 unsigned char TMR1ON:1;
1114 unsigned char TMR1CS:1;
1115 unsigned char NOT_T1SYNC:1;
1116 unsigned char T1OSCEN:1;
1117 unsigned char T1CKPS0:1;
1118 unsigned char T1CKPS1:1;
1119 unsigned char TMR1GE:1;
1120 unsigned char T1GINV:1;
1123 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1125 #define TMR1ON T1CON_bits.TMR1ON
1126 #define TMR1CS T1CON_bits.TMR1CS
1127 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1128 #define T1OSCEN T1CON_bits.T1OSCEN
1129 #define T1CKPS0 T1CON_bits.T1CKPS0
1130 #define T1CKPS1 T1CON_bits.T1CKPS1
1131 #define TMR1GE T1CON_bits.TMR1GE
1132 #define T1GINV T1CON_bits.T1GINV
1134 // ----- T2CON bits --------------------
1137 unsigned char T2CKPS0:1;
1138 unsigned char T2CKPS1:1;
1139 unsigned char TMR2ON:1;
1140 unsigned char TOUTPS0:1;
1141 unsigned char TOUTPS1:1;
1142 unsigned char TOUTPS2:1;
1143 unsigned char TOUTPS3:1;
1147 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1149 #define T2CKPS0 T2CON_bits.T2CKPS0
1150 #define T2CKPS1 T2CON_bits.T2CKPS1
1151 #define TMR2ON T2CON_bits.TMR2ON
1152 #define TOUTPS0 T2CON_bits.TOUTPS0
1153 #define TOUTPS1 T2CON_bits.TOUTPS1
1154 #define TOUTPS2 T2CON_bits.TOUTPS2
1155 #define TOUTPS3 T2CON_bits.TOUTPS3
1157 // ----- TRISA bits --------------------
1160 unsigned char TRISA0:1;
1161 unsigned char TRISA1:1;
1162 unsigned char TRISA2:1;
1163 unsigned char TRISA3:1;
1164 unsigned char TRISA4:1;
1165 unsigned char TRISA5:1;
1170 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1172 #define TRISA0 TRISA_bits.TRISA0
1173 #define TRISA1 TRISA_bits.TRISA1
1174 #define TRISA2 TRISA_bits.TRISA2
1175 #define TRISA3 TRISA_bits.TRISA3
1176 #define TRISA4 TRISA_bits.TRISA4
1177 #define TRISA5 TRISA_bits.TRISA5
1179 // ----- TRISB bits --------------------
1186 unsigned char TRISB4:1;
1187 unsigned char TRISB5:1;
1188 unsigned char TRISB6:1;
1189 unsigned char TRISB7:1;
1192 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1194 #define TRISB4 TRISB_bits.TRISB4
1195 #define TRISB5 TRISB_bits.TRISB5
1196 #define TRISB6 TRISB_bits.TRISB6
1197 #define TRISB7 TRISB_bits.TRISB7
1199 // ----- TRISC bits --------------------
1202 unsigned char TRISC0:1;
1203 unsigned char TRISC1:1;
1204 unsigned char TRISC2:1;
1205 unsigned char TRISC3:1;
1206 unsigned char TRISC4:1;
1207 unsigned char TRISC5:1;
1208 unsigned char TRISC6:1;
1209 unsigned char TRISC7:1;
1212 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1214 #define TRISC0 TRISC_bits.TRISC0
1215 #define TRISC1 TRISC_bits.TRISC1
1216 #define TRISC2 TRISC_bits.TRISC2
1217 #define TRISC3 TRISC_bits.TRISC3
1218 #define TRISC4 TRISC_bits.TRISC4
1219 #define TRISC5 TRISC_bits.TRISC5
1220 #define TRISC6 TRISC_bits.TRISC6
1221 #define TRISC7 TRISC_bits.TRISC7
1223 // ----- TXSTA bits --------------------
1226 unsigned char TX9D:1;
1227 unsigned char TRMT:1;
1228 unsigned char BRGH:1;
1229 unsigned char SENB:1;
1230 unsigned char SYNC:1;
1231 unsigned char TXEN:1;
1232 unsigned char TX9:1;
1233 unsigned char CSRC:1;
1236 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1238 #define TX9D TXSTA_bits.TX9D
1239 #define TRMT TXSTA_bits.TRMT
1240 #define BRGH TXSTA_bits.BRGH
1241 #define SENB TXSTA_bits.SENB
1242 #define SYNC TXSTA_bits.SYNC
1243 #define TXEN TXSTA_bits.TXEN
1244 #define TX9 TXSTA_bits.TX9
1245 #define CSRC TXSTA_bits.CSRC
1247 // ----- VRCON bits --------------------
1250 unsigned char VR0:1;
1251 unsigned char VR1:1;
1252 unsigned char VR2:1;
1253 unsigned char VR3:1;
1254 unsigned char VP6EN:1;
1255 unsigned char VRR:1;
1256 unsigned char C2VREN:1;
1257 unsigned char C1VREN:1;
1260 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1262 #define VR0 VRCON_bits.VR0
1263 #define VR1 VRCON_bits.VR1
1264 #define VR2 VRCON_bits.VR2
1265 #define VR3 VRCON_bits.VR3
1266 #define VP6EN VRCON_bits.VP6EN
1267 #define VRR VRCON_bits.VRR
1268 #define C2VREN VRCON_bits.C2VREN
1269 #define C1VREN VRCON_bits.C1VREN
1271 // ----- WDTCON bits --------------------
1274 unsigned char SWDTEN:1;
1275 unsigned char WDTPS0:1;
1276 unsigned char WDTPS1:1;
1277 unsigned char WDTPS2:1;
1278 unsigned char WDTPS3:1;
1284 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1286 #define SWDTEN WDTCON_bits.SWDTEN
1287 #define WDTPS0 WDTCON_bits.WDTPS0
1288 #define WDTPS1 WDTCON_bits.WDTPS1
1289 #define WDTPS2 WDTCON_bits.WDTPS2
1290 #define WDTPS3 WDTCON_bits.WDTPS3
1292 // ----- WPUB bits --------------------
1299 unsigned char WPUB4:1;
1300 unsigned char WPUB5:1;
1301 unsigned char WPUB6:1;
1302 unsigned char WPUB7:1;
1309 unsigned char IOCB4:1;
1310 unsigned char IOCB5:1;
1311 unsigned char IOCB6:1;
1312 unsigned char IOCB7:1;
1315 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1317 #define WPUB4 WPUB_bits.WPUB4
1318 #define IOCB4 WPUB_bits.IOCB4
1319 #define WPUB5 WPUB_bits.WPUB5
1320 #define IOCB5 WPUB_bits.IOCB5
1321 #define WPUB6 WPUB_bits.WPUB6
1322 #define IOCB6 WPUB_bits.IOCB6
1323 #define WPUB7 WPUB_bits.WPUB7
1324 #define IOCB7 WPUB_bits.IOCB7