2 // Register Declarations for Microchip 16F689 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define SSPBUF_ADDR 0x0013
44 #define SSPCON_ADDR 0x0014
45 #define RCSTA_ADDR 0x0018
46 #define TXREG_ADDR 0x0019
47 #define RCREG_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define SSPADD_ADDR 0x0093
60 #define MSK_ADDR 0x0093
61 #define SSPMSK_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define WPU_ADDR 0x0095
64 #define WPUA_ADDR 0x0095
65 #define IOC_ADDR 0x0096
66 #define IOCA_ADDR 0x0096
67 #define WDTCON_ADDR 0x0097
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define SPBRGH_ADDR 0x009A
71 #define BAUDCTL_ADDR 0x009B
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
74 #define EEDATA_ADDR 0x010C
75 #define EEADR_ADDR 0x010D
76 #define EEDATH_ADDR 0x010E
77 #define EEADRH_ADDR 0x010F
78 #define WPUB_ADDR 0x0115
79 #define IOCB_ADDR 0x0116
80 #define VRCON_ADDR 0x0118
81 #define CM1CON0_ADDR 0x0119
82 #define CM2CON0_ADDR 0x011A
83 #define CM2CON1_ADDR 0x011B
84 #define ANSEL_ADDR 0x011E
85 #define ANSELH_ADDR 0x011F
86 #define EECON1_ADDR 0x018C
87 #define EECON2_ADDR 0x018D
88 #define SRCON_ADDR 0x019E
91 // Memory organization.
97 // P16F689.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
100 // This header file defines configurations, registers, and other useful bits of
101 // information for the PIC16F689 microcontroller. These names are taken to match
102 // the data sheets as closely as possible.
104 // Note that the processor must be selected before this file is
105 // included. The processor may be selected the following ways:
107 // 1. Command line switch:
108 // C:\ MPASM MYFILE.ASM /PIC16F689
109 // 2. LIST directive in the source file
111 // 3. Processor Type entry in the MPASM full-screen interface
113 //==========================================================================
117 //==========================================================================
118 //1.00 10/12/04 Original
119 //==========================================================================
123 //==========================================================================
126 // MESSG "Processor-header file mismatch. Verify selected processor."
129 //==========================================================================
131 // Register Definitions
133 //==========================================================================
138 //----- Register Files------------------------------------------------------
140 extern __data __at (INDF_ADDR) volatile char INDF;
141 extern __sfr __at (TMR0_ADDR) TMR0;
142 extern __data __at (PCL_ADDR) volatile char PCL;
143 extern __sfr __at (STATUS_ADDR) STATUS;
144 extern __sfr __at (FSR_ADDR) FSR;
145 extern __sfr __at (PORTA_ADDR) PORTA;
146 extern __sfr __at (PORTB_ADDR) PORTB;
147 extern __sfr __at (PORTC_ADDR) PORTC;
149 extern __sfr __at (PCLATH_ADDR) PCLATH;
150 extern __sfr __at (INTCON_ADDR) INTCON;
151 extern __sfr __at (PIR1_ADDR) PIR1;
152 extern __sfr __at (PIR2_ADDR) PIR2;
153 extern __sfr __at (TMR1L_ADDR) TMR1L;
154 extern __sfr __at (TMR1H_ADDR) TMR1H;
155 extern __sfr __at (T1CON_ADDR) T1CON;
158 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
159 extern __sfr __at (SSPCON_ADDR) SSPCON;
162 extern __sfr __at (RCSTA_ADDR) RCSTA;
163 extern __sfr __at (TXREG_ADDR) TXREG;
164 extern __sfr __at (RCREG_ADDR) RCREG;
166 extern __sfr __at (ADRESH_ADDR) ADRESH;
167 extern __sfr __at (ADCON0_ADDR) ADCON0;
170 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
172 extern __sfr __at (TRISA_ADDR) TRISA;
173 extern __sfr __at (TRISB_ADDR) TRISB;
174 extern __sfr __at (TRISC_ADDR) TRISC;
176 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PIE2_ADDR) PIE2;
178 extern __sfr __at (PCON_ADDR) PCON;
179 extern __sfr __at (OSCCON_ADDR) OSCCON;
180 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
182 extern __sfr __at (SSPADD_ADDR) SSPADD;
183 extern __sfr __at (MSK_ADDR) MSK;
184 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
185 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
186 extern __sfr __at (WPU_ADDR) WPU;
187 extern __sfr __at (WPUA_ADDR) WPUA;
188 extern __sfr __at (IOC_ADDR) IOC;
189 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (WDTCON_ADDR) WDTCON;
191 extern __sfr __at (TXSTA_ADDR) TXSTA;
192 extern __sfr __at (SPBRG_ADDR) SPBRG;
193 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
194 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
197 extern __sfr __at (ADRESL_ADDR) ADRESL;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
202 extern __sfr __at (EEDATA_ADDR) EEDATA;
203 extern __sfr __at (EEADR_ADDR) EEADR;
204 extern __sfr __at (EEDATH_ADDR) EEDATH;
205 extern __sfr __at (EEADRH_ADDR) EEADRH;
208 extern __sfr __at (WPUB_ADDR) WPUB;
209 extern __sfr __at (IOCB_ADDR) IOCB;
211 extern __sfr __at (VRCON_ADDR) VRCON;
212 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
213 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
214 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
216 extern __sfr __at (ANSEL_ADDR) ANSEL;
217 extern __sfr __at (ANSELH_ADDR) ANSELH;
219 extern __sfr __at (EECON1_ADDR) EECON1;
220 extern __sfr __at (EECON2_ADDR) EECON2;
223 extern __sfr __at (SRCON_ADDR) SRCON;
227 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
228 //----- STATUS Bits --------------------------------------------------------
231 //----- INTCON Bits --------------------------------------------------------
234 //----- PIR1 Bits ----------------------------------------------------------
239 //----- PIR2 Bits ----------------------------------------------------------
242 //----- T1CON Bits ---------------------------------------------------------
246 //----- SSPCON Bits -------------------------------------------------------
250 //----- RCSTA Bits ---------------------------------------------------------
254 //----- ADCON0 Bits --------------------------------------------------------
257 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
258 //----- OPTION Bits --------------------------------------------------------
261 //----- TRISA Bits --------------------------------------------------------
264 //----- TRISB Bits --------------------------------------------------------
267 //----- TRISC Bits --------------------------------------------------------
270 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PIE2 Bits ----------------------------------------------------------
278 //----- PCON Bits ----------------------------------------------------------
281 //----- OSCCON Bits --------------------------------------------------------
284 //----- OSCTUNE Bits -------------------------------------------------------
287 //----- SSPSTAT Bits --------------------------------------------------------
290 //----- WPUA --------------------------------------------------------------
294 //----- IOC --------------------------------------------------------------
297 //----- IOCA --------------------------------------------------------------
300 //----- WDTCON Bits --------------------------------------------------------
303 //----- TXSTA Bits -------------------------------------------------------
306 //----- SPBRG Bits -------------------------------------------------------
309 //----- SPBRGH Bits -------------------------------------------------------
312 //----- BAUDCTL Bits -------------------------------------------------------
317 //----- ADCON1 -------------------------------------------------------------
320 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
321 //----- WPUB Bits ----------------------------------------------------------
324 //----- IOCB --------------------------------------------------------------
327 //----- VRCON Bits ---------------------------------------------------------
330 //----- CM1CON0 Bits -------------------------------------------------------
334 //----- CM2CON0 Bits -------------------------------------------------------
338 //----- CM2CON1 Bits -------------------------------------------------------
341 //----- ANSEL --------------------------------------------------------------
344 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
345 //----- EECON1 -------------------------------------------------------------
348 //----- SRCON ---------------------------------------------------------------
351 //==========================================================================
355 //==========================================================================
358 // __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'-H'1D'
359 // __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D'
360 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
361 // __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF'
363 //==========================================================================
365 // Configuration Bits
367 //==========================================================================
369 #define _FCMEN_ON 0x3FFF
370 #define _FCMEN_OFF 0x37FF
371 #define _IESO_ON 0x3FFF
372 #define _IESO_OFF 0x3BFF
373 #define _BOD_ON 0x3FFF
374 #define _BOD_NSLEEP 0x3EFF
375 #define _BOD_SBODEN 0x3DFF
376 #define _BOD_OFF 0x3CFF
377 #define _CPD_ON 0x3F7F
378 #define _CPD_OFF 0x3FFF
379 #define _CP_ON 0x3FBF
380 #define _CP_OFF 0x3FFF
381 #define _MCLRE_ON 0x3FFF
382 #define _MCLRE_OFF 0x3FDF
383 #define _PWRTE_OFF 0x3FFF
384 #define _PWRTE_ON 0x3FEF
385 #define _WDT_ON 0x3FFF
386 #define _WDT_OFF 0x3FF7
387 #define _LP_OSC 0x3FF8
388 #define _XT_OSC 0x3FF9
389 #define _HS_OSC 0x3FFA
390 #define _EC_OSC 0x3FFB
391 #define _INTRC_OSC_NOCLKOUT 0x3FFC
392 #define _INTRC_OSC_CLKOUT 0x3FFD
393 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
394 #define _EXTRC_OSC_CLKOUT 0x3FFF
395 #define _INTOSCIO 0x3FFC
396 #define _INTOSC 0x3FFD
397 #define _EXTRCIO 0x3FFE
398 #define _EXTRC 0x3FFF
402 // ----- ADCON0 bits --------------------
405 unsigned char ADON:1;
407 unsigned char CHS0:1;
408 unsigned char CHS1:1;
409 unsigned char CHS2:1;
410 unsigned char CHS3:1;
411 unsigned char VCFG:1;
412 unsigned char ADFM:1;
416 unsigned char NOT_DONE:1;
426 unsigned char GO_DONE:1;
435 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
437 #define ADON ADCON0_bits.ADON
438 #define GO ADCON0_bits.GO
439 #define NOT_DONE ADCON0_bits.NOT_DONE
440 #define GO_DONE ADCON0_bits.GO_DONE
441 #define CHS0 ADCON0_bits.CHS0
442 #define CHS1 ADCON0_bits.CHS1
443 #define CHS2 ADCON0_bits.CHS2
444 #define CHS3 ADCON0_bits.CHS3
445 #define VCFG ADCON0_bits.VCFG
446 #define ADFM ADCON0_bits.ADFM
448 // ----- ADCON1 bits --------------------
455 unsigned char ADCS0:1;
456 unsigned char ADCS1:1;
457 unsigned char ADCS2:1;
461 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
463 #define ADCS0 ADCON1_bits.ADCS0
464 #define ADCS1 ADCON1_bits.ADCS1
465 #define ADCS2 ADCON1_bits.ADCS2
467 // ----- ANSEL bits --------------------
470 unsigned char ANS0:1;
471 unsigned char ANS1:1;
472 unsigned char ANS2:1;
473 unsigned char ANS3:1;
474 unsigned char ANS4:1;
475 unsigned char ANS5:1;
476 unsigned char ANS6:1;
477 unsigned char ANS7:1;
480 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
482 #define ANS0 ANSEL_bits.ANS0
483 #define ANS1 ANSEL_bits.ANS1
484 #define ANS2 ANSEL_bits.ANS2
485 #define ANS3 ANSEL_bits.ANS3
486 #define ANS4 ANSEL_bits.ANS4
487 #define ANS5 ANSEL_bits.ANS5
488 #define ANS6 ANSEL_bits.ANS6
489 #define ANS7 ANSEL_bits.ANS7
491 // ----- BAUDCTL bits --------------------
494 unsigned char ABDEN:1;
497 unsigned char BRG16:1;
498 unsigned char CKTXP:1;
500 unsigned char RCIDL:1;
501 unsigned char ABDOVF:1;
504 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
506 #define ABDEN BAUDCTL_bits.ABDEN
507 #define WUE BAUDCTL_bits.WUE
508 #define BRG16 BAUDCTL_bits.BRG16
509 #define CKTXP BAUDCTL_bits.CKTXP
510 #define RCIDL BAUDCTL_bits.RCIDL
511 #define ABDOVF BAUDCTL_bits.ABDOVF
513 // ----- CM1CON0 bits --------------------
516 unsigned char C1CH0:1;
517 unsigned char C1CH1:1;
520 unsigned char C1POL:1;
521 unsigned char C1OE:1;
522 unsigned char C1OUT:1;
523 unsigned char C1ON:1;
526 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
528 #define C1CH0 CM1CON0_bits.C1CH0
529 #define C1CH1 CM1CON0_bits.C1CH1
530 #define C1R CM1CON0_bits.C1R
531 #define C1POL CM1CON0_bits.C1POL
532 #define C1OE CM1CON0_bits.C1OE
533 #define C1OUT CM1CON0_bits.C1OUT
534 #define C1ON CM1CON0_bits.C1ON
536 // ----- CM2CON0 bits --------------------
539 unsigned char C2CH0:1;
540 unsigned char C2CH1:1;
543 unsigned char C2POL:1;
544 unsigned char C2OE:1;
545 unsigned char C2OUT:1;
546 unsigned char C2ON:1;
549 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
551 #define C2CH0 CM2CON0_bits.C2CH0
552 #define C2CH1 CM2CON0_bits.C2CH1
553 #define C2R CM2CON0_bits.C2R
554 #define C2POL CM2CON0_bits.C2POL
555 #define C2OE CM2CON0_bits.C2OE
556 #define C2OUT CM2CON0_bits.C2OUT
557 #define C2ON CM2CON0_bits.C2ON
559 // ----- CM2CON1 bits --------------------
562 unsigned char C2SYNC:1;
563 unsigned char T1GSS:1;
568 unsigned char MC2OUT:1;
569 unsigned char MC1OUT:1;
572 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
574 #define C2SYNC CM2CON1_bits.C2SYNC
575 #define T1GSS CM2CON1_bits.T1GSS
576 #define MC2OUT CM2CON1_bits.MC2OUT
577 #define MC1OUT CM2CON1_bits.MC1OUT
579 // ----- EECON1 bits --------------------
584 unsigned char WREN:1;
585 unsigned char WRERR:1;
589 unsigned char EEPGD:1;
592 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
594 #define RD EECON1_bits.RD
595 #define WR EECON1_bits.WR
596 #define WREN EECON1_bits.WREN
597 #define WRERR EECON1_bits.WRERR
598 #define EEPGD EECON1_bits.EEPGD
600 // ----- INTCON bits --------------------
603 unsigned char RABIF:1;
604 unsigned char INTF:1;
605 unsigned char T0IF:1;
606 unsigned char RABIE:1;
607 unsigned char INTE:1;
608 unsigned char T0IE:1;
609 unsigned char PEIE:1;
613 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
615 #define RABIF INTCON_bits.RABIF
616 #define INTF INTCON_bits.INTF
617 #define T0IF INTCON_bits.T0IF
618 #define RABIE INTCON_bits.RABIE
619 #define INTE INTCON_bits.INTE
620 #define T0IE INTCON_bits.T0IE
621 #define PEIE INTCON_bits.PEIE
622 #define GIE INTCON_bits.GIE
624 // ----- IOC bits --------------------
627 unsigned char IOC0:1;
628 unsigned char IOC1:1;
629 unsigned char IOC2:1;
630 unsigned char IOC3:1;
631 unsigned char IOC4:1;
632 unsigned char IOC5:1;
637 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
639 #define IOC0 IOC_bits.IOC0
640 #define IOC1 IOC_bits.IOC1
641 #define IOC2 IOC_bits.IOC2
642 #define IOC3 IOC_bits.IOC3
643 #define IOC4 IOC_bits.IOC4
644 #define IOC5 IOC_bits.IOC5
646 // ----- IOCA bits --------------------
649 unsigned char IOCA0:1;
650 unsigned char IOCA1:1;
651 unsigned char IOCA2:1;
652 unsigned char IOCA3:1;
653 unsigned char IOCA4:1;
654 unsigned char IOCA5:1;
659 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
661 #define IOCA0 IOCA_bits.IOCA0
662 #define IOCA1 IOCA_bits.IOCA1
663 #define IOCA2 IOCA_bits.IOCA2
664 #define IOCA3 IOCA_bits.IOCA3
665 #define IOCA4 IOCA_bits.IOCA4
666 #define IOCA5 IOCA_bits.IOCA5
668 // ----- IOCB bits --------------------
675 unsigned char IOCB4:1;
676 unsigned char IOCB5:1;
677 unsigned char IOCB6:1;
678 unsigned char IOCB7:1;
681 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
683 #define IOCB4 IOCB_bits.IOCB4
684 #define IOCB5 IOCB_bits.IOCB5
685 #define IOCB6 IOCB_bits.IOCB6
686 #define IOCB7 IOCB_bits.IOCB7
688 // ----- OPTION_REG bits --------------------
695 unsigned char T0SE:1;
696 unsigned char T0CS:1;
697 unsigned char INTEDG:1;
698 unsigned char NOT_RABPU:1;
700 } __OPTION_REG_bits_t;
701 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
703 #define PS0 OPTION_REG_bits.PS0
704 #define PS1 OPTION_REG_bits.PS1
705 #define PS2 OPTION_REG_bits.PS2
706 #define PSA OPTION_REG_bits.PSA
707 #define T0SE OPTION_REG_bits.T0SE
708 #define T0CS OPTION_REG_bits.T0CS
709 #define INTEDG OPTION_REG_bits.INTEDG
710 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
712 // ----- OSCCON bits --------------------
718 unsigned char OSTS:1;
719 unsigned char IRCF0:1;
720 unsigned char IRCF1:1;
721 unsigned char IRCF2:1;
725 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
727 #define SCS OSCCON_bits.SCS
728 #define LTS OSCCON_bits.LTS
729 #define HTS OSCCON_bits.HTS
730 #define OSTS OSCCON_bits.OSTS
731 #define IRCF0 OSCCON_bits.IRCF0
732 #define IRCF1 OSCCON_bits.IRCF1
733 #define IRCF2 OSCCON_bits.IRCF2
735 // ----- OSCTUNE bits --------------------
738 unsigned char TUN0:1;
739 unsigned char TUN1:1;
740 unsigned char TUN2:1;
741 unsigned char TUN3:1;
742 unsigned char TUN4:1;
748 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
750 #define TUN0 OSCTUNE_bits.TUN0
751 #define TUN1 OSCTUNE_bits.TUN1
752 #define TUN2 OSCTUNE_bits.TUN2
753 #define TUN3 OSCTUNE_bits.TUN3
754 #define TUN4 OSCTUNE_bits.TUN4
756 // ----- PCON bits --------------------
759 unsigned char NOT_BOD:1;
760 unsigned char NOT_POR:1;
763 unsigned char SBODEN:1;
764 unsigned char ULPWUE:1;
769 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
771 #define NOT_BOD PCON_bits.NOT_BOD
772 #define NOT_POR PCON_bits.NOT_POR
773 #define SBODEN PCON_bits.SBODEN
774 #define ULPWUE PCON_bits.ULPWUE
776 // ----- PIE1 bits --------------------
779 unsigned char T1IE:1;
782 unsigned char SSPIE:1;
783 unsigned char TXIE:1;
784 unsigned char RCIE:1;
785 unsigned char ADIE:1;
789 unsigned char TMR1IE:1;
799 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
801 #define T1IE PIE1_bits.T1IE
802 #define TMR1IE PIE1_bits.TMR1IE
803 #define SSPIE PIE1_bits.SSPIE
804 #define TXIE PIE1_bits.TXIE
805 #define RCIE PIE1_bits.RCIE
806 #define ADIE PIE1_bits.ADIE
808 // ----- PIE2 bits --------------------
815 unsigned char EEIE:1;
816 unsigned char C1IE:1;
817 unsigned char C2IE:1;
818 unsigned char OSFIE:1;
821 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
823 #define EEIE PIE2_bits.EEIE
824 #define C1IE PIE2_bits.C1IE
825 #define C2IE PIE2_bits.C2IE
826 #define OSFIE PIE2_bits.OSFIE
828 // ----- PIR1 bits --------------------
831 unsigned char T1IF:1;
834 unsigned char SSPIF:1;
835 unsigned char TXIF:1;
836 unsigned char RCIF:1;
837 unsigned char ADIF:1;
841 unsigned char TMR1IF:1;
851 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
853 #define T1IF PIR1_bits.T1IF
854 #define TMR1IF PIR1_bits.TMR1IF
855 #define SSPIF PIR1_bits.SSPIF
856 #define TXIF PIR1_bits.TXIF
857 #define RCIF PIR1_bits.RCIF
858 #define ADIF PIR1_bits.ADIF
860 // ----- PIR2 bits --------------------
867 unsigned char EEIF:1;
868 unsigned char C1IF:1;
869 unsigned char C2IF:1;
870 unsigned char OSFIF:1;
873 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
875 #define EEIF PIR2_bits.EEIF
876 #define C1IF PIR2_bits.C1IF
877 #define C2IF PIR2_bits.C2IF
878 #define OSFIF PIR2_bits.OSFIF
880 // ----- PORTA bits --------------------
893 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
895 #define RA0 PORTA_bits.RA0
896 #define RA1 PORTA_bits.RA1
897 #define RA2 PORTA_bits.RA2
898 #define RA3 PORTA_bits.RA3
899 #define RA4 PORTA_bits.RA4
900 #define RA5 PORTA_bits.RA5
902 // ----- PORTB bits --------------------
915 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
917 #define RB0 PORTB_bits.RB0
918 #define RB1 PORTB_bits.RB1
919 #define RB2 PORTB_bits.RB2
920 #define RB3 PORTB_bits.RB3
921 #define RB4 PORTB_bits.RB4
922 #define RB5 PORTB_bits.RB5
923 #define RB6 PORTB_bits.RB6
924 #define RB7 PORTB_bits.RB7
926 // ----- PORTC bits --------------------
939 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
941 #define RC0 PORTC_bits.RC0
942 #define RC1 PORTC_bits.RC1
943 #define RC2 PORTC_bits.RC2
944 #define RC3 PORTC_bits.RC3
945 #define RC4 PORTC_bits.RC4
946 #define RC5 PORTC_bits.RC5
947 #define RC6 PORTC_bits.RC6
948 #define RC7 PORTC_bits.RC7
950 // ----- RCSTA bits --------------------
953 unsigned char RX9D:1;
954 unsigned char OERR:1;
955 unsigned char FERR:1;
956 unsigned char ADDEN:1;
957 unsigned char CREN:1;
958 unsigned char SREN:1;
960 unsigned char SPEN:1;
963 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
965 #define RX9D RCSTA_bits.RX9D
966 #define OERR RCSTA_bits.OERR
967 #define FERR RCSTA_bits.FERR
968 #define ADDEN RCSTA_bits.ADDEN
969 #define CREN RCSTA_bits.CREN
970 #define SREN RCSTA_bits.SREN
971 #define RX9 RCSTA_bits.RX9
972 #define SPEN RCSTA_bits.SPEN
974 // ----- SPBRG bits --------------------
977 unsigned char BRG0:1;
978 unsigned char BRG1:1;
979 unsigned char BRG2:1;
980 unsigned char BRG3:1;
981 unsigned char BRG4:1;
982 unsigned char BRG5:1;
983 unsigned char BRG6:1;
984 unsigned char BRG7:1;
987 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
989 #define BRG0 SPBRG_bits.BRG0
990 #define BRG1 SPBRG_bits.BRG1
991 #define BRG2 SPBRG_bits.BRG2
992 #define BRG3 SPBRG_bits.BRG3
993 #define BRG4 SPBRG_bits.BRG4
994 #define BRG5 SPBRG_bits.BRG5
995 #define BRG6 SPBRG_bits.BRG6
996 #define BRG7 SPBRG_bits.BRG7
998 // ----- SPBRGH bits --------------------
1001 unsigned char BRG8:1;
1002 unsigned char BRG9:1;
1003 unsigned char BRG10:1;
1004 unsigned char BRG11:1;
1005 unsigned char BRG12:1;
1006 unsigned char BRG13:1;
1007 unsigned char BRG14:1;
1008 unsigned char BRG15:1;
1011 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1013 #define BRG8 SPBRGH_bits.BRG8
1014 #define BRG9 SPBRGH_bits.BRG9
1015 #define BRG10 SPBRGH_bits.BRG10
1016 #define BRG11 SPBRGH_bits.BRG11
1017 #define BRG12 SPBRGH_bits.BRG12
1018 #define BRG13 SPBRGH_bits.BRG13
1019 #define BRG14 SPBRGH_bits.BRG14
1020 #define BRG15 SPBRGH_bits.BRG15
1022 // ----- SRCON bits --------------------
1027 unsigned char PULSR:1;
1028 unsigned char PULSS:1;
1029 unsigned char C2REN:1;
1030 unsigned char C1SEN:1;
1031 unsigned char SR0:1;
1032 unsigned char SR1:1;
1035 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1037 #define PULSR SRCON_bits.PULSR
1038 #define PULSS SRCON_bits.PULSS
1039 #define C2REN SRCON_bits.C2REN
1040 #define C1SEN SRCON_bits.C1SEN
1041 #define SR0 SRCON_bits.SR0
1042 #define SR1 SRCON_bits.SR1
1044 // ----- SSPCON bits --------------------
1047 unsigned char SSPM0:1;
1048 unsigned char SSPM1:1;
1049 unsigned char SSPM2:1;
1050 unsigned char SSPM3:1;
1051 unsigned char CKP:1;
1052 unsigned char SSPEN:1;
1053 unsigned char SSPOV:1;
1054 unsigned char WCOL:1;
1057 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1059 #define SSPM0 SSPCON_bits.SSPM0
1060 #define SSPM1 SSPCON_bits.SSPM1
1061 #define SSPM2 SSPCON_bits.SSPM2
1062 #define SSPM3 SSPCON_bits.SSPM3
1063 #define CKP SSPCON_bits.CKP
1064 #define SSPEN SSPCON_bits.SSPEN
1065 #define SSPOV SSPCON_bits.SSPOV
1066 #define WCOL SSPCON_bits.WCOL
1068 // ----- SSPSTAT bits --------------------
1073 unsigned char R_W_NOT:1;
1076 unsigned char D_A_NOT:1;
1077 unsigned char CKE:1;
1078 unsigned char SMP:1;
1081 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1083 #define BF SSPSTAT_bits.BF
1084 #define UA SSPSTAT_bits.UA
1085 #define R_W_NOT SSPSTAT_bits.R_W_NOT
1086 #define S SSPSTAT_bits.S
1087 #define P SSPSTAT_bits.P
1088 #define D_A_NOT SSPSTAT_bits.D_A_NOT
1089 #define CKE SSPSTAT_bits.CKE
1090 #define SMP SSPSTAT_bits.SMP
1092 // ----- STATUS bits --------------------
1098 unsigned char NOT_PD:1;
1099 unsigned char NOT_TO:1;
1100 unsigned char RP0:1;
1101 unsigned char RP1:1;
1102 unsigned char IRP:1;
1105 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1107 #define C STATUS_bits.C
1108 #define DC STATUS_bits.DC
1109 #define Z STATUS_bits.Z
1110 #define NOT_PD STATUS_bits.NOT_PD
1111 #define NOT_TO STATUS_bits.NOT_TO
1112 #define RP0 STATUS_bits.RP0
1113 #define RP1 STATUS_bits.RP1
1114 #define IRP STATUS_bits.IRP
1116 // ----- T1CON bits --------------------
1119 unsigned char TMR1ON:1;
1120 unsigned char TMR1CS:1;
1121 unsigned char NOT_T1SYNC:1;
1122 unsigned char T1OSCEN:1;
1123 unsigned char T1CKPS0:1;
1124 unsigned char T1CKPS1:1;
1125 unsigned char TMR1GE:1;
1126 unsigned char T1GINV:1;
1129 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1131 #define TMR1ON T1CON_bits.TMR1ON
1132 #define TMR1CS T1CON_bits.TMR1CS
1133 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1134 #define T1OSCEN T1CON_bits.T1OSCEN
1135 #define T1CKPS0 T1CON_bits.T1CKPS0
1136 #define T1CKPS1 T1CON_bits.T1CKPS1
1137 #define TMR1GE T1CON_bits.TMR1GE
1138 #define T1GINV T1CON_bits.T1GINV
1140 // ----- TRISA bits --------------------
1143 unsigned char TRISA0:1;
1144 unsigned char TRISA1:1;
1145 unsigned char TRISA2:1;
1146 unsigned char TRISA3:1;
1147 unsigned char TRISA4:1;
1148 unsigned char TRISA5:1;
1153 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1155 #define TRISA0 TRISA_bits.TRISA0
1156 #define TRISA1 TRISA_bits.TRISA1
1157 #define TRISA2 TRISA_bits.TRISA2
1158 #define TRISA3 TRISA_bits.TRISA3
1159 #define TRISA4 TRISA_bits.TRISA4
1160 #define TRISA5 TRISA_bits.TRISA5
1162 // ----- TRISB bits --------------------
1169 unsigned char TRISB4:1;
1170 unsigned char TRISB5:1;
1171 unsigned char TRISB6:1;
1172 unsigned char TRISB7:1;
1175 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1177 #define TRISB4 TRISB_bits.TRISB4
1178 #define TRISB5 TRISB_bits.TRISB5
1179 #define TRISB6 TRISB_bits.TRISB6
1180 #define TRISB7 TRISB_bits.TRISB7
1182 // ----- TRISC bits --------------------
1185 unsigned char TRISC0:1;
1186 unsigned char TRISC1:1;
1187 unsigned char TRISC2:1;
1188 unsigned char TRISC3:1;
1189 unsigned char TRISC4:1;
1190 unsigned char TRISC5:1;
1191 unsigned char TRISC6:1;
1192 unsigned char TRISC7:1;
1195 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1197 #define TRISC0 TRISC_bits.TRISC0
1198 #define TRISC1 TRISC_bits.TRISC1
1199 #define TRISC2 TRISC_bits.TRISC2
1200 #define TRISC3 TRISC_bits.TRISC3
1201 #define TRISC4 TRISC_bits.TRISC4
1202 #define TRISC5 TRISC_bits.TRISC5
1203 #define TRISC6 TRISC_bits.TRISC6
1204 #define TRISC7 TRISC_bits.TRISC7
1206 // ----- TXSTA bits --------------------
1209 unsigned char TX9D:1;
1210 unsigned char TRMT:1;
1211 unsigned char BRGH:1;
1212 unsigned char SENB:1;
1213 unsigned char SYNC:1;
1214 unsigned char TXEN:1;
1215 unsigned char TX9:1;
1216 unsigned char CSRC:1;
1219 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1221 #define TX9D TXSTA_bits.TX9D
1222 #define TRMT TXSTA_bits.TRMT
1223 #define BRGH TXSTA_bits.BRGH
1224 #define SENB TXSTA_bits.SENB
1225 #define SYNC TXSTA_bits.SYNC
1226 #define TXEN TXSTA_bits.TXEN
1227 #define TX9 TXSTA_bits.TX9
1228 #define CSRC TXSTA_bits.CSRC
1230 // ----- VRCON bits --------------------
1233 unsigned char VR0:1;
1234 unsigned char VR1:1;
1235 unsigned char VR2:1;
1236 unsigned char VR3:1;
1237 unsigned char VP6EN:1;
1238 unsigned char VRR:1;
1239 unsigned char C2VREN:1;
1240 unsigned char C1VREN:1;
1243 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1245 #define VR0 VRCON_bits.VR0
1246 #define VR1 VRCON_bits.VR1
1247 #define VR2 VRCON_bits.VR2
1248 #define VR3 VRCON_bits.VR3
1249 #define VP6EN VRCON_bits.VP6EN
1250 #define VRR VRCON_bits.VRR
1251 #define C2VREN VRCON_bits.C2VREN
1252 #define C1VREN VRCON_bits.C1VREN
1254 // ----- WDTCON bits --------------------
1257 unsigned char SWDTEN:1;
1258 unsigned char WDTPS0:1;
1259 unsigned char WDTPS1:1;
1260 unsigned char WDTPS2:1;
1261 unsigned char WDTPS3:1;
1267 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1269 #define SWDTEN WDTCON_bits.SWDTEN
1270 #define WDTPS0 WDTCON_bits.WDTPS0
1271 #define WDTPS1 WDTCON_bits.WDTPS1
1272 #define WDTPS2 WDTCON_bits.WDTPS2
1273 #define WDTPS3 WDTCON_bits.WDTPS3
1275 // ----- WPUA bits --------------------
1278 unsigned char WPUA0:1;
1279 unsigned char WPUA1:1;
1280 unsigned char WPUA2:1;
1282 unsigned char WPUA4:1;
1283 unsigned char WPUA5:1;
1288 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1290 #define WPUA0 WPUA_bits.WPUA0
1291 #define WPUA1 WPUA_bits.WPUA1
1292 #define WPUA2 WPUA_bits.WPUA2
1293 #define WPUA4 WPUA_bits.WPUA4
1294 #define WPUA5 WPUA_bits.WPUA5
1296 // ----- WPUB bits --------------------
1303 unsigned char WPUB4:1;
1304 unsigned char WPUB5:1;
1305 unsigned char WPUB6:1;
1306 unsigned char WPUB7:1;
1309 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1311 #define WPUB4 WPUB_bits.WPUB4
1312 #define WPUB5 WPUB_bits.WPUB5
1313 #define WPUB6 WPUB_bits.WPUB6
1314 #define WPUB7 WPUB_bits.WPUB7