2 // Register Declarations for Microchip 16F688 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define BAUDCTL_ADDR 0x0011
42 #define SPBRGH_ADDR 0x0012
43 #define SPBRG_ADDR 0x0013
44 #define RCREG_ADDR 0x0014
45 #define TXREG_ADDR 0x0015
46 #define TXSTA_ADDR 0x0016
47 #define RCSTA_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define WPU_ADDR 0x0095
62 #define WPUA_ADDR 0x0095
63 #define IOC_ADDR 0x0096
64 #define IOCA_ADDR 0x0096
65 #define EEDATH_ADDR 0x0097
66 #define EEADRH_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
77 // Memory organization.
83 // P16F688.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
86 // This header file defines configurations, registers, and other useful bits of
87 // information for the PIC16F688 microcontroller. These names are taken to match
88 // the data sheets as closely as possible.
90 // Note that the processor must be selected before this file is
91 // included. The processor may be selected the following ways:
93 // 1. Command line switch:
94 // C:\ MPASM MYFILE.ASM /PIC16F688
95 // 2. LIST directive in the source file
97 // 3. Processor Type entry in the MPASM full-screen interface
99 //==========================================================================
103 //==========================================================================
104 //1.00 07/28/03 Original
105 //1.01 09/02/03 Modified to match datasheet
106 //1.02 09/19/03 Changed CMCON1 from 0x20 to 0x1A (pas)
107 //==========================================================================
111 //==========================================================================
114 // MESSG "Processor-header file mismatch. Verify selected processor."
117 //==========================================================================
119 // Register Definitions
121 //==========================================================================
126 //----- Register Files------------------------------------------------------
128 extern __data __at (INDF_ADDR) volatile char INDF;
129 extern __sfr __at (TMR0_ADDR) TMR0;
130 extern __data __at (PCL_ADDR) volatile char PCL;
131 extern __sfr __at (STATUS_ADDR) STATUS;
132 extern __sfr __at (FSR_ADDR) FSR;
133 extern __sfr __at (PORTA_ADDR) PORTA;
135 extern __sfr __at (PORTC_ADDR) PORTC;
137 extern __sfr __at (PCLATH_ADDR) PCLATH;
138 extern __sfr __at (INTCON_ADDR) INTCON;
139 extern __sfr __at (PIR1_ADDR) PIR1;
141 extern __sfr __at (TMR1L_ADDR) TMR1L;
142 extern __sfr __at (TMR1H_ADDR) TMR1H;
143 extern __sfr __at (T1CON_ADDR) T1CON;
144 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
145 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
146 extern __sfr __at (SPBRG_ADDR) SPBRG;
147 extern __sfr __at (RCREG_ADDR) RCREG;
148 extern __sfr __at (TXREG_ADDR) TXREG;
149 extern __sfr __at (TXSTA_ADDR) TXSTA;
150 extern __sfr __at (RCSTA_ADDR) RCSTA;
151 extern __sfr __at (WDTCON_ADDR) WDTCON;
152 extern __sfr __at (CMCON0_ADDR) CMCON0;
153 extern __sfr __at (CMCON1_ADDR) CMCON1;
155 extern __sfr __at (ADRESH_ADDR) ADRESH;
156 extern __sfr __at (ADCON0_ADDR) ADCON0;
159 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
161 extern __sfr __at (TRISA_ADDR) TRISA;
162 extern __sfr __at (TRISC_ADDR) TRISC;
164 extern __sfr __at (PIE1_ADDR) PIE1;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (OSCCON_ADDR) OSCCON;
168 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
169 extern __sfr __at (ANSEL_ADDR) ANSEL;
171 extern __sfr __at (WPU_ADDR) WPU;
172 extern __sfr __at (WPUA_ADDR) WPUA;
173 extern __sfr __at (IOC_ADDR) IOC;
174 extern __sfr __at (IOCA_ADDR) IOCA;
175 extern __sfr __at (EEDATH_ADDR) EEDATH;
176 extern __sfr __at (EEADRH_ADDR) EEADRH;
177 extern __sfr __at (VRCON_ADDR) VRCON;
178 extern __sfr __at (EEDAT_ADDR) EEDAT;
179 extern __sfr __at (EEDATA_ADDR) EEDATA;
180 extern __sfr __at (EEADR_ADDR) EEADR;
181 extern __sfr __at (EECON1_ADDR) EECON1;
182 extern __sfr __at (EECON2_ADDR) EECON2;
183 extern __sfr __at (ADRESL_ADDR) ADRESL;
184 extern __sfr __at (ADCON1_ADDR) ADCON1;
187 //----- STATUS Bits --------------------------------------------------------
190 //----- INTCON Bits --------------------------------------------------------
193 //----- PIR1 Bits ----------------------------------------------------------
196 //----- T1CON Bits ---------------------------------------------------------
199 //----- BAUDCTL Bits --------------------------------------------------------
202 //----- TXSTA Bits --------------------------------------------------------
205 //----- RCSTA Bits --------------------------------------------------------
207 //----- WDTCON Bits --------------------------------------------------------
210 //----- CMCON0 Bits -------------------------------------------------------
213 //----- CMCON1 Bits -------------------------------------------------------
216 //----- ADCON0 Bits --------------------------------------------------------
219 //----- OPTION Bits --------------------------------------------------------
222 //----- PIE1 Bits ----------------------------------------------------------
225 //----- PCON Bits ----------------------------------------------------------
228 //----- OSCCON Bits --------------------------------------------------------
231 //----- OSCTUNE Bits -------------------------------------------------------
234 //----- ANSEL --------------------------------------------------------------
237 //----- IOC --------------------------------------------------------------
240 //----- IOCA --------------------------------------------------------------
243 //----- VRCON Bits ---------------------------------------------------------
246 //----- EECON1 -------------------------------------------------------------
249 //----- ADCON1 -------------------------------------------------------------
252 //==========================================================================
256 //==========================================================================
259 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
260 // __BADRAM H'86', H'88'-H'89', H'8D', H'92'-H'94'
261 // __BADRAM H'106', H'108'-H'109', H'10C'-H'11F'
262 // __BADRAM H'186', H'188'-H'189', H'18C'-H'18D', H'190'-H'1EF'
264 //==========================================================================
266 // Configuration Bits
268 //==========================================================================
270 #define _FCMEN_ON 0x3FFF
271 #define _FCMEN_OFF 0x37FF
272 #define _IESO_ON 0x3FFF
273 #define _IESO_OFF 0x3BFF
274 #define _BOD_ON 0x3FFF
275 #define _BOD_NSLEEP 0x3EFF
276 #define _BOD_SBODEN 0x3DFF
277 #define _BOD_OFF 0x3CFF
278 #define _CPD_ON 0x3F7F
279 #define _CPD_OFF 0x3FFF
280 #define _CP_ON 0x3FBF
281 #define _CP_OFF 0x3FFF
282 #define _MCLRE_ON 0x3FFF
283 #define _MCLRE_OFF 0x3FDF
284 #define _PWRTE_OFF 0x3FFF
285 #define _PWRTE_ON 0x3FEF
286 #define _WDT_ON 0x3FFF
287 #define _WDT_OFF 0x3FF7
288 #define _LP_OSC 0x3FF8
289 #define _XT_OSC 0x3FF9
290 #define _HS_OSC 0x3FFA
291 #define _EC_OSC 0x3FFB
292 #define _INTRC_OSC_NOCLKOUT 0x3FFC
293 #define _INTRC_OSC_CLKOUT 0x3FFD
294 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
295 #define _EXTRC_OSC_CLKOUT 0x3FFF
296 #define _INTOSCIO 0x3FFC
297 #define _INTOSC 0x3FFD
298 #define _EXTRCIO 0x3FFE
299 #define _EXTRC 0x3FFF
303 // ----- ADCON0 bits --------------------
306 unsigned char ADON:1;
308 unsigned char CHS0:1;
309 unsigned char CHS1:1;
310 unsigned char CHS2:1;
312 unsigned char VCFG:1;
313 unsigned char ADFM:1;
317 unsigned char NOT_DONE:1;
327 unsigned char GO_DONE:1;
336 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
338 #define ADON ADCON0_bits.ADON
339 #define GO ADCON0_bits.GO
340 #define NOT_DONE ADCON0_bits.NOT_DONE
341 #define GO_DONE ADCON0_bits.GO_DONE
342 #define CHS0 ADCON0_bits.CHS0
343 #define CHS1 ADCON0_bits.CHS1
344 #define CHS2 ADCON0_bits.CHS2
345 #define VCFG ADCON0_bits.VCFG
346 #define ADFM ADCON0_bits.ADFM
348 // ----- BAUDCTL bits --------------------
351 unsigned char ABDEN:1;
354 unsigned char BRG16:1;
355 unsigned char SCKP:1;
357 unsigned char RCIDL:1;
358 unsigned char ABDOVF:1;
361 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
363 #define ABDEN BAUDCTL_bits.ABDEN
364 #define WUE BAUDCTL_bits.WUE
365 #define BRG16 BAUDCTL_bits.BRG16
366 #define SCKP BAUDCTL_bits.SCKP
367 #define RCIDL BAUDCTL_bits.RCIDL
368 #define ABDOVF BAUDCTL_bits.ABDOVF
370 // ----- CMCON0 bits --------------------
377 unsigned char C1INV:1;
378 unsigned char C2INV:1;
379 unsigned char C1OUT:1;
380 unsigned char C2OUT:1;
383 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
385 #define CM0 CMCON0_bits.CM0
386 #define CM1 CMCON0_bits.CM1
387 #define CM2 CMCON0_bits.CM2
388 #define CIS CMCON0_bits.CIS
389 #define C1INV CMCON0_bits.C1INV
390 #define C2INV CMCON0_bits.C2INV
391 #define C1OUT CMCON0_bits.C1OUT
392 #define C2OUT CMCON0_bits.C2OUT
394 // ----- CMCON1 bits --------------------
397 unsigned char C2SYNC:1;
398 unsigned char T1GSS:1;
407 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
409 #define C2SYNC CMCON1_bits.C2SYNC
410 #define T1GSS CMCON1_bits.T1GSS
412 // ----- INTCON bits --------------------
415 unsigned char RAIF:1;
416 unsigned char INTF:1;
417 unsigned char T0IF:1;
418 unsigned char RAIE:1;
419 unsigned char INTE:1;
420 unsigned char T0IE:1;
421 unsigned char PEIE:1;
425 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
427 #define RAIF INTCON_bits.RAIF
428 #define INTF INTCON_bits.INTF
429 #define T0IF INTCON_bits.T0IF
430 #define RAIE INTCON_bits.RAIE
431 #define INTE INTCON_bits.INTE
432 #define T0IE INTCON_bits.T0IE
433 #define PEIE INTCON_bits.PEIE
434 #define GIE INTCON_bits.GIE
436 // ----- OPTION_REG bits --------------------
443 unsigned char T0SE:1;
444 unsigned char T0CS:1;
445 unsigned char INTEDG:1;
446 unsigned char NOT_RAPU:1;
448 } __OPTION_REG_bits_t;
449 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
451 #define PS0 OPTION_REG_bits.PS0
452 #define PS1 OPTION_REG_bits.PS1
453 #define PS2 OPTION_REG_bits.PS2
454 #define PSA OPTION_REG_bits.PSA
455 #define T0SE OPTION_REG_bits.T0SE
456 #define T0CS OPTION_REG_bits.T0CS
457 #define INTEDG OPTION_REG_bits.INTEDG
458 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
460 // ----- OSCCON bits --------------------
466 unsigned char OSTS:1;
467 unsigned char IRCF0:1;
468 unsigned char IRCF1:1;
469 unsigned char IRCF2:1;
473 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
475 #define SCS OSCCON_bits.SCS
476 #define LTS OSCCON_bits.LTS
477 #define HTS OSCCON_bits.HTS
478 #define OSTS OSCCON_bits.OSTS
479 #define IRCF0 OSCCON_bits.IRCF0
480 #define IRCF1 OSCCON_bits.IRCF1
481 #define IRCF2 OSCCON_bits.IRCF2
483 // ----- OSCTUNE bits --------------------
486 unsigned char TUN0:1;
487 unsigned char TUN1:1;
488 unsigned char TUN2:1;
489 unsigned char TUN3:1;
490 unsigned char TUN4:1;
491 unsigned char ANS5:1;
492 unsigned char ANS6:1;
493 unsigned char ANS7:1;
496 unsigned char ANS0:1;
497 unsigned char ANS1:1;
498 unsigned char ANS2:1;
499 unsigned char ANS3:1;
500 unsigned char ANS4:1;
501 unsigned char IOC5:1;
506 unsigned char IOC0:1;
507 unsigned char IOC1:1;
508 unsigned char IOC2:1;
509 unsigned char IOC3:1;
510 unsigned char IOC4:1;
511 unsigned char IOCA5:1;
516 unsigned char IOCA0:1;
517 unsigned char IOCA1:1;
518 unsigned char IOCA2:1;
519 unsigned char IOCA3:1;
520 unsigned char IOCA4:1;
526 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
528 #define TUN0 OSCTUNE_bits.TUN0
529 #define ANS0 OSCTUNE_bits.ANS0
530 #define IOC0 OSCTUNE_bits.IOC0
531 #define IOCA0 OSCTUNE_bits.IOCA0
532 #define TUN1 OSCTUNE_bits.TUN1
533 #define ANS1 OSCTUNE_bits.ANS1
534 #define IOC1 OSCTUNE_bits.IOC1
535 #define IOCA1 OSCTUNE_bits.IOCA1
536 #define TUN2 OSCTUNE_bits.TUN2
537 #define ANS2 OSCTUNE_bits.ANS2
538 #define IOC2 OSCTUNE_bits.IOC2
539 #define IOCA2 OSCTUNE_bits.IOCA2
540 #define TUN3 OSCTUNE_bits.TUN3
541 #define ANS3 OSCTUNE_bits.ANS3
542 #define IOC3 OSCTUNE_bits.IOC3
543 #define IOCA3 OSCTUNE_bits.IOCA3
544 #define TUN4 OSCTUNE_bits.TUN4
545 #define ANS4 OSCTUNE_bits.ANS4
546 #define IOC4 OSCTUNE_bits.IOC4
547 #define IOCA4 OSCTUNE_bits.IOCA4
548 #define ANS5 OSCTUNE_bits.ANS5
549 #define IOC5 OSCTUNE_bits.IOC5
550 #define IOCA5 OSCTUNE_bits.IOCA5
551 #define ANS6 OSCTUNE_bits.ANS6
552 #define ANS7 OSCTUNE_bits.ANS7
554 // ----- PCON bits --------------------
557 unsigned char NOT_BOD:1;
558 unsigned char NOT_POR:1;
561 unsigned char SBODEN:1;
562 unsigned char ULPWUE:1;
567 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
569 #define NOT_BOD PCON_bits.NOT_BOD
570 #define NOT_POR PCON_bits.NOT_POR
571 #define SBODEN PCON_bits.SBODEN
572 #define ULPWUE PCON_bits.ULPWUE
574 // ----- PIE1 bits --------------------
577 unsigned char T1IE:1;
578 unsigned char TXIE:1;
579 unsigned char OSFIE:1;
580 unsigned char C1IE:1;
581 unsigned char C2IE:1;
582 unsigned char RCIE:1;
583 unsigned char ADIE:1;
584 unsigned char EEIE:1;
587 unsigned char TMR1IE:1;
597 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
599 #define T1IE PIE1_bits.T1IE
600 #define TMR1IE PIE1_bits.TMR1IE
601 #define TXIE PIE1_bits.TXIE
602 #define OSFIE PIE1_bits.OSFIE
603 #define C1IE PIE1_bits.C1IE
604 #define C2IE PIE1_bits.C2IE
605 #define RCIE PIE1_bits.RCIE
606 #define ADIE PIE1_bits.ADIE
607 #define EEIE PIE1_bits.EEIE
609 // ----- PIR1 bits --------------------
612 unsigned char T1IF:1;
613 unsigned char TXIF:1;
614 unsigned char OSFIF:1;
615 unsigned char C1IF:1;
616 unsigned char C2IF:1;
617 unsigned char RCIF:1;
618 unsigned char ADIF:1;
619 unsigned char EEIF:1;
622 unsigned char TMR1IF:1;
632 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
634 #define T1IF PIR1_bits.T1IF
635 #define TMR1IF PIR1_bits.TMR1IF
636 #define TXIF PIR1_bits.TXIF
637 #define OSFIF PIR1_bits.OSFIF
638 #define C1IF PIR1_bits.C1IF
639 #define C2IF PIR1_bits.C2IF
640 #define RCIF PIR1_bits.RCIF
641 #define ADIF PIR1_bits.ADIF
642 #define EEIF PIR1_bits.EEIF
644 // ----- RCSTA bits --------------------
647 unsigned char RX9D:1;
648 unsigned char OERR:1;
649 unsigned char FERR:1;
650 unsigned char ADDEN:1;
651 unsigned char CREN:1;
652 unsigned char SREN:1;
654 unsigned char SPEN:1;
657 unsigned char SWDTEN:1;
658 unsigned char WDTPS0:1;
659 unsigned char WDTPS1:1;
660 unsigned char WDTPS2:1;
661 unsigned char WDTPS3:1;
667 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
669 #define RX9D RCSTA_bits.RX9D
670 #define SWDTEN RCSTA_bits.SWDTEN
671 #define OERR RCSTA_bits.OERR
672 #define WDTPS0 RCSTA_bits.WDTPS0
673 #define FERR RCSTA_bits.FERR
674 #define WDTPS1 RCSTA_bits.WDTPS1
675 #define ADDEN RCSTA_bits.ADDEN
676 #define WDTPS2 RCSTA_bits.WDTPS2
677 #define CREN RCSTA_bits.CREN
678 #define WDTPS3 RCSTA_bits.WDTPS3
679 #define SREN RCSTA_bits.SREN
680 #define RX9 RCSTA_bits.RX9
681 #define SPEN RCSTA_bits.SPEN
683 // ----- STATUS bits --------------------
689 unsigned char NOT_PD:1;
690 unsigned char NOT_TO:1;
696 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
698 #define C STATUS_bits.C
699 #define DC STATUS_bits.DC
700 #define Z STATUS_bits.Z
701 #define NOT_PD STATUS_bits.NOT_PD
702 #define NOT_TO STATUS_bits.NOT_TO
703 #define RP0 STATUS_bits.RP0
704 #define RP1 STATUS_bits.RP1
705 #define IRP STATUS_bits.IRP
707 // ----- T1CON bits --------------------
710 unsigned char TMR1ON:1;
711 unsigned char TMR1CS:1;
712 unsigned char NOT_T1SYNC:1;
713 unsigned char T1OSCEN:1;
714 unsigned char T1CKPS0:1;
715 unsigned char T1CKPS1:1;
716 unsigned char TMR1GE:1;
717 unsigned char T1GINV:1;
720 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
722 #define TMR1ON T1CON_bits.TMR1ON
723 #define TMR1CS T1CON_bits.TMR1CS
724 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
725 #define T1OSCEN T1CON_bits.T1OSCEN
726 #define T1CKPS0 T1CON_bits.T1CKPS0
727 #define T1CKPS1 T1CON_bits.T1CKPS1
728 #define TMR1GE T1CON_bits.TMR1GE
729 #define T1GINV T1CON_bits.T1GINV
731 // ----- TXSTA bits --------------------
734 unsigned char TX9D:1;
735 unsigned char TRMT:1;
736 unsigned char BRGH:1;
737 unsigned char SENDB:1;
738 unsigned char SYNC:1;
739 unsigned char TXEN:1;
741 unsigned char CSRC:1;
744 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
746 #define TX9D TXSTA_bits.TX9D
747 #define TRMT TXSTA_bits.TRMT
748 #define BRGH TXSTA_bits.BRGH
749 #define SENDB TXSTA_bits.SENDB
750 #define SYNC TXSTA_bits.SYNC
751 #define TXEN TXSTA_bits.TXEN
752 #define TX9 TXSTA_bits.TX9
753 #define CSRC TXSTA_bits.CSRC
755 // ----- VRCON bits --------------------
762 unsigned char ADCS0:1;
764 unsigned char ADCS2:1;
765 unsigned char VREN:1;
770 unsigned char WREN:1;
771 unsigned char WRERR:1;
773 unsigned char ADCS1:1;
775 unsigned char EEPGD:1;
778 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
780 #define VR0 VRCON_bits.VR0
781 #define RD VRCON_bits.RD
782 #define VR1 VRCON_bits.VR1
783 #define WR VRCON_bits.WR
784 #define VR2 VRCON_bits.VR2
785 #define WREN VRCON_bits.WREN
786 #define VR3 VRCON_bits.VR3
787 #define WRERR VRCON_bits.WRERR
788 #define ADCS0 VRCON_bits.ADCS0
789 #define VRR VRCON_bits.VRR
790 #define ADCS1 VRCON_bits.ADCS1
791 #define ADCS2 VRCON_bits.ADCS2
792 #define VREN VRCON_bits.VREN
793 #define EEPGD VRCON_bits.EEPGD