2 // Register Declarations for Microchip 16F688 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define BAUDCTL_ADDR 0x0011
42 #define SPBRGH_ADDR 0x0012
43 #define SPBRG_ADDR 0x0013
44 #define RCREG_ADDR 0x0014
45 #define TXREG_ADDR 0x0015
46 #define TXSTA_ADDR 0x0016
47 #define RCSTA_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define WPU_ADDR 0x0095
62 #define WPUA_ADDR 0x0095
63 #define IOC_ADDR 0x0096
64 #define IOCA_ADDR 0x0096
65 #define EEDATH_ADDR 0x0097
66 #define EEADRH_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
77 // Memory organization.
80 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
81 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
82 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
83 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
84 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
85 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
86 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
87 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
88 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
89 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
90 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
91 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
92 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
93 #pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL
94 #pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH
95 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
96 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
97 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
98 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
99 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
100 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
101 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
102 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
103 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
104 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
105 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
106 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
107 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
108 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
109 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
110 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
111 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
112 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
113 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
114 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
115 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
116 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
117 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
118 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
119 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
120 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
121 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
122 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
123 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
124 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
125 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
126 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
130 // P16F688.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
133 // This header file defines configurations, registers, and other useful bits of
134 // information for the PIC16F688 microcontroller. These names are taken to match
135 // the data sheets as closely as possible.
137 // Note that the processor must be selected before this file is
138 // included. The processor may be selected the following ways:
140 // 1. Command line switch:
141 // C:\ MPASM MYFILE.ASM /PIC16F688
142 // 2. LIST directive in the source file
144 // 3. Processor Type entry in the MPASM full-screen interface
146 //==========================================================================
150 //==========================================================================
151 //1.00 07/28/03 Original
152 //1.01 09/02/03 Modified to match datasheet
153 //1.02 09/19/03 Changed CMCON1 from 0x20 to 0x1A (pas)
154 //==========================================================================
158 //==========================================================================
161 // MESSG "Processor-header file mismatch. Verify selected processor."
164 //==========================================================================
166 // Register Definitions
168 //==========================================================================
173 //----- Register Files------------------------------------------------------
175 extern __data __at (INDF_ADDR) volatile char INDF;
176 extern __sfr __at (TMR0_ADDR) TMR0;
177 extern __data __at (PCL_ADDR) volatile char PCL;
178 extern __sfr __at (STATUS_ADDR) STATUS;
179 extern __sfr __at (FSR_ADDR) FSR;
180 extern __sfr __at (PORTA_ADDR) PORTA;
182 extern __sfr __at (PORTC_ADDR) PORTC;
184 extern __sfr __at (PCLATH_ADDR) PCLATH;
185 extern __sfr __at (INTCON_ADDR) INTCON;
186 extern __sfr __at (PIR1_ADDR) PIR1;
188 extern __sfr __at (TMR1L_ADDR) TMR1L;
189 extern __sfr __at (TMR1H_ADDR) TMR1H;
190 extern __sfr __at (T1CON_ADDR) T1CON;
191 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
192 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
193 extern __sfr __at (SPBRG_ADDR) SPBRG;
194 extern __sfr __at (RCREG_ADDR) RCREG;
195 extern __sfr __at (TXREG_ADDR) TXREG;
196 extern __sfr __at (TXSTA_ADDR) TXSTA;
197 extern __sfr __at (RCSTA_ADDR) RCSTA;
198 extern __sfr __at (WDTCON_ADDR) WDTCON;
199 extern __sfr __at (CMCON0_ADDR) CMCON0;
200 extern __sfr __at (CMCON1_ADDR) CMCON1;
202 extern __sfr __at (ADRESH_ADDR) ADRESH;
203 extern __sfr __at (ADCON0_ADDR) ADCON0;
206 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
208 extern __sfr __at (TRISA_ADDR) TRISA;
209 extern __sfr __at (TRISC_ADDR) TRISC;
211 extern __sfr __at (PIE1_ADDR) PIE1;
213 extern __sfr __at (PCON_ADDR) PCON;
214 extern __sfr __at (OSCCON_ADDR) OSCCON;
215 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
216 extern __sfr __at (ANSEL_ADDR) ANSEL;
218 extern __sfr __at (WPU_ADDR) WPU;
219 extern __sfr __at (WPUA_ADDR) WPUA;
220 extern __sfr __at (IOC_ADDR) IOC;
221 extern __sfr __at (IOCA_ADDR) IOCA;
222 extern __sfr __at (EEDATH_ADDR) EEDATH;
223 extern __sfr __at (EEADRH_ADDR) EEADRH;
224 extern __sfr __at (VRCON_ADDR) VRCON;
225 extern __sfr __at (EEDAT_ADDR) EEDAT;
226 extern __sfr __at (EEDATA_ADDR) EEDATA;
227 extern __sfr __at (EEADR_ADDR) EEADR;
228 extern __sfr __at (EECON1_ADDR) EECON1;
229 extern __sfr __at (EECON2_ADDR) EECON2;
230 extern __sfr __at (ADRESL_ADDR) ADRESL;
231 extern __sfr __at (ADCON1_ADDR) ADCON1;
234 //----- STATUS Bits --------------------------------------------------------
237 //----- INTCON Bits --------------------------------------------------------
240 //----- PIR1 Bits ----------------------------------------------------------
243 //----- T1CON Bits ---------------------------------------------------------
246 //----- BAUDCTL Bits --------------------------------------------------------
249 //----- TXSTA Bits --------------------------------------------------------
252 //----- RCSTA Bits --------------------------------------------------------
254 //----- WDTCON Bits --------------------------------------------------------
257 //----- CMCON0 Bits -------------------------------------------------------
260 //----- CMCON1 Bits -------------------------------------------------------
263 //----- ADCON0 Bits --------------------------------------------------------
266 //----- OPTION Bits --------------------------------------------------------
269 //----- PIE1 Bits ----------------------------------------------------------
272 //----- PCON Bits ----------------------------------------------------------
275 //----- OSCCON Bits --------------------------------------------------------
278 //----- OSCTUNE Bits -------------------------------------------------------
281 //----- ANSEL --------------------------------------------------------------
284 //----- IOC --------------------------------------------------------------
287 //----- IOCA --------------------------------------------------------------
290 //----- VRCON Bits ---------------------------------------------------------
293 //----- EECON1 -------------------------------------------------------------
296 //----- ADCON1 -------------------------------------------------------------
299 //==========================================================================
303 //==========================================================================
306 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
307 // __BADRAM H'86', H'88'-H'89', H'8D', H'92'-H'94'
308 // __BADRAM H'106', H'108'-H'109', H'10C'-H'11F'
309 // __BADRAM H'186', H'188'-H'189', H'18C'-H'18D', H'190'-H'1EF'
311 //==========================================================================
313 // Configuration Bits
315 //==========================================================================
317 #define _FCMEN_ON 0x3FFF
318 #define _FCMEN_OFF 0x37FF
319 #define _IESO_ON 0x3FFF
320 #define _IESO_OFF 0x3BFF
321 #define _BOD_ON 0x3FFF
322 #define _BOD_NSLEEP 0x3EFF
323 #define _BOD_SBODEN 0x3DFF
324 #define _BOD_OFF 0x3CFF
325 #define _CPD_ON 0x3F7F
326 #define _CPD_OFF 0x3FFF
327 #define _CP_ON 0x3FBF
328 #define _CP_OFF 0x3FFF
329 #define _MCLRE_ON 0x3FFF
330 #define _MCLRE_OFF 0x3FDF
331 #define _PWRTE_OFF 0x3FFF
332 #define _PWRTE_ON 0x3FEF
333 #define _WDT_ON 0x3FFF
334 #define _WDT_OFF 0x3FF7
335 #define _LP_OSC 0x3FF8
336 #define _XT_OSC 0x3FF9
337 #define _HS_OSC 0x3FFA
338 #define _EC_OSC 0x3FFB
339 #define _INTRC_OSC_NOCLKOUT 0x3FFC
340 #define _INTRC_OSC_CLKOUT 0x3FFD
341 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
342 #define _EXTRC_OSC_CLKOUT 0x3FFF
343 #define _INTOSCIO 0x3FFC
344 #define _INTOSC 0x3FFD
345 #define _EXTRCIO 0x3FFE
346 #define _EXTRC 0x3FFF
350 // ----- ADCON0 bits --------------------
353 unsigned char ADON:1;
355 unsigned char CHS0:1;
356 unsigned char CHS1:1;
357 unsigned char CHS2:1;
359 unsigned char VCFG:1;
360 unsigned char ADFM:1;
364 unsigned char NOT_DONE:1;
374 unsigned char GO_DONE:1;
383 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
385 #define ADON ADCON0_bits.ADON
386 #define GO ADCON0_bits.GO
387 #define NOT_DONE ADCON0_bits.NOT_DONE
388 #define GO_DONE ADCON0_bits.GO_DONE
389 #define CHS0 ADCON0_bits.CHS0
390 #define CHS1 ADCON0_bits.CHS1
391 #define CHS2 ADCON0_bits.CHS2
392 #define VCFG ADCON0_bits.VCFG
393 #define ADFM ADCON0_bits.ADFM
395 // ----- BAUDCTL bits --------------------
398 unsigned char ABDEN:1;
401 unsigned char BRG16:1;
402 unsigned char SCKP:1;
404 unsigned char RCIDL:1;
405 unsigned char ABDOVF:1;
408 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
410 #define ABDEN BAUDCTL_bits.ABDEN
411 #define WUE BAUDCTL_bits.WUE
412 #define BRG16 BAUDCTL_bits.BRG16
413 #define SCKP BAUDCTL_bits.SCKP
414 #define RCIDL BAUDCTL_bits.RCIDL
415 #define ABDOVF BAUDCTL_bits.ABDOVF
417 // ----- CMCON0 bits --------------------
424 unsigned char C1INV:1;
425 unsigned char C2INV:1;
426 unsigned char C1OUT:1;
427 unsigned char C2OUT:1;
430 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
432 #define CM0 CMCON0_bits.CM0
433 #define CM1 CMCON0_bits.CM1
434 #define CM2 CMCON0_bits.CM2
435 #define CIS CMCON0_bits.CIS
436 #define C1INV CMCON0_bits.C1INV
437 #define C2INV CMCON0_bits.C2INV
438 #define C1OUT CMCON0_bits.C1OUT
439 #define C2OUT CMCON0_bits.C2OUT
441 // ----- CMCON1 bits --------------------
444 unsigned char C2SYNC:1;
445 unsigned char T1GSS:1;
454 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
456 #define C2SYNC CMCON1_bits.C2SYNC
457 #define T1GSS CMCON1_bits.T1GSS
459 // ----- INTCON bits --------------------
462 unsigned char RAIF:1;
463 unsigned char INTF:1;
464 unsigned char T0IF:1;
465 unsigned char RAIE:1;
466 unsigned char INTE:1;
467 unsigned char T0IE:1;
468 unsigned char PEIE:1;
472 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
474 #define RAIF INTCON_bits.RAIF
475 #define INTF INTCON_bits.INTF
476 #define T0IF INTCON_bits.T0IF
477 #define RAIE INTCON_bits.RAIE
478 #define INTE INTCON_bits.INTE
479 #define T0IE INTCON_bits.T0IE
480 #define PEIE INTCON_bits.PEIE
481 #define GIE INTCON_bits.GIE
483 // ----- OPTION_REG bits --------------------
490 unsigned char T0SE:1;
491 unsigned char T0CS:1;
492 unsigned char INTEDG:1;
493 unsigned char NOT_RAPU:1;
495 } __OPTION_REG_bits_t;
496 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
498 #define PS0 OPTION_REG_bits.PS0
499 #define PS1 OPTION_REG_bits.PS1
500 #define PS2 OPTION_REG_bits.PS2
501 #define PSA OPTION_REG_bits.PSA
502 #define T0SE OPTION_REG_bits.T0SE
503 #define T0CS OPTION_REG_bits.T0CS
504 #define INTEDG OPTION_REG_bits.INTEDG
505 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
507 // ----- OSCCON bits --------------------
513 unsigned char OSTS:1;
514 unsigned char IRCF0:1;
515 unsigned char IRCF1:1;
516 unsigned char IRCF2:1;
520 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
522 #define SCS OSCCON_bits.SCS
523 #define LTS OSCCON_bits.LTS
524 #define HTS OSCCON_bits.HTS
525 #define OSTS OSCCON_bits.OSTS
526 #define IRCF0 OSCCON_bits.IRCF0
527 #define IRCF1 OSCCON_bits.IRCF1
528 #define IRCF2 OSCCON_bits.IRCF2
530 // ----- OSCTUNE bits --------------------
533 unsigned char TUN0:1;
534 unsigned char TUN1:1;
535 unsigned char TUN2:1;
536 unsigned char TUN3:1;
537 unsigned char TUN4:1;
538 unsigned char ANS5:1;
539 unsigned char ANS6:1;
540 unsigned char ANS7:1;
543 unsigned char ANS0:1;
544 unsigned char ANS1:1;
545 unsigned char ANS2:1;
546 unsigned char ANS3:1;
547 unsigned char ANS4:1;
548 unsigned char IOC5:1;
553 unsigned char IOC0:1;
554 unsigned char IOC1:1;
555 unsigned char IOC2:1;
556 unsigned char IOC3:1;
557 unsigned char IOC4:1;
558 unsigned char IOCA5:1;
563 unsigned char IOCA0:1;
564 unsigned char IOCA1:1;
565 unsigned char IOCA2:1;
566 unsigned char IOCA3:1;
567 unsigned char IOCA4:1;
573 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
575 #define TUN0 OSCTUNE_bits.TUN0
576 #define ANS0 OSCTUNE_bits.ANS0
577 #define IOC0 OSCTUNE_bits.IOC0
578 #define IOCA0 OSCTUNE_bits.IOCA0
579 #define TUN1 OSCTUNE_bits.TUN1
580 #define ANS1 OSCTUNE_bits.ANS1
581 #define IOC1 OSCTUNE_bits.IOC1
582 #define IOCA1 OSCTUNE_bits.IOCA1
583 #define TUN2 OSCTUNE_bits.TUN2
584 #define ANS2 OSCTUNE_bits.ANS2
585 #define IOC2 OSCTUNE_bits.IOC2
586 #define IOCA2 OSCTUNE_bits.IOCA2
587 #define TUN3 OSCTUNE_bits.TUN3
588 #define ANS3 OSCTUNE_bits.ANS3
589 #define IOC3 OSCTUNE_bits.IOC3
590 #define IOCA3 OSCTUNE_bits.IOCA3
591 #define TUN4 OSCTUNE_bits.TUN4
592 #define ANS4 OSCTUNE_bits.ANS4
593 #define IOC4 OSCTUNE_bits.IOC4
594 #define IOCA4 OSCTUNE_bits.IOCA4
595 #define ANS5 OSCTUNE_bits.ANS5
596 #define IOC5 OSCTUNE_bits.IOC5
597 #define IOCA5 OSCTUNE_bits.IOCA5
598 #define ANS6 OSCTUNE_bits.ANS6
599 #define ANS7 OSCTUNE_bits.ANS7
601 // ----- PCON bits --------------------
604 unsigned char NOT_BOD:1;
605 unsigned char NOT_POR:1;
608 unsigned char SBODEN:1;
609 unsigned char ULPWUE:1;
614 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
616 #define NOT_BOD PCON_bits.NOT_BOD
617 #define NOT_POR PCON_bits.NOT_POR
618 #define SBODEN PCON_bits.SBODEN
619 #define ULPWUE PCON_bits.ULPWUE
621 // ----- PIE1 bits --------------------
624 unsigned char T1IE:1;
625 unsigned char TXIE:1;
626 unsigned char OSFIE:1;
627 unsigned char C1IE:1;
628 unsigned char C2IE:1;
629 unsigned char RCIE:1;
630 unsigned char ADIE:1;
631 unsigned char EEIE:1;
634 unsigned char TMR1IE:1;
644 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
646 #define T1IE PIE1_bits.T1IE
647 #define TMR1IE PIE1_bits.TMR1IE
648 #define TXIE PIE1_bits.TXIE
649 #define OSFIE PIE1_bits.OSFIE
650 #define C1IE PIE1_bits.C1IE
651 #define C2IE PIE1_bits.C2IE
652 #define RCIE PIE1_bits.RCIE
653 #define ADIE PIE1_bits.ADIE
654 #define EEIE PIE1_bits.EEIE
656 // ----- PIR1 bits --------------------
659 unsigned char T1IF:1;
660 unsigned char TXIF:1;
661 unsigned char OSFIF:1;
662 unsigned char C1IF:1;
663 unsigned char C2IF:1;
664 unsigned char RCIF:1;
665 unsigned char ADIF:1;
666 unsigned char EEIF:1;
669 unsigned char TMR1IF:1;
679 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
681 #define T1IF PIR1_bits.T1IF
682 #define TMR1IF PIR1_bits.TMR1IF
683 #define TXIF PIR1_bits.TXIF
684 #define OSFIF PIR1_bits.OSFIF
685 #define C1IF PIR1_bits.C1IF
686 #define C2IF PIR1_bits.C2IF
687 #define RCIF PIR1_bits.RCIF
688 #define ADIF PIR1_bits.ADIF
689 #define EEIF PIR1_bits.EEIF
691 // ----- RCSTA bits --------------------
694 unsigned char RX9D:1;
695 unsigned char OERR:1;
696 unsigned char FERR:1;
697 unsigned char ADDEN:1;
698 unsigned char CREN:1;
699 unsigned char SREN:1;
701 unsigned char SPEN:1;
704 unsigned char SWDTEN:1;
705 unsigned char WDTPS0:1;
706 unsigned char WDTPS1:1;
707 unsigned char WDTPS2:1;
708 unsigned char WDTPS3:1;
714 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
716 #define RX9D RCSTA_bits.RX9D
717 #define SWDTEN RCSTA_bits.SWDTEN
718 #define OERR RCSTA_bits.OERR
719 #define WDTPS0 RCSTA_bits.WDTPS0
720 #define FERR RCSTA_bits.FERR
721 #define WDTPS1 RCSTA_bits.WDTPS1
722 #define ADDEN RCSTA_bits.ADDEN
723 #define WDTPS2 RCSTA_bits.WDTPS2
724 #define CREN RCSTA_bits.CREN
725 #define WDTPS3 RCSTA_bits.WDTPS3
726 #define SREN RCSTA_bits.SREN
727 #define RX9 RCSTA_bits.RX9
728 #define SPEN RCSTA_bits.SPEN
730 // ----- STATUS bits --------------------
736 unsigned char NOT_PD:1;
737 unsigned char NOT_TO:1;
743 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
745 #define C STATUS_bits.C
746 #define DC STATUS_bits.DC
747 #define Z STATUS_bits.Z
748 #define NOT_PD STATUS_bits.NOT_PD
749 #define NOT_TO STATUS_bits.NOT_TO
750 #define RP0 STATUS_bits.RP0
751 #define RP1 STATUS_bits.RP1
752 #define IRP STATUS_bits.IRP
754 // ----- T1CON bits --------------------
757 unsigned char TMR1ON:1;
758 unsigned char TMR1CS:1;
759 unsigned char NOT_T1SYNC:1;
760 unsigned char T1OSCEN:1;
761 unsigned char T1CKPS0:1;
762 unsigned char T1CKPS1:1;
763 unsigned char TMR1GE:1;
764 unsigned char T1GINV:1;
767 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
769 #define TMR1ON T1CON_bits.TMR1ON
770 #define TMR1CS T1CON_bits.TMR1CS
771 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
772 #define T1OSCEN T1CON_bits.T1OSCEN
773 #define T1CKPS0 T1CON_bits.T1CKPS0
774 #define T1CKPS1 T1CON_bits.T1CKPS1
775 #define TMR1GE T1CON_bits.TMR1GE
776 #define T1GINV T1CON_bits.T1GINV
778 // ----- TXSTA bits --------------------
781 unsigned char TX9D:1;
782 unsigned char TRMT:1;
783 unsigned char BRGH:1;
784 unsigned char SENDB:1;
785 unsigned char SYNC:1;
786 unsigned char TXEN:1;
788 unsigned char CSRC:1;
791 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
793 #define TX9D TXSTA_bits.TX9D
794 #define TRMT TXSTA_bits.TRMT
795 #define BRGH TXSTA_bits.BRGH
796 #define SENDB TXSTA_bits.SENDB
797 #define SYNC TXSTA_bits.SYNC
798 #define TXEN TXSTA_bits.TXEN
799 #define TX9 TXSTA_bits.TX9
800 #define CSRC TXSTA_bits.CSRC
802 // ----- VRCON bits --------------------
809 unsigned char ADCS0:1;
811 unsigned char ADCS2:1;
812 unsigned char VREN:1;
817 unsigned char WREN:1;
818 unsigned char WRERR:1;
820 unsigned char ADCS1:1;
822 unsigned char EEPGD:1;
825 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
827 #define VR0 VRCON_bits.VR0
828 #define RD VRCON_bits.RD
829 #define VR1 VRCON_bits.VR1
830 #define WR VRCON_bits.WR
831 #define VR2 VRCON_bits.VR2
832 #define WREN VRCON_bits.WREN
833 #define VR3 VRCON_bits.VR3
834 #define WRERR VRCON_bits.WRERR
835 #define ADCS0 VRCON_bits.ADCS0
836 #define VRR VRCON_bits.VRR
837 #define ADCS1 VRCON_bits.ADCS1
838 #define ADCS2 VRCON_bits.ADCS2
839 #define VREN VRCON_bits.VREN
840 #define EEPGD VRCON_bits.EEPGD