2 // Register Declarations for Microchip 16F688 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define BAUDCTL_ADDR 0x0011
42 #define SPBRGH_ADDR 0x0012
43 #define SPBRG_ADDR 0x0013
44 #define RCREG_ADDR 0x0014
45 #define TXREG_ADDR 0x0015
46 #define TXSTA_ADDR 0x0016
47 #define RCSTA_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define WPU_ADDR 0x0095
62 #define WPUA_ADDR 0x0095
63 #define IOC_ADDR 0x0096
64 #define IOCA_ADDR 0x0096
65 #define EEDATH_ADDR 0x0097
66 #define EEADRH_ADDR 0x0098
67 #define VRCON_ADDR 0x0099
68 #define EEDAT_ADDR 0x009A
69 #define EEDATA_ADDR 0x009A
70 #define EEADR_ADDR 0x009B
71 #define EECON1_ADDR 0x009C
72 #define EECON2_ADDR 0x009D
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
77 // Memory organization.
83 // P16F688.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
86 // This header file defines configurations, registers, and other useful bits of
87 // information for the PIC16F688 microcontroller. These names are taken to match
88 // the data sheets as closely as possible.
90 // Note that the processor must be selected before this file is
91 // included. The processor may be selected the following ways:
93 // 1. Command line switch:
94 // C:\ MPASM MYFILE.ASM /PIC16F688
95 // 2. LIST directive in the source file
97 // 3. Processor Type entry in the MPASM full-screen interface
99 //==========================================================================
103 //==========================================================================
104 //1.00 07/28/03 Original
105 //1.01 09/02/03 Modified to match datasheet
106 //1.02 09/19/03 Changed CMCON1 from 0x20 to 0x1A (pas)
107 //==========================================================================
111 //==========================================================================
114 // MESSG "Processor-header file mismatch. Verify selected processor."
117 //==========================================================================
119 // Register Definitions
121 //==========================================================================
126 //----- Register Files------------------------------------------------------
128 extern __sfr __at (INDF_ADDR) INDF;
129 extern __sfr __at (TMR0_ADDR) TMR0;
130 extern __sfr __at (PCL_ADDR) PCL;
131 extern __sfr __at (STATUS_ADDR) STATUS;
132 extern __sfr __at (FSR_ADDR) FSR;
133 extern __sfr __at (PORTA_ADDR) PORTA;
135 extern __sfr __at (PORTC_ADDR) PORTC;
137 extern __sfr __at (PCLATH_ADDR) PCLATH;
138 extern __sfr __at (INTCON_ADDR) INTCON;
139 extern __sfr __at (PIR1_ADDR) PIR1;
141 extern __sfr __at (TMR1L_ADDR) TMR1L;
142 extern __sfr __at (TMR1H_ADDR) TMR1H;
143 extern __sfr __at (T1CON_ADDR) T1CON;
144 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
145 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
146 extern __sfr __at (SPBRG_ADDR) SPBRG;
147 extern __sfr __at (RCREG_ADDR) RCREG;
148 extern __sfr __at (TXREG_ADDR) TXREG;
149 extern __sfr __at (TXSTA_ADDR) TXSTA;
150 extern __sfr __at (RCSTA_ADDR) RCSTA;
151 extern __sfr __at (WDTCON_ADDR) WDTCON;
152 extern __sfr __at (CMCON0_ADDR) CMCON0;
153 extern __sfr __at (CMCON1_ADDR) CMCON1;
155 extern __sfr __at (ADRESH_ADDR) ADRESH;
156 extern __sfr __at (ADCON0_ADDR) ADCON0;
159 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
161 extern __sfr __at (TRISA_ADDR) TRISA;
162 extern __sfr __at (TRISC_ADDR) TRISC;
164 extern __sfr __at (PIE1_ADDR) PIE1;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (OSCCON_ADDR) OSCCON;
168 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
169 extern __sfr __at (ANSEL_ADDR) ANSEL;
171 extern __sfr __at (WPU_ADDR) WPU;
172 extern __sfr __at (WPUA_ADDR) WPUA;
173 extern __sfr __at (IOC_ADDR) IOC;
174 extern __sfr __at (IOCA_ADDR) IOCA;
175 extern __sfr __at (EEDATH_ADDR) EEDATH;
176 extern __sfr __at (EEADRH_ADDR) EEADRH;
177 extern __sfr __at (VRCON_ADDR) VRCON;
178 extern __sfr __at (EEDAT_ADDR) EEDAT;
179 extern __sfr __at (EEDATA_ADDR) EEDATA;
180 extern __sfr __at (EEADR_ADDR) EEADR;
181 extern __sfr __at (EECON1_ADDR) EECON1;
182 extern __sfr __at (EECON2_ADDR) EECON2;
183 extern __sfr __at (ADRESL_ADDR) ADRESL;
184 extern __sfr __at (ADCON1_ADDR) ADCON1;
187 //----- STATUS Bits --------------------------------------------------------
190 //----- INTCON Bits --------------------------------------------------------
193 //----- PIR1 Bits ----------------------------------------------------------
196 //----- T1CON Bits ---------------------------------------------------------
199 //----- BAUDCTL Bits --------------------------------------------------------
202 //----- TXSTA Bits --------------------------------------------------------
205 //----- RCSTA Bits --------------------------------------------------------
207 //----- WDTCON Bits --------------------------------------------------------
210 //----- COMCON0 Bits -------------------------------------------------------
213 //----- COMCON1 Bits -------------------------------------------------------
216 //----- ADCON0 Bits --------------------------------------------------------
219 //----- OPTION Bits --------------------------------------------------------
222 //----- PIE1 Bits ----------------------------------------------------------
225 //----- PCON Bits ----------------------------------------------------------
228 //----- OSCCON Bits --------------------------------------------------------
231 //----- OSCTUNE Bits -------------------------------------------------------
234 //----- ANSEL --------------------------------------------------------------
237 //----- IOC --------------------------------------------------------------
240 //----- IOCA --------------------------------------------------------------
243 //----- VRCON Bits ---------------------------------------------------------
246 //----- EECON1 -------------------------------------------------------------
249 //----- ADCON1 -------------------------------------------------------------
252 //==========================================================================
256 //==========================================================================
259 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
260 // __BADRAM H'86', H'88'-H'89', H'8D', H'92'-H'94'
261 // __BADRAM H'106', H'108'-H'109', H'10C'-H'11F'
262 // __BADRAM H'186', H'188'-H'189', H'18C'-H'18D', H'190'-H'1EF'
264 //==========================================================================
266 // Configuration Bits
268 //==========================================================================
270 #define _FCMEN_ON 0x3FFF
271 #define _FCMEN_OFF 0x37FF
272 #define _IESO_ON 0x3FFF
273 #define _IESO_OFF 0x3BFF
274 #define _BOD_ON 0x3FFF
275 #define _BOD_NSLEEP 0x3EFF
276 #define _BOD_SBODEN 0x3DFF
277 #define _BOD_OFF 0x3CFF
278 #define _CPD_ON 0x3F7F
279 #define _CPD_OFF 0x3FFF
280 #define _CP_ON 0x3FBF
281 #define _CP_OFF 0x3FFF
282 #define _MCLRE_ON 0x3FFF
283 #define _MCLRE_OFF 0x3FDF
284 #define _PWRTE_OFF 0x3FFF
285 #define _PWRTE_ON 0x3FEF
286 #define _WDT_ON 0x3FFF
287 #define _WDT_OFF 0x3FF7
288 #define _LP_OSC 0x3FF8
289 #define _XT_OSC 0x3FF9
290 #define _HS_OSC 0x3FFA
291 #define _EC_OSC 0x3FFB
292 #define _INTRC_OSC_NOCLKOUT 0x3FFC
293 #define _INTRC_OSC_CLKOUT 0x3FFD
294 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
295 #define _EXTRC_OSC_CLKOUT 0x3FFF
296 #define _INTOSCIO 0x3FFC
297 #define _INTOSC 0x3FFD
298 #define _EXTRCIO 0x3FFE
299 #define _EXTRC 0x3FFF
303 // ----- ADCON0 bits --------------------
306 unsigned char ADON:1;
308 unsigned char CHS0:1;
309 unsigned char CHS1:1;
310 unsigned char CHS2:1;
312 unsigned char VCFG:1;
313 unsigned char ADFM:1;
317 unsigned char NOT_DONE:1;
327 unsigned char GO_DONE:1;
336 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
338 #ifndef NO_BIT_DEFINES
339 #define ADON ADCON0_bits.ADON
340 #define GO ADCON0_bits.GO
341 #define NOT_DONE ADCON0_bits.NOT_DONE
342 #define GO_DONE ADCON0_bits.GO_DONE
343 #define CHS0 ADCON0_bits.CHS0
344 #define CHS1 ADCON0_bits.CHS1
345 #define CHS2 ADCON0_bits.CHS2
346 #define VCFG ADCON0_bits.VCFG
347 #define ADFM ADCON0_bits.ADFM
348 #endif /* NO_BIT_DEFINES */
350 // ----- ADCON1 bits --------------------
357 unsigned char ADCS0:1;
358 unsigned char ADCS1:1;
359 unsigned char ADCS2:1;
363 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
365 #ifndef NO_BIT_DEFINES
366 #define ADCS0 ADCON1_bits.ADCS0
367 #define ADCS1 ADCON1_bits.ADCS1
368 #define ADCS2 ADCON1_bits.ADCS2
369 #endif /* NO_BIT_DEFINES */
371 // ----- ANSEL bits --------------------
374 unsigned char ANS0:1;
375 unsigned char ANS1:1;
376 unsigned char ANS2:1;
377 unsigned char ANS3:1;
378 unsigned char ANS4:1;
379 unsigned char ANS5:1;
380 unsigned char ANS6:1;
381 unsigned char ANS7:1;
384 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
386 #ifndef NO_BIT_DEFINES
387 #define ANS0 ANSEL_bits.ANS0
388 #define ANS1 ANSEL_bits.ANS1
389 #define ANS2 ANSEL_bits.ANS2
390 #define ANS3 ANSEL_bits.ANS3
391 #define ANS4 ANSEL_bits.ANS4
392 #define ANS5 ANSEL_bits.ANS5
393 #define ANS6 ANSEL_bits.ANS6
394 #define ANS7 ANSEL_bits.ANS7
395 #endif /* NO_BIT_DEFINES */
397 // ----- BAUDCTL bits --------------------
400 unsigned char ABDEN:1;
403 unsigned char BRG16:1;
404 unsigned char SCKP:1;
406 unsigned char RCIDL:1;
407 unsigned char ABDOVF:1;
410 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
412 #ifndef NO_BIT_DEFINES
413 #define ABDEN BAUDCTL_bits.ABDEN
414 #define WUE BAUDCTL_bits.WUE
415 #define BRG16 BAUDCTL_bits.BRG16
416 #define SCKP BAUDCTL_bits.SCKP
417 #define RCIDL BAUDCTL_bits.RCIDL
418 #define ABDOVF BAUDCTL_bits.ABDOVF
419 #endif /* NO_BIT_DEFINES */
421 // ----- CMCON0 bits --------------------
428 unsigned char C1INV:1;
429 unsigned char C2INV:1;
430 unsigned char C1OUT:1;
431 unsigned char C2OUT:1;
434 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
436 #ifndef NO_BIT_DEFINES
437 #define CM0 CMCON0_bits.CM0
438 #define CM1 CMCON0_bits.CM1
439 #define CM2 CMCON0_bits.CM2
440 #define CIS CMCON0_bits.CIS
441 #define C1INV CMCON0_bits.C1INV
442 #define C2INV CMCON0_bits.C2INV
443 #define C1OUT CMCON0_bits.C1OUT
444 #define C2OUT CMCON0_bits.C2OUT
445 #endif /* NO_BIT_DEFINES */
447 // ----- CMCON1 bits --------------------
450 unsigned char C2SYNC:1;
451 unsigned char T1GSS:1;
460 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
462 #ifndef NO_BIT_DEFINES
463 #define C2SYNC CMCON1_bits.C2SYNC
464 #define T1GSS CMCON1_bits.T1GSS
465 #endif /* NO_BIT_DEFINES */
467 // ----- EECON1 bits --------------------
472 unsigned char WREN:1;
473 unsigned char WRERR:1;
477 unsigned char EEPGD:1;
480 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
482 #ifndef NO_BIT_DEFINES
483 #define RD EECON1_bits.RD
484 #define WR EECON1_bits.WR
485 #define WREN EECON1_bits.WREN
486 #define WRERR EECON1_bits.WRERR
487 #define EEPGD EECON1_bits.EEPGD
488 #endif /* NO_BIT_DEFINES */
490 // ----- INTCON bits --------------------
493 unsigned char RAIF:1;
494 unsigned char INTF:1;
495 unsigned char T0IF:1;
496 unsigned char RAIE:1;
497 unsigned char INTE:1;
498 unsigned char T0IE:1;
499 unsigned char PEIE:1;
503 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
505 #ifndef NO_BIT_DEFINES
506 #define RAIF INTCON_bits.RAIF
507 #define INTF INTCON_bits.INTF
508 #define T0IF INTCON_bits.T0IF
509 #define RAIE INTCON_bits.RAIE
510 #define INTE INTCON_bits.INTE
511 #define T0IE INTCON_bits.T0IE
512 #define PEIE INTCON_bits.PEIE
513 #define GIE INTCON_bits.GIE
514 #endif /* NO_BIT_DEFINES */
516 // ----- IOC bits --------------------
519 unsigned char IOC0:1;
520 unsigned char IOC1:1;
521 unsigned char IOC2:1;
522 unsigned char IOC3:1;
523 unsigned char IOC4:1;
524 unsigned char IOC5:1;
529 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
531 #ifndef NO_BIT_DEFINES
532 #define IOC0 IOC_bits.IOC0
533 #define IOC1 IOC_bits.IOC1
534 #define IOC2 IOC_bits.IOC2
535 #define IOC3 IOC_bits.IOC3
536 #define IOC4 IOC_bits.IOC4
537 #define IOC5 IOC_bits.IOC5
538 #endif /* NO_BIT_DEFINES */
540 // ----- IOCA bits --------------------
543 unsigned char IOCA0:1;
544 unsigned char IOCA1:1;
545 unsigned char IOCA2:1;
546 unsigned char IOCA3:1;
547 unsigned char IOCA4:1;
548 unsigned char IOCA5:1;
553 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
555 #ifndef NO_BIT_DEFINES
556 #define IOCA0 IOCA_bits.IOCA0
557 #define IOCA1 IOCA_bits.IOCA1
558 #define IOCA2 IOCA_bits.IOCA2
559 #define IOCA3 IOCA_bits.IOCA3
560 #define IOCA4 IOCA_bits.IOCA4
561 #define IOCA5 IOCA_bits.IOCA5
562 #endif /* NO_BIT_DEFINES */
564 // ----- OPTION_REG bits --------------------
571 unsigned char T0SE:1;
572 unsigned char T0CS:1;
573 unsigned char INTEDG:1;
574 unsigned char NOT_RAPU:1;
576 } __OPTION_REG_bits_t;
577 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
579 #ifndef NO_BIT_DEFINES
580 #define PS0 OPTION_REG_bits.PS0
581 #define PS1 OPTION_REG_bits.PS1
582 #define PS2 OPTION_REG_bits.PS2
583 #define PSA OPTION_REG_bits.PSA
584 #define T0SE OPTION_REG_bits.T0SE
585 #define T0CS OPTION_REG_bits.T0CS
586 #define INTEDG OPTION_REG_bits.INTEDG
587 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
588 #endif /* NO_BIT_DEFINES */
590 // ----- OSCCON bits --------------------
596 unsigned char OSTS:1;
597 unsigned char IRCF0:1;
598 unsigned char IRCF1:1;
599 unsigned char IRCF2:1;
603 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
605 #ifndef NO_BIT_DEFINES
606 #define SCS OSCCON_bits.SCS
607 #define LTS OSCCON_bits.LTS
608 #define HTS OSCCON_bits.HTS
609 #define OSTS OSCCON_bits.OSTS
610 #define IRCF0 OSCCON_bits.IRCF0
611 #define IRCF1 OSCCON_bits.IRCF1
612 #define IRCF2 OSCCON_bits.IRCF2
613 #endif /* NO_BIT_DEFINES */
615 // ----- OSCTUNE bits --------------------
618 unsigned char TUN0:1;
619 unsigned char TUN1:1;
620 unsigned char TUN2:1;
621 unsigned char TUN3:1;
622 unsigned char TUN4:1;
628 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
630 #ifndef NO_BIT_DEFINES
631 #define TUN0 OSCTUNE_bits.TUN0
632 #define TUN1 OSCTUNE_bits.TUN1
633 #define TUN2 OSCTUNE_bits.TUN2
634 #define TUN3 OSCTUNE_bits.TUN3
635 #define TUN4 OSCTUNE_bits.TUN4
636 #endif /* NO_BIT_DEFINES */
638 // ----- PCON bits --------------------
641 unsigned char NOT_BOD:1;
642 unsigned char NOT_POR:1;
645 unsigned char SBODEN:1;
646 unsigned char ULPWUE:1;
651 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
653 #ifndef NO_BIT_DEFINES
654 #define NOT_BOD PCON_bits.NOT_BOD
655 #define NOT_POR PCON_bits.NOT_POR
656 #define SBODEN PCON_bits.SBODEN
657 #define ULPWUE PCON_bits.ULPWUE
658 #endif /* NO_BIT_DEFINES */
660 // ----- PIE1 bits --------------------
663 unsigned char T1IE:1;
664 unsigned char TXIE:1;
665 unsigned char OSFIE:1;
666 unsigned char C1IE:1;
667 unsigned char C2IE:1;
668 unsigned char RCIE:1;
669 unsigned char ADIE:1;
670 unsigned char EEIE:1;
673 unsigned char TMR1IE:1;
683 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
685 #ifndef NO_BIT_DEFINES
686 #define T1IE PIE1_bits.T1IE
687 #define TMR1IE PIE1_bits.TMR1IE
688 #define TXIE PIE1_bits.TXIE
689 #define OSFIE PIE1_bits.OSFIE
690 #define C1IE PIE1_bits.C1IE
691 #define C2IE PIE1_bits.C2IE
692 #define RCIE PIE1_bits.RCIE
693 #define ADIE PIE1_bits.ADIE
694 #define EEIE PIE1_bits.EEIE
695 #endif /* NO_BIT_DEFINES */
697 // ----- PIR1 bits --------------------
700 unsigned char T1IF:1;
701 unsigned char TXIF:1;
702 unsigned char OSFIF:1;
703 unsigned char C1IF:1;
704 unsigned char C2IF:1;
705 unsigned char RCIF:1;
706 unsigned char ADIF:1;
707 unsigned char EEIF:1;
710 unsigned char TMR1IF:1;
720 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
722 #ifndef NO_BIT_DEFINES
723 #define T1IF PIR1_bits.T1IF
724 #define TMR1IF PIR1_bits.TMR1IF
725 #define TXIF PIR1_bits.TXIF
726 #define OSFIF PIR1_bits.OSFIF
727 #define C1IF PIR1_bits.C1IF
728 #define C2IF PIR1_bits.C2IF
729 #define RCIF PIR1_bits.RCIF
730 #define ADIF PIR1_bits.ADIF
731 #define EEIF PIR1_bits.EEIF
732 #endif /* NO_BIT_DEFINES */
734 // ----- PORTA bits --------------------
747 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
749 #ifndef NO_BIT_DEFINES
750 #define RA0 PORTA_bits.RA0
751 #define RA1 PORTA_bits.RA1
752 #define RA2 PORTA_bits.RA2
753 #define RA3 PORTA_bits.RA3
754 #define RA4 PORTA_bits.RA4
755 #define RA5 PORTA_bits.RA5
756 #endif /* NO_BIT_DEFINES */
758 // ----- PORTC bits --------------------
771 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
773 #ifndef NO_BIT_DEFINES
774 #define RC0 PORTC_bits.RC0
775 #define RC1 PORTC_bits.RC1
776 #define RC2 PORTC_bits.RC2
777 #define RC3 PORTC_bits.RC3
778 #define RC4 PORTC_bits.RC4
779 #define RC5 PORTC_bits.RC5
780 #define RC6 PORTC_bits.RC6
781 #define RC7 PORTC_bits.RC7
782 #endif /* NO_BIT_DEFINES */
784 // ----- RCSTA bits --------------------
787 unsigned char RX9D:1;
788 unsigned char OERR:1;
789 unsigned char FERR:1;
790 unsigned char ADDEN:1;
791 unsigned char CREN:1;
792 unsigned char SREN:1;
794 unsigned char SPEN:1;
797 unsigned char SWDTEN:1;
798 unsigned char WDTPS0:1;
799 unsigned char WDTPS1:1;
800 unsigned char WDTPS2:1;
801 unsigned char WDTPS3:1;
807 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
809 #ifndef NO_BIT_DEFINES
810 #define RX9D RCSTA_bits.RX9D
811 #define SWDTEN RCSTA_bits.SWDTEN
812 #define OERR RCSTA_bits.OERR
813 #define WDTPS0 RCSTA_bits.WDTPS0
814 #define FERR RCSTA_bits.FERR
815 #define WDTPS1 RCSTA_bits.WDTPS1
816 #define ADDEN RCSTA_bits.ADDEN
817 #define WDTPS2 RCSTA_bits.WDTPS2
818 #define CREN RCSTA_bits.CREN
819 #define WDTPS3 RCSTA_bits.WDTPS3
820 #define SREN RCSTA_bits.SREN
821 #define RX9 RCSTA_bits.RX9
822 #define SPEN RCSTA_bits.SPEN
823 #endif /* NO_BIT_DEFINES */
825 // ----- STATUS bits --------------------
831 unsigned char NOT_PD:1;
832 unsigned char NOT_TO:1;
838 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
840 #ifndef NO_BIT_DEFINES
841 #define C STATUS_bits.C
842 #define DC STATUS_bits.DC
843 #define Z STATUS_bits.Z
844 #define NOT_PD STATUS_bits.NOT_PD
845 #define NOT_TO STATUS_bits.NOT_TO
846 #define RP0 STATUS_bits.RP0
847 #define RP1 STATUS_bits.RP1
848 #define IRP STATUS_bits.IRP
849 #endif /* NO_BIT_DEFINES */
851 // ----- T1CON bits --------------------
854 unsigned char TMR1ON:1;
855 unsigned char TMR1CS:1;
856 unsigned char NOT_T1SYNC:1;
857 unsigned char T1OSCEN:1;
858 unsigned char T1CKPS0:1;
859 unsigned char T1CKPS1:1;
860 unsigned char TMR1GE:1;
861 unsigned char T1GINV:1;
864 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
866 #ifndef NO_BIT_DEFINES
867 #define TMR1ON T1CON_bits.TMR1ON
868 #define TMR1CS T1CON_bits.TMR1CS
869 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
870 #define T1OSCEN T1CON_bits.T1OSCEN
871 #define T1CKPS0 T1CON_bits.T1CKPS0
872 #define T1CKPS1 T1CON_bits.T1CKPS1
873 #define TMR1GE T1CON_bits.TMR1GE
874 #define T1GINV T1CON_bits.T1GINV
875 #endif /* NO_BIT_DEFINES */
877 // ----- TRISA bits --------------------
880 unsigned char TRISA0:1;
881 unsigned char TRISA1:1;
882 unsigned char TRISA2:1;
883 unsigned char TRISA3:1;
884 unsigned char TRISA4:1;
885 unsigned char TRISA5:1;
890 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
892 #ifndef NO_BIT_DEFINES
893 #define TRISA0 TRISA_bits.TRISA0
894 #define TRISA1 TRISA_bits.TRISA1
895 #define TRISA2 TRISA_bits.TRISA2
896 #define TRISA3 TRISA_bits.TRISA3
897 #define TRISA4 TRISA_bits.TRISA4
898 #define TRISA5 TRISA_bits.TRISA5
899 #endif /* NO_BIT_DEFINES */
901 // ----- TRISC bits --------------------
904 unsigned char TRISC0:1;
905 unsigned char TRISC1:1;
906 unsigned char TRISC2:1;
907 unsigned char TRISC3:1;
908 unsigned char TRISC4:1;
909 unsigned char TRISC5:1;
910 unsigned char TRISC6:1;
911 unsigned char TRISC7:1;
914 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
916 #ifndef NO_BIT_DEFINES
917 #define TRISC0 TRISC_bits.TRISC0
918 #define TRISC1 TRISC_bits.TRISC1
919 #define TRISC2 TRISC_bits.TRISC2
920 #define TRISC3 TRISC_bits.TRISC3
921 #define TRISC4 TRISC_bits.TRISC4
922 #define TRISC5 TRISC_bits.TRISC5
923 #define TRISC6 TRISC_bits.TRISC6
924 #define TRISC7 TRISC_bits.TRISC7
925 #endif /* NO_BIT_DEFINES */
927 // ----- TXSTA bits --------------------
930 unsigned char TX9D:1;
931 unsigned char TRMT:1;
932 unsigned char BRGH:1;
933 unsigned char SENDB:1;
934 unsigned char SYNC:1;
935 unsigned char TXEN:1;
937 unsigned char CSRC:1;
940 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
942 #ifndef NO_BIT_DEFINES
943 #define TX9D TXSTA_bits.TX9D
944 #define TRMT TXSTA_bits.TRMT
945 #define BRGH TXSTA_bits.BRGH
946 #define SENDB TXSTA_bits.SENDB
947 #define SYNC TXSTA_bits.SYNC
948 #define TXEN TXSTA_bits.TXEN
949 #define TX9 TXSTA_bits.TX9
950 #define CSRC TXSTA_bits.CSRC
951 #endif /* NO_BIT_DEFINES */
953 // ----- VRCON bits --------------------
963 unsigned char VREN:1;
966 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
968 #ifndef NO_BIT_DEFINES
969 #define VR0 VRCON_bits.VR0
970 #define VR1 VRCON_bits.VR1
971 #define VR2 VRCON_bits.VR2
972 #define VR3 VRCON_bits.VR3
973 #define VRR VRCON_bits.VRR
974 #define VREN VRCON_bits.VREN
975 #endif /* NO_BIT_DEFINES */