2 // Register Declarations for Microchip 16F687 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define SSPBUF_ADDR 0x0013
44 #define SSPCON_ADDR 0x0014
45 #define RCSTA_ADDR 0x0018
46 #define TXREG_ADDR 0x0019
47 #define RCREG_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define SSPADD_ADDR 0x0093
60 #define MSK_ADDR 0x0093
61 #define SSPMSK_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define WPU_ADDR 0x0095
64 #define WPUA_ADDR 0x0095
65 #define IOC_ADDR 0x0096
66 #define IOCA_ADDR 0x0096
67 #define WDTCON_ADDR 0x0097
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define SPBRGH_ADDR 0x009A
71 #define BAUDCTL_ADDR 0x009B
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
74 #define EEDAT_ADDR 0x010C
75 #define EEDATA_ADDR 0x010C
76 #define EEADR_ADDR 0x010D
77 #define EEDATH_ADDR 0x010E
78 #define EEADRH_ADDR 0x010F
79 #define WPUB_ADDR 0x0115
80 #define IOCB_ADDR 0x0116
81 #define VRCON_ADDR 0x0118
82 #define CM1CON0_ADDR 0x0119
83 #define CM2CON0_ADDR 0x011A
84 #define CM2CON1_ADDR 0x011B
85 #define ANSEL_ADDR 0x011E
86 #define ANSELH_ADDR 0x011F
87 #define EECON1_ADDR 0x018C
88 #define EECON2_ADDR 0x018D
89 #define SRCON_ADDR 0x019E
92 // Memory organization.
98 // P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
101 // This header file defines configurations, registers, and other useful bits of
102 // information for the PIC16F687 microcontroller. These names are taken to match
103 // the data sheets as closely as possible.
105 // Note that the processor must be selected before this file is
106 // included. The processor may be selected the following ways:
108 // 1. Command line switch:
109 // C:\ MPASM MYFILE.ASM /PIC16F687
110 // 2. LIST directive in the source file
112 // 3. Processor Type entry in the MPASM full-screen interface
114 //==========================================================================
118 //==========================================================================
119 //1.00 10/12/04 Original
120 //2.00 04/21/05 Modified to match released datasheet
121 //==========================================================================
125 //==========================================================================
128 // MESSG "Processor-header file mismatch. Verify selected processor."
131 //==========================================================================
133 // Register Definitions
135 //==========================================================================
140 //----- Register Files------------------------------------------------------
142 extern __sfr __at (INDF_ADDR) INDF;
143 extern __sfr __at (TMR0_ADDR) TMR0;
144 extern __sfr __at (PCL_ADDR) PCL;
145 extern __sfr __at (STATUS_ADDR) STATUS;
146 extern __sfr __at (FSR_ADDR) FSR;
147 extern __sfr __at (PORTA_ADDR) PORTA;
148 extern __sfr __at (PORTB_ADDR) PORTB;
149 extern __sfr __at (PORTC_ADDR) PORTC;
151 extern __sfr __at (PCLATH_ADDR) PCLATH;
152 extern __sfr __at (INTCON_ADDR) INTCON;
153 extern __sfr __at (PIR1_ADDR) PIR1;
154 extern __sfr __at (PIR2_ADDR) PIR2;
155 extern __sfr __at (TMR1L_ADDR) TMR1L;
156 extern __sfr __at (TMR1H_ADDR) TMR1H;
157 extern __sfr __at (T1CON_ADDR) T1CON;
160 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
161 extern __sfr __at (SSPCON_ADDR) SSPCON;
164 extern __sfr __at (RCSTA_ADDR) RCSTA;
165 extern __sfr __at (TXREG_ADDR) TXREG;
166 extern __sfr __at (RCREG_ADDR) RCREG;
168 extern __sfr __at (ADRESH_ADDR) ADRESH;
169 extern __sfr __at (ADCON0_ADDR) ADCON0;
172 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
174 extern __sfr __at (TRISA_ADDR) TRISA;
175 extern __sfr __at (TRISB_ADDR) TRISB;
176 extern __sfr __at (TRISC_ADDR) TRISC;
178 extern __sfr __at (PIE1_ADDR) PIE1;
179 extern __sfr __at (PIE2_ADDR) PIE2;
180 extern __sfr __at (PCON_ADDR) PCON;
181 extern __sfr __at (OSCCON_ADDR) OSCCON;
182 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
184 extern __sfr __at (SSPADD_ADDR) SSPADD;
185 extern __sfr __at (MSK_ADDR) MSK;
186 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
187 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
188 extern __sfr __at (WPU_ADDR) WPU;
189 extern __sfr __at (WPUA_ADDR) WPUA;
190 extern __sfr __at (IOC_ADDR) IOC;
191 extern __sfr __at (IOCA_ADDR) IOCA;
192 extern __sfr __at (WDTCON_ADDR) WDTCON;
193 extern __sfr __at (TXSTA_ADDR) TXSTA;
194 extern __sfr __at (SPBRG_ADDR) SPBRG;
195 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
196 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
199 extern __sfr __at (ADRESL_ADDR) ADRESL;
200 extern __sfr __at (ADCON1_ADDR) ADCON1;
203 extern __sfr __at (EEDAT_ADDR) EEDAT;
204 extern __sfr __at (EEDATA_ADDR) EEDATA;
205 extern __sfr __at (EEADR_ADDR) EEADR;
206 extern __sfr __at (EEDATH_ADDR) EEDATH;
207 extern __sfr __at (EEADRH_ADDR) EEADRH;
210 extern __sfr __at (WPUB_ADDR) WPUB;
211 extern __sfr __at (IOCB_ADDR) IOCB;
213 extern __sfr __at (VRCON_ADDR) VRCON;
214 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
215 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
216 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
218 extern __sfr __at (ANSEL_ADDR) ANSEL;
219 extern __sfr __at (ANSELH_ADDR) ANSELH;
221 extern __sfr __at (EECON1_ADDR) EECON1;
222 extern __sfr __at (EECON2_ADDR) EECON2;
225 extern __sfr __at (SRCON_ADDR) SRCON;
229 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
230 //----- STATUS Bits --------------------------------------------------------
233 //----- INTCON Bits --------------------------------------------------------
236 //----- PIR1 Bits ----------------------------------------------------------
241 //----- PIR2 Bits ----------------------------------------------------------
244 //----- T1CON Bits ---------------------------------------------------------
248 //----- SSPCON Bits --------------------------------------------------------
252 //----- RCSTA Bits ---------------------------------------------------------
256 //----- ADCON0 Bits --------------------------------------------------------
259 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
260 //----- OPTION Bits --------------------------------------------------------
263 //----- TRISA Bits --------------------------------------------------------
266 //----- TRISB Bits --------------------------------------------------------
269 //----- TRISC Bits --------------------------------------------------------
272 //----- PIE1 Bits ----------------------------------------------------------
277 //----- PIE2 Bits ----------------------------------------------------------
280 //----- PCON Bits ----------------------------------------------------------
283 //----- OSCCON Bits --------------------------------------------------------
286 //----- OSCTUNE Bits -------------------------------------------------------
289 //----- SSPSTAT Bits --------------------------------------------------------
292 //----- WPUA --------------------------------------------------------------
296 //----- IOC --------------------------------------------------------------
299 //----- IOCA --------------------------------------------------------------
302 //----- WDTCON Bits --------------------------------------------------------
305 //----- TXSTA Bits -------------------------------------------------------
308 //----- SPBRG Bits -------------------------------------------------------
311 //----- SPBRGH Bits -------------------------------------------------------
314 //----- BAUDCTL Bits -------------------------------------------------------
319 //----- ADCON1 -------------------------------------------------------------
322 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
323 //----- WPUB Bits ----------------------------------------------------------
326 //----- IOCB --------------------------------------------------------------
329 //----- VRCON Bits ---------------------------------------------------------
332 //----- CM1CON0 Bits -------------------------------------------------------
336 //----- CM2CON0 Bits -------------------------------------------------------
340 //----- CM2CON1 Bits -------------------------------------------------------
343 //----- ANSELH -------------------------------------------------------------
346 //----- ANSEL --------------------------------------------------------------
349 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
350 //----- EECON1 -------------------------------------------------------------
353 //----- SRCON ---------------------------------------------------------------
356 //==========================================================================
360 //==========================================================================
363 // __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D'
364 // __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF'
365 // __BADRAM H'108'-H'109', H'10E'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F'
366 // __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF'
368 //==========================================================================
370 // Configuration Bits
372 //==========================================================================
374 #define _FCMEN_ON 0x3FFF
375 #define _FCMEN_OFF 0x37FF
376 #define _IESO_ON 0x3FFF
377 #define _IESO_OFF 0x3BFF
378 #define _BOR_ON 0x3FFF
379 #define _BOR_NSLEEP 0x3EFF
380 #define _BOR_SBODEN 0x3DFF
381 #define _BOR_OFF 0x3CFF
382 #define _CPD_ON 0x3F7F
383 #define _CPD_OFF 0x3FFF
384 #define _CP_ON 0x3FBF
385 #define _CP_OFF 0x3FFF
386 #define _MCLRE_ON 0x3FFF
387 #define _MCLRE_OFF 0x3FDF
388 #define _PWRTE_OFF 0x3FFF
389 #define _PWRTE_ON 0x3FEF
390 #define _WDT_ON 0x3FFF
391 #define _WDT_OFF 0x3FF7
392 #define _LP_OSC 0x3FF8
393 #define _XT_OSC 0x3FF9
394 #define _HS_OSC 0x3FFA
395 #define _EC_OSC 0x3FFB
396 #define _INTRC_OSC_NOCLKOUT 0x3FFC
397 #define _INTRC_OSC_CLKOUT 0x3FFD
398 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
399 #define _EXTRC_OSC_CLKOUT 0x3FFF
400 #define _INTOSCIO 0x3FFC
401 #define _INTOSC 0x3FFD
402 #define _EXTRCIO 0x3FFE
403 #define _EXTRC 0x3FFF
407 // ----- ADCON0 bits --------------------
410 unsigned char ADON:1;
412 unsigned char CHS0:1;
413 unsigned char CHS1:1;
414 unsigned char CHS2:1;
415 unsigned char CHS3:1;
416 unsigned char VCFG:1;
417 unsigned char ADFM:1;
421 unsigned char NOT_DONE:1;
431 unsigned char GO_DONE:1;
440 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
442 #define ADON ADCON0_bits.ADON
443 #define GO ADCON0_bits.GO
444 #define NOT_DONE ADCON0_bits.NOT_DONE
445 #define GO_DONE ADCON0_bits.GO_DONE
446 #define CHS0 ADCON0_bits.CHS0
447 #define CHS1 ADCON0_bits.CHS1
448 #define CHS2 ADCON0_bits.CHS2
449 #define CHS3 ADCON0_bits.CHS3
450 #define VCFG ADCON0_bits.VCFG
451 #define ADFM ADCON0_bits.ADFM
453 // ----- ADCON1 bits --------------------
460 unsigned char ADCS0:1;
461 unsigned char ADCS1:1;
462 unsigned char ADCS2:1;
466 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
468 #define ADCS0 ADCON1_bits.ADCS0
469 #define ADCS1 ADCON1_bits.ADCS1
470 #define ADCS2 ADCON1_bits.ADCS2
472 // ----- ANSEL bits --------------------
475 unsigned char ANS0:1;
476 unsigned char ANS1:1;
477 unsigned char ANS2:1;
478 unsigned char ANS3:1;
479 unsigned char ANS4:1;
480 unsigned char ANS5:1;
481 unsigned char ANS6:1;
482 unsigned char ANS7:1;
485 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
487 #define ANS0 ANSEL_bits.ANS0
488 #define ANS1 ANSEL_bits.ANS1
489 #define ANS2 ANSEL_bits.ANS2
490 #define ANS3 ANSEL_bits.ANS3
491 #define ANS4 ANSEL_bits.ANS4
492 #define ANS5 ANSEL_bits.ANS5
493 #define ANS6 ANSEL_bits.ANS6
494 #define ANS7 ANSEL_bits.ANS7
496 // ----- ANSELH bits --------------------
499 unsigned char ANS8:1;
500 unsigned char ANS9:1;
501 unsigned char ANS10:1;
502 unsigned char ANS11:1;
509 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
511 #define ANS8 ANSELH_bits.ANS8
512 #define ANS9 ANSELH_bits.ANS9
513 #define ANS10 ANSELH_bits.ANS10
514 #define ANS11 ANSELH_bits.ANS11
516 // ----- BAUDCTL bits --------------------
519 unsigned char ABDEN:1;
522 unsigned char BRG16:1;
523 unsigned char SCKP:1;
525 unsigned char RCIDL:1;
526 unsigned char ABDOVF:1;
529 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
531 #define ABDEN BAUDCTL_bits.ABDEN
532 #define WUE BAUDCTL_bits.WUE
533 #define BRG16 BAUDCTL_bits.BRG16
534 #define SCKP BAUDCTL_bits.SCKP
535 #define RCIDL BAUDCTL_bits.RCIDL
536 #define ABDOVF BAUDCTL_bits.ABDOVF
538 // ----- CM1CON0 bits --------------------
541 unsigned char C1CH0:1;
542 unsigned char C1CH1:1;
545 unsigned char C1POL:1;
546 unsigned char C1OE:1;
547 unsigned char C1OUT:1;
548 unsigned char C1ON:1;
551 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
553 #define C1CH0 CM1CON0_bits.C1CH0
554 #define C1CH1 CM1CON0_bits.C1CH1
555 #define C1R CM1CON0_bits.C1R
556 #define C1POL CM1CON0_bits.C1POL
557 #define C1OE CM1CON0_bits.C1OE
558 #define C1OUT CM1CON0_bits.C1OUT
559 #define C1ON CM1CON0_bits.C1ON
561 // ----- CM2CON0 bits --------------------
564 unsigned char C2CH0:1;
565 unsigned char C2CH1:1;
568 unsigned char C2POL:1;
569 unsigned char C2OE:1;
570 unsigned char C2OUT:1;
571 unsigned char C2ON:1;
574 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
576 #define C2CH0 CM2CON0_bits.C2CH0
577 #define C2CH1 CM2CON0_bits.C2CH1
578 #define C2R CM2CON0_bits.C2R
579 #define C2POL CM2CON0_bits.C2POL
580 #define C2OE CM2CON0_bits.C2OE
581 #define C2OUT CM2CON0_bits.C2OUT
582 #define C2ON CM2CON0_bits.C2ON
584 // ----- CM2CON1 bits --------------------
587 unsigned char C2SYNC:1;
588 unsigned char T1GSS:1;
593 unsigned char MC2OUT:1;
594 unsigned char MC1OUT:1;
597 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
599 #define C2SYNC CM2CON1_bits.C2SYNC
600 #define T1GSS CM2CON1_bits.T1GSS
601 #define MC2OUT CM2CON1_bits.MC2OUT
602 #define MC1OUT CM2CON1_bits.MC1OUT
604 // ----- EECON1 bits --------------------
609 unsigned char WREN:1;
610 unsigned char WRERR:1;
614 unsigned char EEPGD:1;
617 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
619 #define RD EECON1_bits.RD
620 #define WR EECON1_bits.WR
621 #define WREN EECON1_bits.WREN
622 #define WRERR EECON1_bits.WRERR
623 #define EEPGD EECON1_bits.EEPGD
625 // ----- INTCON bits --------------------
628 unsigned char RABIF:1;
629 unsigned char INTF:1;
630 unsigned char T0IF:1;
631 unsigned char RABIE:1;
632 unsigned char INTE:1;
633 unsigned char T0IE:1;
634 unsigned char PEIE:1;
638 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
640 #define RABIF INTCON_bits.RABIF
641 #define INTF INTCON_bits.INTF
642 #define T0IF INTCON_bits.T0IF
643 #define RABIE INTCON_bits.RABIE
644 #define INTE INTCON_bits.INTE
645 #define T0IE INTCON_bits.T0IE
646 #define PEIE INTCON_bits.PEIE
647 #define GIE INTCON_bits.GIE
649 // ----- IOC bits --------------------
652 unsigned char IOC0:1;
653 unsigned char IOC1:1;
654 unsigned char IOC2:1;
655 unsigned char IOC3:1;
656 unsigned char IOC4:1;
657 unsigned char IOC5:1;
662 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
664 #define IOC0 IOC_bits.IOC0
665 #define IOC1 IOC_bits.IOC1
666 #define IOC2 IOC_bits.IOC2
667 #define IOC3 IOC_bits.IOC3
668 #define IOC4 IOC_bits.IOC4
669 #define IOC5 IOC_bits.IOC5
671 // ----- IOCA bits --------------------
674 unsigned char IOCA0:1;
675 unsigned char IOCA1:1;
676 unsigned char IOCA2:1;
677 unsigned char IOCA3:1;
678 unsigned char IOCA4:1;
679 unsigned char IOCA5:1;
684 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
686 #define IOCA0 IOCA_bits.IOCA0
687 #define IOCA1 IOCA_bits.IOCA1
688 #define IOCA2 IOCA_bits.IOCA2
689 #define IOCA3 IOCA_bits.IOCA3
690 #define IOCA4 IOCA_bits.IOCA4
691 #define IOCA5 IOCA_bits.IOCA5
693 // ----- IOCB bits --------------------
700 unsigned char IOCB4:1;
701 unsigned char IOCB5:1;
702 unsigned char IOCB6:1;
703 unsigned char IOCB7:1;
706 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
708 #define IOCB4 IOCB_bits.IOCB4
709 #define IOCB5 IOCB_bits.IOCB5
710 #define IOCB6 IOCB_bits.IOCB6
711 #define IOCB7 IOCB_bits.IOCB7
713 // ----- OPTION_REG bits --------------------
720 unsigned char T0SE:1;
721 unsigned char T0CS:1;
722 unsigned char INTEDG:1;
723 unsigned char NOT_RABPU:1;
725 } __OPTION_REG_bits_t;
726 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
728 #define PS0 OPTION_REG_bits.PS0
729 #define PS1 OPTION_REG_bits.PS1
730 #define PS2 OPTION_REG_bits.PS2
731 #define PSA OPTION_REG_bits.PSA
732 #define T0SE OPTION_REG_bits.T0SE
733 #define T0CS OPTION_REG_bits.T0CS
734 #define INTEDG OPTION_REG_bits.INTEDG
735 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
737 // ----- OSCCON bits --------------------
743 unsigned char OSTS:1;
744 unsigned char IRCF0:1;
745 unsigned char IRCF1:1;
746 unsigned char IRCF2:1;
750 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
752 #define SCS OSCCON_bits.SCS
753 #define LTS OSCCON_bits.LTS
754 #define HTS OSCCON_bits.HTS
755 #define OSTS OSCCON_bits.OSTS
756 #define IRCF0 OSCCON_bits.IRCF0
757 #define IRCF1 OSCCON_bits.IRCF1
758 #define IRCF2 OSCCON_bits.IRCF2
760 // ----- OSCTUNE bits --------------------
763 unsigned char TUN0:1;
764 unsigned char TUN1:1;
765 unsigned char TUN2:1;
766 unsigned char TUN3:1;
767 unsigned char TUN4:1;
773 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
775 #define TUN0 OSCTUNE_bits.TUN0
776 #define TUN1 OSCTUNE_bits.TUN1
777 #define TUN2 OSCTUNE_bits.TUN2
778 #define TUN3 OSCTUNE_bits.TUN3
779 #define TUN4 OSCTUNE_bits.TUN4
781 // ----- PCON bits --------------------
784 unsigned char NOT_BOR:1;
785 unsigned char NOT_POR:1;
788 unsigned char SBOREN:1;
789 unsigned char ULPWUE:1;
794 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
796 #define NOT_BOR PCON_bits.NOT_BOR
797 #define NOT_POR PCON_bits.NOT_POR
798 #define SBOREN PCON_bits.SBOREN
799 #define ULPWUE PCON_bits.ULPWUE
801 // ----- PIE1 bits --------------------
804 unsigned char T1IE:1;
807 unsigned char SSPIE:1;
808 unsigned char TXIE:1;
809 unsigned char RCIE:1;
810 unsigned char ADIE:1;
814 unsigned char TMR1IE:1;
824 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
826 #define T1IE PIE1_bits.T1IE
827 #define TMR1IE PIE1_bits.TMR1IE
828 #define SSPIE PIE1_bits.SSPIE
829 #define TXIE PIE1_bits.TXIE
830 #define RCIE PIE1_bits.RCIE
831 #define ADIE PIE1_bits.ADIE
833 // ----- PIE2 bits --------------------
840 unsigned char EEIE:1;
841 unsigned char C1IE:1;
842 unsigned char C2IE:1;
843 unsigned char OSFIE:1;
846 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
848 #define EEIE PIE2_bits.EEIE
849 #define C1IE PIE2_bits.C1IE
850 #define C2IE PIE2_bits.C2IE
851 #define OSFIE PIE2_bits.OSFIE
853 // ----- PIR1 bits --------------------
856 unsigned char T1IF:1;
859 unsigned char SSPIF:1;
860 unsigned char TXIF:1;
861 unsigned char RCIF:1;
862 unsigned char ADIF:1;
866 unsigned char TMR1IF:1;
876 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
878 #define T1IF PIR1_bits.T1IF
879 #define TMR1IF PIR1_bits.TMR1IF
880 #define SSPIF PIR1_bits.SSPIF
881 #define TXIF PIR1_bits.TXIF
882 #define RCIF PIR1_bits.RCIF
883 #define ADIF PIR1_bits.ADIF
885 // ----- PIR2 bits --------------------
892 unsigned char EEIF:1;
893 unsigned char C1IF:1;
894 unsigned char C2IF:1;
895 unsigned char OSFIF:1;
898 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
900 #define EEIF PIR2_bits.EEIF
901 #define C1IF PIR2_bits.C1IF
902 #define C2IF PIR2_bits.C2IF
903 #define OSFIF PIR2_bits.OSFIF
905 // ----- PORTA bits --------------------
918 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
920 #define RA0 PORTA_bits.RA0
921 #define RA1 PORTA_bits.RA1
922 #define RA2 PORTA_bits.RA2
923 #define RA3 PORTA_bits.RA3
924 #define RA4 PORTA_bits.RA4
925 #define RA5 PORTA_bits.RA5
927 // ----- PORTB bits --------------------
940 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
942 #define RB0 PORTB_bits.RB0
943 #define RB1 PORTB_bits.RB1
944 #define RB2 PORTB_bits.RB2
945 #define RB3 PORTB_bits.RB3
946 #define RB4 PORTB_bits.RB4
947 #define RB5 PORTB_bits.RB5
948 #define RB6 PORTB_bits.RB6
949 #define RB7 PORTB_bits.RB7
951 // ----- PORTC bits --------------------
964 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
966 #define RC0 PORTC_bits.RC0
967 #define RC1 PORTC_bits.RC1
968 #define RC2 PORTC_bits.RC2
969 #define RC3 PORTC_bits.RC3
970 #define RC4 PORTC_bits.RC4
971 #define RC5 PORTC_bits.RC5
972 #define RC6 PORTC_bits.RC6
973 #define RC7 PORTC_bits.RC7
975 // ----- RCSTA bits --------------------
978 unsigned char RX9D:1;
979 unsigned char OERR:1;
980 unsigned char FERR:1;
981 unsigned char ADDEN:1;
982 unsigned char CREN:1;
983 unsigned char SREN:1;
985 unsigned char SPEN:1;
988 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
990 #define RX9D RCSTA_bits.RX9D
991 #define OERR RCSTA_bits.OERR
992 #define FERR RCSTA_bits.FERR
993 #define ADDEN RCSTA_bits.ADDEN
994 #define CREN RCSTA_bits.CREN
995 #define SREN RCSTA_bits.SREN
996 #define RX9 RCSTA_bits.RX9
997 #define SPEN RCSTA_bits.SPEN
999 // ----- SPBRG bits --------------------
1002 unsigned char BRG0:1;
1003 unsigned char BRG1:1;
1004 unsigned char BRG2:1;
1005 unsigned char BRG3:1;
1006 unsigned char BRG4:1;
1007 unsigned char BRG5:1;
1008 unsigned char BRG6:1;
1009 unsigned char BRG7:1;
1012 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
1014 #define BRG0 SPBRG_bits.BRG0
1015 #define BRG1 SPBRG_bits.BRG1
1016 #define BRG2 SPBRG_bits.BRG2
1017 #define BRG3 SPBRG_bits.BRG3
1018 #define BRG4 SPBRG_bits.BRG4
1019 #define BRG5 SPBRG_bits.BRG5
1020 #define BRG6 SPBRG_bits.BRG6
1021 #define BRG7 SPBRG_bits.BRG7
1023 // ----- SPBRGH bits --------------------
1026 unsigned char BRG8:1;
1027 unsigned char BRG9:1;
1028 unsigned char BRG10:1;
1029 unsigned char BRG11:1;
1030 unsigned char BRG12:1;
1031 unsigned char BRG13:1;
1032 unsigned char BRG14:1;
1033 unsigned char BRG15:1;
1036 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
1038 #define BRG8 SPBRGH_bits.BRG8
1039 #define BRG9 SPBRGH_bits.BRG9
1040 #define BRG10 SPBRGH_bits.BRG10
1041 #define BRG11 SPBRGH_bits.BRG11
1042 #define BRG12 SPBRGH_bits.BRG12
1043 #define BRG13 SPBRGH_bits.BRG13
1044 #define BRG14 SPBRGH_bits.BRG14
1045 #define BRG15 SPBRGH_bits.BRG15
1047 // ----- SRCON bits --------------------
1052 unsigned char PULSR:1;
1053 unsigned char PULSS:1;
1054 unsigned char C2REN:1;
1055 unsigned char C1SEN:1;
1056 unsigned char SR0:1;
1057 unsigned char SR1:1;
1060 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1062 #define PULSR SRCON_bits.PULSR
1063 #define PULSS SRCON_bits.PULSS
1064 #define C2REN SRCON_bits.C2REN
1065 #define C1SEN SRCON_bits.C1SEN
1066 #define SR0 SRCON_bits.SR0
1067 #define SR1 SRCON_bits.SR1
1069 // ----- SSPCON bits --------------------
1072 unsigned char SSPM0:1;
1073 unsigned char SSPM1:1;
1074 unsigned char SSPM2:1;
1075 unsigned char SSPM3:1;
1076 unsigned char CKP:1;
1077 unsigned char SSPEN:1;
1078 unsigned char SSPOV:1;
1079 unsigned char WCOL:1;
1082 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
1084 #define SSPM0 SSPCON_bits.SSPM0
1085 #define SSPM1 SSPCON_bits.SSPM1
1086 #define SSPM2 SSPCON_bits.SSPM2
1087 #define SSPM3 SSPCON_bits.SSPM3
1088 #define CKP SSPCON_bits.CKP
1089 #define SSPEN SSPCON_bits.SSPEN
1090 #define SSPOV SSPCON_bits.SSPOV
1091 #define WCOL SSPCON_bits.WCOL
1093 // ----- SSPSTAT bits --------------------
1102 unsigned char CKE:1;
1103 unsigned char SMP:1;
1108 unsigned char I2C_READ:1;
1109 unsigned char I2C_START:1;
1110 unsigned char I2C_STOP:1;
1111 unsigned char I2C_DATA:1;
1118 unsigned char NOT_W:1;
1121 unsigned char NOT_A:1;
1128 unsigned char NOT_WRITE:1;
1131 unsigned char NOT_ADDRESS:1;
1138 unsigned char R_W:1;
1141 unsigned char D_A:1;
1148 unsigned char READ_WRITE:1;
1151 unsigned char DATA_ADDRESS:1;
1156 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1158 #define BF SSPSTAT_bits.BF
1159 #define UA SSPSTAT_bits.UA
1160 #define R SSPSTAT_bits.R
1161 #define I2C_READ SSPSTAT_bits.I2C_READ
1162 #define NOT_W SSPSTAT_bits.NOT_W
1163 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
1164 #define R_W SSPSTAT_bits.R_W
1165 #define READ_WRITE SSPSTAT_bits.READ_WRITE
1166 #define S SSPSTAT_bits.S
1167 #define I2C_START SSPSTAT_bits.I2C_START
1168 #define P SSPSTAT_bits.P
1169 #define I2C_STOP SSPSTAT_bits.I2C_STOP
1170 #define D SSPSTAT_bits.D
1171 #define I2C_DATA SSPSTAT_bits.I2C_DATA
1172 #define NOT_A SSPSTAT_bits.NOT_A
1173 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
1174 #define D_A SSPSTAT_bits.D_A
1175 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
1176 #define CKE SSPSTAT_bits.CKE
1177 #define SMP SSPSTAT_bits.SMP
1179 // ----- STATUS bits --------------------
1185 unsigned char NOT_PD:1;
1186 unsigned char NOT_TO:1;
1187 unsigned char RP0:1;
1188 unsigned char RP1:1;
1189 unsigned char IRP:1;
1192 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1194 #define C STATUS_bits.C
1195 #define DC STATUS_bits.DC
1196 #define Z STATUS_bits.Z
1197 #define NOT_PD STATUS_bits.NOT_PD
1198 #define NOT_TO STATUS_bits.NOT_TO
1199 #define RP0 STATUS_bits.RP0
1200 #define RP1 STATUS_bits.RP1
1201 #define IRP STATUS_bits.IRP
1203 // ----- T1CON bits --------------------
1206 unsigned char TMR1ON:1;
1207 unsigned char TMR1CS:1;
1208 unsigned char NOT_T1SYNC:1;
1209 unsigned char T1OSCEN:1;
1210 unsigned char T1CKPS0:1;
1211 unsigned char T1CKPS1:1;
1212 unsigned char TMR1GE:1;
1213 unsigned char T1GINV:1;
1216 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1218 #define TMR1ON T1CON_bits.TMR1ON
1219 #define TMR1CS T1CON_bits.TMR1CS
1220 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1221 #define T1OSCEN T1CON_bits.T1OSCEN
1222 #define T1CKPS0 T1CON_bits.T1CKPS0
1223 #define T1CKPS1 T1CON_bits.T1CKPS1
1224 #define TMR1GE T1CON_bits.TMR1GE
1225 #define T1GINV T1CON_bits.T1GINV
1227 // ----- TRISA bits --------------------
1230 unsigned char TRISA0:1;
1231 unsigned char TRISA1:1;
1232 unsigned char TRISA2:1;
1233 unsigned char TRISA3:1;
1234 unsigned char TRISA4:1;
1235 unsigned char TRISA5:1;
1240 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1242 #define TRISA0 TRISA_bits.TRISA0
1243 #define TRISA1 TRISA_bits.TRISA1
1244 #define TRISA2 TRISA_bits.TRISA2
1245 #define TRISA3 TRISA_bits.TRISA3
1246 #define TRISA4 TRISA_bits.TRISA4
1247 #define TRISA5 TRISA_bits.TRISA5
1249 // ----- TRISB bits --------------------
1256 unsigned char TRISB4:1;
1257 unsigned char TRISB5:1;
1258 unsigned char TRISB6:1;
1259 unsigned char TRISB7:1;
1262 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1264 #define TRISB4 TRISB_bits.TRISB4
1265 #define TRISB5 TRISB_bits.TRISB5
1266 #define TRISB6 TRISB_bits.TRISB6
1267 #define TRISB7 TRISB_bits.TRISB7
1269 // ----- TRISC bits --------------------
1272 unsigned char TRISC0:1;
1273 unsigned char TRISC1:1;
1274 unsigned char TRISC2:1;
1275 unsigned char TRISC3:1;
1276 unsigned char TRISC4:1;
1277 unsigned char TRISC5:1;
1278 unsigned char TRISC6:1;
1279 unsigned char TRISC7:1;
1282 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1284 #define TRISC0 TRISC_bits.TRISC0
1285 #define TRISC1 TRISC_bits.TRISC1
1286 #define TRISC2 TRISC_bits.TRISC2
1287 #define TRISC3 TRISC_bits.TRISC3
1288 #define TRISC4 TRISC_bits.TRISC4
1289 #define TRISC5 TRISC_bits.TRISC5
1290 #define TRISC6 TRISC_bits.TRISC6
1291 #define TRISC7 TRISC_bits.TRISC7
1293 // ----- TXSTA bits --------------------
1296 unsigned char TX9D:1;
1297 unsigned char TRMT:1;
1298 unsigned char BRGH:1;
1299 unsigned char SENB:1;
1300 unsigned char SYNC:1;
1301 unsigned char TXEN:1;
1302 unsigned char TX9:1;
1303 unsigned char CSRC:1;
1306 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1308 #define TX9D TXSTA_bits.TX9D
1309 #define TRMT TXSTA_bits.TRMT
1310 #define BRGH TXSTA_bits.BRGH
1311 #define SENB TXSTA_bits.SENB
1312 #define SYNC TXSTA_bits.SYNC
1313 #define TXEN TXSTA_bits.TXEN
1314 #define TX9 TXSTA_bits.TX9
1315 #define CSRC TXSTA_bits.CSRC
1317 // ----- VRCON bits --------------------
1320 unsigned char VR0:1;
1321 unsigned char VR1:1;
1322 unsigned char VR2:1;
1323 unsigned char VR3:1;
1324 unsigned char VP6EN:1;
1325 unsigned char VRR:1;
1326 unsigned char C2VREN:1;
1327 unsigned char C1VREN:1;
1330 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1332 #define VR0 VRCON_bits.VR0
1333 #define VR1 VRCON_bits.VR1
1334 #define VR2 VRCON_bits.VR2
1335 #define VR3 VRCON_bits.VR3
1336 #define VP6EN VRCON_bits.VP6EN
1337 #define VRR VRCON_bits.VRR
1338 #define C2VREN VRCON_bits.C2VREN
1339 #define C1VREN VRCON_bits.C1VREN
1341 // ----- WDTCON bits --------------------
1344 unsigned char SWDTEN:1;
1345 unsigned char WDTPS0:1;
1346 unsigned char WDTPS1:1;
1347 unsigned char WDTPS2:1;
1348 unsigned char WDTPS3:1;
1354 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1356 #define SWDTEN WDTCON_bits.SWDTEN
1357 #define WDTPS0 WDTCON_bits.WDTPS0
1358 #define WDTPS1 WDTCON_bits.WDTPS1
1359 #define WDTPS2 WDTCON_bits.WDTPS2
1360 #define WDTPS3 WDTCON_bits.WDTPS3
1362 // ----- WPUA bits --------------------
1365 unsigned char WPUA0:1;
1366 unsigned char WPUA1:1;
1367 unsigned char WPUA2:1;
1369 unsigned char WPUA4:1;
1370 unsigned char WPUA5:1;
1375 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1377 #define WPUA0 WPUA_bits.WPUA0
1378 #define WPUA1 WPUA_bits.WPUA1
1379 #define WPUA2 WPUA_bits.WPUA2
1380 #define WPUA4 WPUA_bits.WPUA4
1381 #define WPUA5 WPUA_bits.WPUA5
1383 // ----- WPUB bits --------------------
1390 unsigned char WPUB4:1;
1391 unsigned char WPUB5:1;
1392 unsigned char WPUB6:1;
1393 unsigned char WPUB7:1;
1396 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1398 #define WPUB4 WPUB_bits.WPUB4
1399 #define WPUB5 WPUB_bits.WPUB5
1400 #define WPUB6 WPUB_bits.WPUB6
1401 #define WPUB7 WPUB_bits.WPUB7