2 // Register Declarations for Microchip 16F687 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define SSPBUF_ADDR 0x0013
44 #define SSPCON_ADDR 0x0014
45 #define RCSTA_ADDR 0x0018
46 #define TXREG_ADDR 0x0019
47 #define RCREG_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define SSPADD_ADDR 0x0093
60 #define MSK_ADDR 0x0093
61 #define SSPMSK_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define WPU_ADDR 0x0095
64 #define WPUA_ADDR 0x0095
65 #define IOC_ADDR 0x0096
66 #define IOCA_ADDR 0x0096
67 #define WDTCON_ADDR 0x0097
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define SPBRGH_ADDR 0x009A
71 #define BAUDCTL_ADDR 0x009B
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
74 #define EEDATA_ADDR 0x010C
75 #define EEADR_ADDR 0x010D
76 #define EEDATH_ADDR 0x010E
77 #define EEADRH_ADDR 0x010F
78 #define WPUB_ADDR 0x0115
79 #define IOCB_ADDR 0x0116
80 #define VRCON_ADDR 0x0118
81 #define CM1CON0_ADDR 0x0119
82 #define CM2CON0_ADDR 0x011A
83 #define CM2CON1_ADDR 0x011B
84 #define ANSEL_ADDR 0x011E
85 #define ANSELH_ADDR 0x011F
86 #define EECON1_ADDR 0x018C
87 #define EECON2_ADDR 0x018D
88 #define SRCON_ADDR 0x019E
91 // Memory organization.
97 // P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
100 // This header file defines configurations, registers, and other useful bits of
101 // information for the PIC16F687 microcontroller. These names are taken to match
102 // the data sheets as closely as possible.
104 // Note that the processor must be selected before this file is
105 // included. The processor may be selected the following ways:
107 // 1. Command line switch:
108 // C:\ MPASM MYFILE.ASM /PIC16F687
109 // 2. LIST directive in the source file
111 // 3. Processor Type entry in the MPASM full-screen interface
113 //==========================================================================
117 //==========================================================================
118 //1.00 10/12/04 Original
119 //==========================================================================
123 //==========================================================================
126 // MESSG "Processor-header file mismatch. Verify selected processor."
129 //==========================================================================
131 // Register Definitions
133 //==========================================================================
138 //----- Register Files------------------------------------------------------
140 extern __data __at (INDF_ADDR) volatile char INDF;
141 extern __sfr __at (TMR0_ADDR) TMR0;
142 extern __data __at (PCL_ADDR) volatile char PCL;
143 extern __sfr __at (STATUS_ADDR) STATUS;
144 extern __sfr __at (FSR_ADDR) FSR;
145 extern __sfr __at (PORTA_ADDR) PORTA;
146 extern __sfr __at (PORTB_ADDR) PORTB;
147 extern __sfr __at (PORTC_ADDR) PORTC;
149 extern __sfr __at (PCLATH_ADDR) PCLATH;
150 extern __sfr __at (INTCON_ADDR) INTCON;
151 extern __sfr __at (PIR1_ADDR) PIR1;
152 extern __sfr __at (PIR2_ADDR) PIR2;
153 extern __sfr __at (TMR1L_ADDR) TMR1L;
154 extern __sfr __at (TMR1H_ADDR) TMR1H;
155 extern __sfr __at (T1CON_ADDR) T1CON;
158 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
159 extern __sfr __at (SSPCON_ADDR) SSPCON;
162 extern __sfr __at (RCSTA_ADDR) RCSTA;
163 extern __sfr __at (TXREG_ADDR) TXREG;
164 extern __sfr __at (RCREG_ADDR) RCREG;
166 extern __sfr __at (ADRESH_ADDR) ADRESH;
167 extern __sfr __at (ADCON0_ADDR) ADCON0;
170 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
172 extern __sfr __at (TRISA_ADDR) TRISA;
173 extern __sfr __at (TRISB_ADDR) TRISB;
174 extern __sfr __at (TRISC_ADDR) TRISC;
176 extern __sfr __at (PIE1_ADDR) PIE1;
177 extern __sfr __at (PIE2_ADDR) PIE2;
178 extern __sfr __at (PCON_ADDR) PCON;
179 extern __sfr __at (OSCCON_ADDR) OSCCON;
180 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
182 extern __sfr __at (SSPADD_ADDR) SSPADD;
183 extern __sfr __at (MSK_ADDR) MSK;
184 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
185 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
186 extern __sfr __at (WPU_ADDR) WPU;
187 extern __sfr __at (WPUA_ADDR) WPUA;
188 extern __sfr __at (IOC_ADDR) IOC;
189 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (WDTCON_ADDR) WDTCON;
191 extern __sfr __at (TXSTA_ADDR) TXSTA;
192 extern __sfr __at (SPBRG_ADDR) SPBRG;
193 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
194 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
197 extern __sfr __at (ADRESL_ADDR) ADRESL;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
202 extern __sfr __at (EEDATA_ADDR) EEDATA;
203 extern __sfr __at (EEADR_ADDR) EEADR;
204 extern __sfr __at (EEDATH_ADDR) EEDATH;
205 extern __sfr __at (EEADRH_ADDR) EEADRH;
208 extern __sfr __at (WPUB_ADDR) WPUB;
209 extern __sfr __at (IOCB_ADDR) IOCB;
211 extern __sfr __at (VRCON_ADDR) VRCON;
212 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
213 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
214 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
216 extern __sfr __at (ANSEL_ADDR) ANSEL;
217 extern __sfr __at (ANSELH_ADDR) ANSELH;
219 extern __sfr __at (EECON1_ADDR) EECON1;
220 extern __sfr __at (EECON2_ADDR) EECON2;
223 extern __sfr __at (SRCON_ADDR) SRCON;
227 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
228 //----- STATUS Bits --------------------------------------------------------
231 //----- INTCON Bits --------------------------------------------------------
234 //----- PIR1 Bits ----------------------------------------------------------
239 //----- PIR2 Bits ----------------------------------------------------------
242 //----- T1CON Bits ---------------------------------------------------------
246 //----- SSPCON Bits -------------------------------------------------------
250 //----- RCSTA Bits ---------------------------------------------------------
254 //----- ADCON0 Bits --------------------------------------------------------
257 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
258 //----- OPTION Bits --------------------------------------------------------
261 //----- TRISA Bits --------------------------------------------------------
264 //----- TRISB Bits --------------------------------------------------------
267 //----- TRISC Bits --------------------------------------------------------
270 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PIE2 Bits ----------------------------------------------------------
278 //----- PCON Bits ----------------------------------------------------------
281 //----- OSCCON Bits --------------------------------------------------------
284 //----- OSCTUNE Bits -------------------------------------------------------
287 //----- SSPSTAT Bits --------------------------------------------------------
290 //----- WPUA --------------------------------------------------------------
294 //----- IOC --------------------------------------------------------------
297 //----- IOCA --------------------------------------------------------------
300 //----- WDTCON Bits --------------------------------------------------------
303 //----- TXSTA Bits -------------------------------------------------------
306 //----- SPBRG Bits -------------------------------------------------------
309 //----- SPBRGH Bits -------------------------------------------------------
312 //----- BAUDCTL Bits -------------------------------------------------------
317 //----- ADCON1 -------------------------------------------------------------
320 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
321 //----- WPUB Bits ----------------------------------------------------------
324 //----- IOCB --------------------------------------------------------------
327 //----- VRCON Bits ---------------------------------------------------------
330 //----- CM1CON0 Bits -------------------------------------------------------
334 //----- CM2CON0 Bits -------------------------------------------------------
338 //----- CM2CON1 Bits -------------------------------------------------------
341 //----- ANSEL --------------------------------------------------------------
344 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
345 //----- EECON1 -------------------------------------------------------------
348 //----- SRCON ---------------------------------------------------------------
351 //==========================================================================
355 //==========================================================================
358 // __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D'
359 // __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF'
360 // __BADRAM H'108'-H'109', H'10F'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F'
361 // __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF'
363 //==========================================================================
365 // Configuration Bits
367 //==========================================================================
369 #define _FCMEN_ON 0x3FFF
370 #define _FCMEN_OFF 0x37FF
371 #define _IESO_ON 0x3FFF
372 #define _IESO_OFF 0x3BFF
373 #define _BOD_ON 0x3FFF
374 #define _BOD_NSLEEP 0x3EFF
375 #define _BOD_SBODEN 0x3DFF
376 #define _BOD_OFF 0x3CFF
377 #define _CPD_ON 0x3F7F
378 #define _CPD_OFF 0x3FFF
379 #define _CP_ON 0x3FBF
380 #define _CP_OFF 0x3FFF
381 #define _MCLRE_ON 0x3FFF
382 #define _MCLRE_OFF 0x3FDF
383 #define _PWRTE_OFF 0x3FFF
384 #define _PWRTE_ON 0x3FEF
385 #define _WDT_ON 0x3FFF
386 #define _WDT_OFF 0x3FF7
387 #define _LP_OSC 0x3FF8
388 #define _XT_OSC 0x3FF9
389 #define _HS_OSC 0x3FFA
390 #define _EC_OSC 0x3FFB
391 #define _INTRC_OSC_NOCLKOUT 0x3FFC
392 #define _INTRC_OSC_CLKOUT 0x3FFD
393 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
394 #define _EXTRC_OSC_CLKOUT 0x3FFF
395 #define _INTOSCIO 0x3FFC
396 #define _INTOSC 0x3FFD
397 #define _EXTRCIO 0x3FFE
398 #define _EXTRC 0x3FFF
402 // ----- ADCON0 bits --------------------
405 unsigned char ADON:1;
407 unsigned char CHS0:1;
408 unsigned char CHS1:1;
409 unsigned char CHS2:1;
410 unsigned char CHS3:1;
411 unsigned char VCFG:1;
412 unsigned char ADFM:1;
416 unsigned char NOT_DONE:1;
426 unsigned char GO_DONE:1;
435 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
437 #define ADON ADCON0_bits.ADON
438 #define GO ADCON0_bits.GO
439 #define NOT_DONE ADCON0_bits.NOT_DONE
440 #define GO_DONE ADCON0_bits.GO_DONE
441 #define CHS0 ADCON0_bits.CHS0
442 #define CHS1 ADCON0_bits.CHS1
443 #define CHS2 ADCON0_bits.CHS2
444 #define CHS3 ADCON0_bits.CHS3
445 #define VCFG ADCON0_bits.VCFG
446 #define ADFM ADCON0_bits.ADFM
448 // ----- BAUDCTL bits --------------------
451 unsigned char ABDEN:1;
454 unsigned char BRG16:1;
455 unsigned char CKTXP:1;
456 unsigned char ADCS1:1;
457 unsigned char RCIDL:1;
458 unsigned char ABDOVF:1;
465 unsigned char ADCS0:1;
467 unsigned char ADCS2:1;
471 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
473 #define ABDEN BAUDCTL_bits.ABDEN
474 #define WUE BAUDCTL_bits.WUE
475 #define BRG16 BAUDCTL_bits.BRG16
476 #define CKTXP BAUDCTL_bits.CKTXP
477 #define ADCS0 BAUDCTL_bits.ADCS0
478 #define ADCS1 BAUDCTL_bits.ADCS1
479 #define RCIDL BAUDCTL_bits.RCIDL
480 #define ADCS2 BAUDCTL_bits.ADCS2
481 #define ABDOVF BAUDCTL_bits.ABDOVF
483 // ----- CM1CON0 bits --------------------
486 unsigned char C1CH0:1;
487 unsigned char C1CH1:1;
490 unsigned char C1POL:1;
491 unsigned char C1OE:1;
492 unsigned char C1OUT:1;
493 unsigned char C1ON:1;
496 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
498 #define C1CH0 CM1CON0_bits.C1CH0
499 #define C1CH1 CM1CON0_bits.C1CH1
500 #define C1R CM1CON0_bits.C1R
501 #define C1POL CM1CON0_bits.C1POL
502 #define C1OE CM1CON0_bits.C1OE
503 #define C1OUT CM1CON0_bits.C1OUT
504 #define C1ON CM1CON0_bits.C1ON
506 // ----- CM2CON0 bits --------------------
509 unsigned char C2CH0:1;
510 unsigned char C2CH1:1;
513 unsigned char C2POL:1;
514 unsigned char C2OE:1;
515 unsigned char C2OUT:1;
516 unsigned char C2ON:1;
519 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
521 #define C2CH0 CM2CON0_bits.C2CH0
522 #define C2CH1 CM2CON0_bits.C2CH1
523 #define C2R CM2CON0_bits.C2R
524 #define C2POL CM2CON0_bits.C2POL
525 #define C2OE CM2CON0_bits.C2OE
526 #define C2OUT CM2CON0_bits.C2OUT
527 #define C2ON CM2CON0_bits.C2ON
529 // ----- CM2CON1 bits --------------------
532 unsigned char C2SYNC:1;
533 unsigned char T1GSS:1;
534 unsigned char ANS2:1;
535 unsigned char ANS3:1;
536 unsigned char ANS4:1;
537 unsigned char ANS5:1;
538 unsigned char MC2OUT:1;
539 unsigned char MC1OUT:1;
542 unsigned char ANS0:1;
543 unsigned char ANS1:1;
544 unsigned char WREN:1;
545 unsigned char WRERR:1;
546 unsigned char C2REN:1;
547 unsigned char C1SEN:1;
548 unsigned char ANS6:1;
549 unsigned char ANS7:1;
554 unsigned char PULSR:1;
555 unsigned char PULSS:1;
559 unsigned char EEPGD:1;
572 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
574 #define C2SYNC CM2CON1_bits.C2SYNC
575 #define ANS0 CM2CON1_bits.ANS0
576 #define RD CM2CON1_bits.RD
577 #define T1GSS CM2CON1_bits.T1GSS
578 #define ANS1 CM2CON1_bits.ANS1
579 #define WR CM2CON1_bits.WR
580 #define ANS2 CM2CON1_bits.ANS2
581 #define WREN CM2CON1_bits.WREN
582 #define PULSR CM2CON1_bits.PULSR
583 #define ANS3 CM2CON1_bits.ANS3
584 #define WRERR CM2CON1_bits.WRERR
585 #define PULSS CM2CON1_bits.PULSS
586 #define ANS4 CM2CON1_bits.ANS4
587 #define C2REN CM2CON1_bits.C2REN
588 #define ANS5 CM2CON1_bits.ANS5
589 #define C1SEN CM2CON1_bits.C1SEN
590 #define MC2OUT CM2CON1_bits.MC2OUT
591 #define ANS6 CM2CON1_bits.ANS6
592 #define SR0 CM2CON1_bits.SR0
593 #define MC1OUT CM2CON1_bits.MC1OUT
594 #define ANS7 CM2CON1_bits.ANS7
595 #define EEPGD CM2CON1_bits.EEPGD
596 #define SR1 CM2CON1_bits.SR1
598 // ----- INTCON bits --------------------
601 unsigned char RABIF:1;
602 unsigned char INTF:1;
603 unsigned char T0IF:1;
604 unsigned char RABIE:1;
605 unsigned char INTE:1;
606 unsigned char T0IE:1;
607 unsigned char PEIE:1;
611 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
613 #define RABIF INTCON_bits.RABIF
614 #define INTF INTCON_bits.INTF
615 #define T0IF INTCON_bits.T0IF
616 #define RABIE INTCON_bits.RABIE
617 #define INTE INTCON_bits.INTE
618 #define T0IE INTCON_bits.T0IE
619 #define PEIE INTCON_bits.PEIE
620 #define GIE INTCON_bits.GIE
622 // ----- OPTION_REG bits --------------------
629 unsigned char T0SE:1;
630 unsigned char T0CS:1;
631 unsigned char INTEDG:1;
632 unsigned char NOT_RABPU:1;
634 } __OPTION_REG_bits_t;
635 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
637 #define PS0 OPTION_REG_bits.PS0
638 #define PS1 OPTION_REG_bits.PS1
639 #define PS2 OPTION_REG_bits.PS2
640 #define PSA OPTION_REG_bits.PSA
641 #define T0SE OPTION_REG_bits.T0SE
642 #define T0CS OPTION_REG_bits.T0CS
643 #define INTEDG OPTION_REG_bits.INTEDG
644 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
646 // ----- OSCCON bits --------------------
652 unsigned char OSTS:1;
653 unsigned char IRCF0:1;
654 unsigned char IRCF1:1;
655 unsigned char IRCF2:1;
659 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
661 #define SCS OSCCON_bits.SCS
662 #define LTS OSCCON_bits.LTS
663 #define HTS OSCCON_bits.HTS
664 #define OSTS OSCCON_bits.OSTS
665 #define IRCF0 OSCCON_bits.IRCF0
666 #define IRCF1 OSCCON_bits.IRCF1
667 #define IRCF2 OSCCON_bits.IRCF2
669 // ----- OSCTUNE bits --------------------
672 unsigned char TUN0:1;
673 unsigned char TUN1:1;
674 unsigned char TUN2:1;
675 unsigned char TUN3:1;
676 unsigned char TUN4:1;
682 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
684 #define TUN0 OSCTUNE_bits.TUN0
685 #define TUN1 OSCTUNE_bits.TUN1
686 #define TUN2 OSCTUNE_bits.TUN2
687 #define TUN3 OSCTUNE_bits.TUN3
688 #define TUN4 OSCTUNE_bits.TUN4
690 // ----- PCON bits --------------------
693 unsigned char NOT_BOD:1;
694 unsigned char NOT_POR:1;
697 unsigned char SBODEN:1;
698 unsigned char ULPWUE:1;
703 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
705 #define NOT_BOD PCON_bits.NOT_BOD
706 #define NOT_POR PCON_bits.NOT_POR
707 #define SBODEN PCON_bits.SBODEN
708 #define ULPWUE PCON_bits.ULPWUE
710 // ----- PIE1 bits --------------------
713 unsigned char T1IE:1;
716 unsigned char SSPIE:1;
717 unsigned char TXIE:1;
718 unsigned char RCIE:1;
719 unsigned char ADIE:1;
723 unsigned char TMR1IE:1;
733 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
735 #define T1IE PIE1_bits.T1IE
736 #define TMR1IE PIE1_bits.TMR1IE
737 #define SSPIE PIE1_bits.SSPIE
738 #define TXIE PIE1_bits.TXIE
739 #define RCIE PIE1_bits.RCIE
740 #define ADIE PIE1_bits.ADIE
742 // ----- PIE2 bits --------------------
749 unsigned char EEIE:1;
750 unsigned char C1IE:1;
751 unsigned char C2IE:1;
752 unsigned char OSFIE:1;
755 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
757 #define EEIE PIE2_bits.EEIE
758 #define C1IE PIE2_bits.C1IE
759 #define C2IE PIE2_bits.C2IE
760 #define OSFIE PIE2_bits.OSFIE
762 // ----- PIR1 bits --------------------
765 unsigned char T1IF:1;
768 unsigned char SSPIF:1;
769 unsigned char TXIF:1;
770 unsigned char RCIF:1;
771 unsigned char ADIF:1;
775 unsigned char TMR1IF:1;
785 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
787 #define T1IF PIR1_bits.T1IF
788 #define TMR1IF PIR1_bits.TMR1IF
789 #define SSPIF PIR1_bits.SSPIF
790 #define TXIF PIR1_bits.TXIF
791 #define RCIF PIR1_bits.RCIF
792 #define ADIF PIR1_bits.ADIF
794 // ----- PIR2 bits --------------------
801 unsigned char EEIF:1;
802 unsigned char C1IF:1;
803 unsigned char C2IF:1;
804 unsigned char OSFIF:1;
807 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
809 #define EEIF PIR2_bits.EEIF
810 #define C1IF PIR2_bits.C1IF
811 #define C2IF PIR2_bits.C2IF
812 #define OSFIF PIR2_bits.OSFIF
814 // ----- RCSTA bits --------------------
817 unsigned char RX9D:1;
818 unsigned char OERR:1;
819 unsigned char FERR:1;
820 unsigned char ADDEN:1;
821 unsigned char CREN:1;
822 unsigned char SREN:1;
824 unsigned char SPEN:1;
827 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
829 #define RX9D RCSTA_bits.RX9D
830 #define OERR RCSTA_bits.OERR
831 #define FERR RCSTA_bits.FERR
832 #define ADDEN RCSTA_bits.ADDEN
833 #define CREN RCSTA_bits.CREN
834 #define SREN RCSTA_bits.SREN
835 #define RX9 RCSTA_bits.RX9
836 #define SPEN RCSTA_bits.SPEN
838 // ----- SPBRG bits --------------------
841 unsigned char BRG0:1;
842 unsigned char BRG1:1;
843 unsigned char BRG2:1;
844 unsigned char BRG3:1;
845 unsigned char BRG4:1;
846 unsigned char BRG5:1;
847 unsigned char BRG6:1;
848 unsigned char BRG7:1;
851 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
853 #define BRG0 SPBRG_bits.BRG0
854 #define BRG1 SPBRG_bits.BRG1
855 #define BRG2 SPBRG_bits.BRG2
856 #define BRG3 SPBRG_bits.BRG3
857 #define BRG4 SPBRG_bits.BRG4
858 #define BRG5 SPBRG_bits.BRG5
859 #define BRG6 SPBRG_bits.BRG6
860 #define BRG7 SPBRG_bits.BRG7
862 // ----- SPBRGH bits --------------------
865 unsigned char BRG8:1;
866 unsigned char BRG9:1;
867 unsigned char BRG10:1;
868 unsigned char BRG11:1;
869 unsigned char BRG12:1;
870 unsigned char BRG13:1;
871 unsigned char BRG14:1;
872 unsigned char BRG15:1;
875 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
877 #define BRG8 SPBRGH_bits.BRG8
878 #define BRG9 SPBRGH_bits.BRG9
879 #define BRG10 SPBRGH_bits.BRG10
880 #define BRG11 SPBRGH_bits.BRG11
881 #define BRG12 SPBRGH_bits.BRG12
882 #define BRG13 SPBRGH_bits.BRG13
883 #define BRG14 SPBRGH_bits.BRG14
884 #define BRG15 SPBRGH_bits.BRG15
886 // ----- SSPCON bits --------------------
889 unsigned char SSPM0:1;
890 unsigned char SSPM1:1;
891 unsigned char SSPM2:1;
892 unsigned char SSPM3:1;
894 unsigned char SSPEN:1;
895 unsigned char SSPOV:1;
896 unsigned char WCOL:1;
899 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
901 #define SSPM0 SSPCON_bits.SSPM0
902 #define SSPM1 SSPCON_bits.SSPM1
903 #define SSPM2 SSPCON_bits.SSPM2
904 #define SSPM3 SSPCON_bits.SSPM3
905 #define CKP SSPCON_bits.CKP
906 #define SSPEN SSPCON_bits.SSPEN
907 #define SSPOV SSPCON_bits.SSPOV
908 #define WCOL SSPCON_bits.WCOL
910 // ----- SSPSTAT bits --------------------
915 unsigned char R_W_NOT:1;
918 unsigned char D_A_NOT:1;
923 unsigned char WPUA0:1;
924 unsigned char WPUA1:1;
925 unsigned char WPUA2:1;
926 unsigned char IOC3:1;
927 unsigned char WPUA4:1;
928 unsigned char WPUA5:1;
933 unsigned char IOC0:1;
934 unsigned char IOC1:1;
935 unsigned char IOC2:1;
936 unsigned char IOCA3:1;
937 unsigned char IOC4:1;
938 unsigned char IOC5:1;
943 unsigned char IOCA0:1;
944 unsigned char IOCA1:1;
945 unsigned char IOCA2:1;
947 unsigned char IOCA4:1;
948 unsigned char IOCA5:1;
953 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
955 #define BF SSPSTAT_bits.BF
956 #define WPUA0 SSPSTAT_bits.WPUA0
957 #define IOC0 SSPSTAT_bits.IOC0
958 #define IOCA0 SSPSTAT_bits.IOCA0
959 #define UA SSPSTAT_bits.UA
960 #define WPUA1 SSPSTAT_bits.WPUA1
961 #define IOC1 SSPSTAT_bits.IOC1
962 #define IOCA1 SSPSTAT_bits.IOCA1
963 #define R_W_NOT SSPSTAT_bits.R_W_NOT
964 #define WPUA2 SSPSTAT_bits.WPUA2
965 #define IOC2 SSPSTAT_bits.IOC2
966 #define IOCA2 SSPSTAT_bits.IOCA2
967 #define S SSPSTAT_bits.S
968 #define IOC3 SSPSTAT_bits.IOC3
969 #define IOCA3 SSPSTAT_bits.IOCA3
970 #define P SSPSTAT_bits.P
971 #define WPUA4 SSPSTAT_bits.WPUA4
972 #define IOC4 SSPSTAT_bits.IOC4
973 #define IOCA4 SSPSTAT_bits.IOCA4
974 #define D_A_NOT SSPSTAT_bits.D_A_NOT
975 #define WPUA5 SSPSTAT_bits.WPUA5
976 #define IOC5 SSPSTAT_bits.IOC5
977 #define IOCA5 SSPSTAT_bits.IOCA5
978 #define CKE SSPSTAT_bits.CKE
979 #define SMP SSPSTAT_bits.SMP
981 // ----- STATUS bits --------------------
987 unsigned char NOT_PD:1;
988 unsigned char NOT_TO:1;
994 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
996 #define C STATUS_bits.C
997 #define DC STATUS_bits.DC
998 #define Z STATUS_bits.Z
999 #define NOT_PD STATUS_bits.NOT_PD
1000 #define NOT_TO STATUS_bits.NOT_TO
1001 #define RP0 STATUS_bits.RP0
1002 #define RP1 STATUS_bits.RP1
1003 #define IRP STATUS_bits.IRP
1005 // ----- T1CON bits --------------------
1008 unsigned char TMR1ON:1;
1009 unsigned char TMR1CS:1;
1010 unsigned char NOT_T1SYNC:1;
1011 unsigned char T1OSCEN:1;
1012 unsigned char T1CKPS0:1;
1013 unsigned char T1CKPS1:1;
1014 unsigned char TMR1GE:1;
1015 unsigned char T1GINV:1;
1018 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1020 #define TMR1ON T1CON_bits.TMR1ON
1021 #define TMR1CS T1CON_bits.TMR1CS
1022 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1023 #define T1OSCEN T1CON_bits.T1OSCEN
1024 #define T1CKPS0 T1CON_bits.T1CKPS0
1025 #define T1CKPS1 T1CON_bits.T1CKPS1
1026 #define TMR1GE T1CON_bits.TMR1GE
1027 #define T1GINV T1CON_bits.T1GINV
1029 // ----- TRISA bits --------------------
1032 unsigned char TRISA0:1;
1033 unsigned char TRISA1:1;
1034 unsigned char TRISA2:1;
1035 unsigned char TRISA3:1;
1036 unsigned char TRISA4:1;
1037 unsigned char TRISA5:1;
1042 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1044 #define TRISA0 TRISA_bits.TRISA0
1045 #define TRISA1 TRISA_bits.TRISA1
1046 #define TRISA2 TRISA_bits.TRISA2
1047 #define TRISA3 TRISA_bits.TRISA3
1048 #define TRISA4 TRISA_bits.TRISA4
1049 #define TRISA5 TRISA_bits.TRISA5
1051 // ----- TRISB bits --------------------
1058 unsigned char TRISB4:1;
1059 unsigned char TRISB5:1;
1060 unsigned char TRISB6:1;
1061 unsigned char TRISB7:1;
1064 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1066 #define TRISB4 TRISB_bits.TRISB4
1067 #define TRISB5 TRISB_bits.TRISB5
1068 #define TRISB6 TRISB_bits.TRISB6
1069 #define TRISB7 TRISB_bits.TRISB7
1071 // ----- TRISC bits --------------------
1074 unsigned char TRISC0:1;
1075 unsigned char TRISC1:1;
1076 unsigned char TRISC2:1;
1077 unsigned char TRISC3:1;
1078 unsigned char TRISC4:1;
1079 unsigned char TRISC5:1;
1080 unsigned char TRISC6:1;
1081 unsigned char TRISC7:1;
1084 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1086 #define TRISC0 TRISC_bits.TRISC0
1087 #define TRISC1 TRISC_bits.TRISC1
1088 #define TRISC2 TRISC_bits.TRISC2
1089 #define TRISC3 TRISC_bits.TRISC3
1090 #define TRISC4 TRISC_bits.TRISC4
1091 #define TRISC5 TRISC_bits.TRISC5
1092 #define TRISC6 TRISC_bits.TRISC6
1093 #define TRISC7 TRISC_bits.TRISC7
1095 // ----- TXSTA bits --------------------
1098 unsigned char TX9D:1;
1099 unsigned char TRMT:1;
1100 unsigned char BRGH:1;
1101 unsigned char SENB:1;
1102 unsigned char SYNC:1;
1103 unsigned char TXEN:1;
1104 unsigned char TX9:1;
1105 unsigned char CSRC:1;
1108 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1110 #define TX9D TXSTA_bits.TX9D
1111 #define TRMT TXSTA_bits.TRMT
1112 #define BRGH TXSTA_bits.BRGH
1113 #define SENB TXSTA_bits.SENB
1114 #define SYNC TXSTA_bits.SYNC
1115 #define TXEN TXSTA_bits.TXEN
1116 #define TX9 TXSTA_bits.TX9
1117 #define CSRC TXSTA_bits.CSRC
1119 // ----- VRCON bits --------------------
1122 unsigned char VR0:1;
1123 unsigned char VR1:1;
1124 unsigned char VR2:1;
1125 unsigned char VR3:1;
1126 unsigned char VP6EN:1;
1127 unsigned char VRR:1;
1128 unsigned char C2VREN:1;
1129 unsigned char C1VREN:1;
1132 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1134 #define VR0 VRCON_bits.VR0
1135 #define VR1 VRCON_bits.VR1
1136 #define VR2 VRCON_bits.VR2
1137 #define VR3 VRCON_bits.VR3
1138 #define VP6EN VRCON_bits.VP6EN
1139 #define VRR VRCON_bits.VRR
1140 #define C2VREN VRCON_bits.C2VREN
1141 #define C1VREN VRCON_bits.C1VREN
1143 // ----- WDTCON bits --------------------
1146 unsigned char SWDTEN:1;
1147 unsigned char WDTPS0:1;
1148 unsigned char WDTPS1:1;
1149 unsigned char WDTPS2:1;
1150 unsigned char WDTPS3:1;
1156 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1158 #define SWDTEN WDTCON_bits.SWDTEN
1159 #define WDTPS0 WDTCON_bits.WDTPS0
1160 #define WDTPS1 WDTCON_bits.WDTPS1
1161 #define WDTPS2 WDTCON_bits.WDTPS2
1162 #define WDTPS3 WDTCON_bits.WDTPS3
1164 // ----- WPUB bits --------------------
1171 unsigned char WPUB4:1;
1172 unsigned char WPUB5:1;
1173 unsigned char WPUB6:1;
1174 unsigned char WPUB7:1;
1181 unsigned char IOCB4:1;
1182 unsigned char IOCB5:1;
1183 unsigned char IOCB6:1;
1184 unsigned char IOCB7:1;
1187 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1189 #define WPUB4 WPUB_bits.WPUB4
1190 #define IOCB4 WPUB_bits.IOCB4
1191 #define WPUB5 WPUB_bits.WPUB5
1192 #define IOCB5 WPUB_bits.IOCB5
1193 #define WPUB6 WPUB_bits.WPUB6
1194 #define IOCB6 WPUB_bits.IOCB6
1195 #define WPUB7 WPUB_bits.WPUB7
1196 #define IOCB7 WPUB_bits.IOCB7