2 // Register Declarations for Microchip 16F687 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define SSPBUF_ADDR 0x0013
44 #define SSPCON_ADDR 0x0014
45 #define RCSTA_ADDR 0x0018
46 #define TXREG_ADDR 0x0019
47 #define RCREG_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define TRISC_ADDR 0x0087
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define OSCCON_ADDR 0x008F
58 #define OSCTUNE_ADDR 0x0090
59 #define SSPADD_ADDR 0x0093
60 #define MSK_ADDR 0x0093
61 #define SSPMSK_ADDR 0x0093
62 #define SSPSTAT_ADDR 0x0094
63 #define WPU_ADDR 0x0095
64 #define WPUA_ADDR 0x0095
65 #define IOC_ADDR 0x0096
66 #define IOCA_ADDR 0x0096
67 #define WDTCON_ADDR 0x0097
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define SPBRGH_ADDR 0x009A
71 #define BAUDCTL_ADDR 0x009B
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
74 #define EEDATA_ADDR 0x010C
75 #define EEADR_ADDR 0x010D
76 #define EEDATH_ADDR 0x010E
77 #define EEADRH_ADDR 0x010F
78 #define WPUB_ADDR 0x0115
79 #define IOCB_ADDR 0x0116
80 #define VRCON_ADDR 0x0118
81 #define CM1CON0_ADDR 0x0119
82 #define CM2CON0_ADDR 0x011A
83 #define CM2CON1_ADDR 0x011B
84 #define ANSEL_ADDR 0x011E
85 #define ANSELH_ADDR 0x011F
86 #define EECON1_ADDR 0x018C
87 #define EECON2_ADDR 0x018D
88 #define SRCON_ADDR 0x019E
91 // Memory organization.
94 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
95 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
96 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
97 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
98 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
99 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
100 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
101 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
102 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
103 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
104 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
105 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
106 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
107 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
108 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
109 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
110 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
111 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
112 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
113 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
114 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
115 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
116 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
117 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
118 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
119 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
120 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
121 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
122 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
123 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
124 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
125 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
126 #pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK
127 #pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK
128 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
129 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
130 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
131 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
132 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
133 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
134 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
135 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
136 #pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH
137 #pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL
138 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
139 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
140 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
141 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
142 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
143 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
144 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
145 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
146 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
147 #pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
148 #pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
149 #pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
150 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
151 #pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH
152 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
153 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
154 #pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON
158 // P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
161 // This header file defines configurations, registers, and other useful bits of
162 // information for the PIC16F687 microcontroller. These names are taken to match
163 // the data sheets as closely as possible.
165 // Note that the processor must be selected before this file is
166 // included. The processor may be selected the following ways:
168 // 1. Command line switch:
169 // C:\ MPASM MYFILE.ASM /PIC16F687
170 // 2. LIST directive in the source file
172 // 3. Processor Type entry in the MPASM full-screen interface
174 //==========================================================================
178 //==========================================================================
179 //1.00 10/12/04 Original
180 //==========================================================================
184 //==========================================================================
187 // MESSG "Processor-header file mismatch. Verify selected processor."
190 //==========================================================================
192 // Register Definitions
194 //==========================================================================
199 //----- Register Files------------------------------------------------------
201 extern __data __at (INDF_ADDR) volatile char INDF;
202 extern __sfr __at (TMR0_ADDR) TMR0;
203 extern __data __at (PCL_ADDR) volatile char PCL;
204 extern __sfr __at (STATUS_ADDR) STATUS;
205 extern __sfr __at (FSR_ADDR) FSR;
206 extern __sfr __at (PORTA_ADDR) PORTA;
207 extern __sfr __at (PORTB_ADDR) PORTB;
208 extern __sfr __at (PORTC_ADDR) PORTC;
210 extern __sfr __at (PCLATH_ADDR) PCLATH;
211 extern __sfr __at (INTCON_ADDR) INTCON;
212 extern __sfr __at (PIR1_ADDR) PIR1;
213 extern __sfr __at (PIR2_ADDR) PIR2;
214 extern __sfr __at (TMR1L_ADDR) TMR1L;
215 extern __sfr __at (TMR1H_ADDR) TMR1H;
216 extern __sfr __at (T1CON_ADDR) T1CON;
219 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
220 extern __sfr __at (SSPCON_ADDR) SSPCON;
223 extern __sfr __at (RCSTA_ADDR) RCSTA;
224 extern __sfr __at (TXREG_ADDR) TXREG;
225 extern __sfr __at (RCREG_ADDR) RCREG;
227 extern __sfr __at (ADRESH_ADDR) ADRESH;
228 extern __sfr __at (ADCON0_ADDR) ADCON0;
231 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
233 extern __sfr __at (TRISA_ADDR) TRISA;
234 extern __sfr __at (TRISB_ADDR) TRISB;
235 extern __sfr __at (TRISC_ADDR) TRISC;
237 extern __sfr __at (PIE1_ADDR) PIE1;
238 extern __sfr __at (PIE2_ADDR) PIE2;
239 extern __sfr __at (PCON_ADDR) PCON;
240 extern __sfr __at (OSCCON_ADDR) OSCCON;
241 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
243 extern __sfr __at (SSPADD_ADDR) SSPADD;
244 extern __sfr __at (MSK_ADDR) MSK;
245 extern __sfr __at (SSPMSK_ADDR) SSPMSK;
246 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
247 extern __sfr __at (WPU_ADDR) WPU;
248 extern __sfr __at (WPUA_ADDR) WPUA;
249 extern __sfr __at (IOC_ADDR) IOC;
250 extern __sfr __at (IOCA_ADDR) IOCA;
251 extern __sfr __at (WDTCON_ADDR) WDTCON;
252 extern __sfr __at (TXSTA_ADDR) TXSTA;
253 extern __sfr __at (SPBRG_ADDR) SPBRG;
254 extern __sfr __at (SPBRGH_ADDR) SPBRGH;
255 extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
258 extern __sfr __at (ADRESL_ADDR) ADRESL;
259 extern __sfr __at (ADCON1_ADDR) ADCON1;
263 extern __sfr __at (EEDATA_ADDR) EEDATA;
264 extern __sfr __at (EEADR_ADDR) EEADR;
265 extern __sfr __at (EEDATH_ADDR) EEDATH;
266 extern __sfr __at (EEADRH_ADDR) EEADRH;
269 extern __sfr __at (WPUB_ADDR) WPUB;
270 extern __sfr __at (IOCB_ADDR) IOCB;
272 extern __sfr __at (VRCON_ADDR) VRCON;
273 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
274 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
275 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
277 extern __sfr __at (ANSEL_ADDR) ANSEL;
278 extern __sfr __at (ANSELH_ADDR) ANSELH;
280 extern __sfr __at (EECON1_ADDR) EECON1;
281 extern __sfr __at (EECON2_ADDR) EECON2;
284 extern __sfr __at (SRCON_ADDR) SRCON;
288 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
289 //----- STATUS Bits --------------------------------------------------------
292 //----- INTCON Bits --------------------------------------------------------
295 //----- PIR1 Bits ----------------------------------------------------------
300 //----- PIR2 Bits ----------------------------------------------------------
303 //----- T1CON Bits ---------------------------------------------------------
307 //----- SSPCON Bits -------------------------------------------------------
311 //----- RCSTA Bits ---------------------------------------------------------
315 //----- ADCON0 Bits --------------------------------------------------------
318 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
319 //----- OPTION Bits --------------------------------------------------------
322 //----- TRISA Bits --------------------------------------------------------
325 //----- TRISB Bits --------------------------------------------------------
328 //----- TRISC Bits --------------------------------------------------------
331 //----- PIE1 Bits ----------------------------------------------------------
336 //----- PIE2 Bits ----------------------------------------------------------
339 //----- PCON Bits ----------------------------------------------------------
342 //----- OSCCON Bits --------------------------------------------------------
345 //----- OSCTUNE Bits -------------------------------------------------------
348 //----- SSPSTAT Bits --------------------------------------------------------
351 //----- WPUA --------------------------------------------------------------
355 //----- IOC --------------------------------------------------------------
358 //----- IOCA --------------------------------------------------------------
361 //----- WDTCON Bits --------------------------------------------------------
364 //----- TXSTA Bits -------------------------------------------------------
367 //----- SPBRG Bits -------------------------------------------------------
370 //----- SPBRGH Bits -------------------------------------------------------
373 //----- BAUDCTL Bits -------------------------------------------------------
378 //----- ADCON1 -------------------------------------------------------------
381 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
382 //----- WPUB Bits ----------------------------------------------------------
385 //----- IOCB --------------------------------------------------------------
388 //----- VRCON Bits ---------------------------------------------------------
391 //----- CM1CON0 Bits -------------------------------------------------------
395 //----- CM2CON0 Bits -------------------------------------------------------
399 //----- CM2CON1 Bits -------------------------------------------------------
402 //----- ANSEL --------------------------------------------------------------
405 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
406 //----- EECON1 -------------------------------------------------------------
409 //----- SRCON ---------------------------------------------------------------
412 //==========================================================================
416 //==========================================================================
419 // __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D'
420 // __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF'
421 // __BADRAM H'108'-H'109', H'10F'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F'
422 // __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF'
424 //==========================================================================
426 // Configuration Bits
428 //==========================================================================
430 #define _FCMEN_ON 0x3FFF
431 #define _FCMEN_OFF 0x37FF
432 #define _IESO_ON 0x3FFF
433 #define _IESO_OFF 0x3BFF
434 #define _BOD_ON 0x3FFF
435 #define _BOD_NSLEEP 0x3EFF
436 #define _BOD_SBODEN 0x3DFF
437 #define _BOD_OFF 0x3CFF
438 #define _CPD_ON 0x3F7F
439 #define _CPD_OFF 0x3FFF
440 #define _CP_ON 0x3FBF
441 #define _CP_OFF 0x3FFF
442 #define _MCLRE_ON 0x3FFF
443 #define _MCLRE_OFF 0x3FDF
444 #define _PWRTE_OFF 0x3FFF
445 #define _PWRTE_ON 0x3FEF
446 #define _WDT_ON 0x3FFF
447 #define _WDT_OFF 0x3FF7
448 #define _LP_OSC 0x3FF8
449 #define _XT_OSC 0x3FF9
450 #define _HS_OSC 0x3FFA
451 #define _EC_OSC 0x3FFB
452 #define _INTRC_OSC_NOCLKOUT 0x3FFC
453 #define _INTRC_OSC_CLKOUT 0x3FFD
454 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
455 #define _EXTRC_OSC_CLKOUT 0x3FFF
456 #define _INTOSCIO 0x3FFC
457 #define _INTOSC 0x3FFD
458 #define _EXTRCIO 0x3FFE
459 #define _EXTRC 0x3FFF
463 // ----- ADCON0 bits --------------------
466 unsigned char ADON:1;
468 unsigned char CHS0:1;
469 unsigned char CHS1:1;
470 unsigned char CHS2:1;
471 unsigned char CHS3:1;
472 unsigned char VCFG:1;
473 unsigned char ADFM:1;
477 unsigned char NOT_DONE:1;
487 unsigned char GO_DONE:1;
496 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
498 #define ADON ADCON0_bits.ADON
499 #define GO ADCON0_bits.GO
500 #define NOT_DONE ADCON0_bits.NOT_DONE
501 #define GO_DONE ADCON0_bits.GO_DONE
502 #define CHS0 ADCON0_bits.CHS0
503 #define CHS1 ADCON0_bits.CHS1
504 #define CHS2 ADCON0_bits.CHS2
505 #define CHS3 ADCON0_bits.CHS3
506 #define VCFG ADCON0_bits.VCFG
507 #define ADFM ADCON0_bits.ADFM
509 // ----- BAUDCTL bits --------------------
512 unsigned char ABDEN:1;
515 unsigned char BRG16:1;
516 unsigned char CKTXP:1;
517 unsigned char ADCS1:1;
518 unsigned char RCIDL:1;
519 unsigned char ABDOVF:1;
526 unsigned char ADCS0:1;
528 unsigned char ADCS2:1;
532 extern volatile __BAUDCTL_bits_t __at(BAUDCTL_ADDR) BAUDCTL_bits;
534 #define ABDEN BAUDCTL_bits.ABDEN
535 #define WUE BAUDCTL_bits.WUE
536 #define BRG16 BAUDCTL_bits.BRG16
537 #define CKTXP BAUDCTL_bits.CKTXP
538 #define ADCS0 BAUDCTL_bits.ADCS0
539 #define ADCS1 BAUDCTL_bits.ADCS1
540 #define RCIDL BAUDCTL_bits.RCIDL
541 #define ADCS2 BAUDCTL_bits.ADCS2
542 #define ABDOVF BAUDCTL_bits.ABDOVF
544 // ----- CM1CON0 bits --------------------
547 unsigned char C1CH0:1;
548 unsigned char C1CH1:1;
551 unsigned char C1POL:1;
552 unsigned char C1OE:1;
553 unsigned char C1OUT:1;
554 unsigned char C1ON:1;
557 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
559 #define C1CH0 CM1CON0_bits.C1CH0
560 #define C1CH1 CM1CON0_bits.C1CH1
561 #define C1R CM1CON0_bits.C1R
562 #define C1POL CM1CON0_bits.C1POL
563 #define C1OE CM1CON0_bits.C1OE
564 #define C1OUT CM1CON0_bits.C1OUT
565 #define C1ON CM1CON0_bits.C1ON
567 // ----- CM2CON0 bits --------------------
570 unsigned char C2CH0:1;
571 unsigned char C2CH1:1;
574 unsigned char C2POL:1;
575 unsigned char C2OE:1;
576 unsigned char C2OUT:1;
577 unsigned char C2ON:1;
580 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
582 #define C2CH0 CM2CON0_bits.C2CH0
583 #define C2CH1 CM2CON0_bits.C2CH1
584 #define C2R CM2CON0_bits.C2R
585 #define C2POL CM2CON0_bits.C2POL
586 #define C2OE CM2CON0_bits.C2OE
587 #define C2OUT CM2CON0_bits.C2OUT
588 #define C2ON CM2CON0_bits.C2ON
590 // ----- CM2CON1 bits --------------------
593 unsigned char C2SYNC:1;
594 unsigned char T1GSS:1;
595 unsigned char ANS2:1;
596 unsigned char ANS3:1;
597 unsigned char ANS4:1;
598 unsigned char ANS5:1;
599 unsigned char MC2OUT:1;
600 unsigned char MC1OUT:1;
603 unsigned char ANS0:1;
604 unsigned char ANS1:1;
605 unsigned char WREN:1;
606 unsigned char WRERR:1;
607 unsigned char C2REN:1;
608 unsigned char C1SEN:1;
609 unsigned char ANS6:1;
610 unsigned char ANS7:1;
615 unsigned char PULSR:1;
616 unsigned char PULSS:1;
620 unsigned char EEPGD:1;
633 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
635 #define C2SYNC CM2CON1_bits.C2SYNC
636 #define ANS0 CM2CON1_bits.ANS0
637 #define RD CM2CON1_bits.RD
638 #define T1GSS CM2CON1_bits.T1GSS
639 #define ANS1 CM2CON1_bits.ANS1
640 #define WR CM2CON1_bits.WR
641 #define ANS2 CM2CON1_bits.ANS2
642 #define WREN CM2CON1_bits.WREN
643 #define PULSR CM2CON1_bits.PULSR
644 #define ANS3 CM2CON1_bits.ANS3
645 #define WRERR CM2CON1_bits.WRERR
646 #define PULSS CM2CON1_bits.PULSS
647 #define ANS4 CM2CON1_bits.ANS4
648 #define C2REN CM2CON1_bits.C2REN
649 #define ANS5 CM2CON1_bits.ANS5
650 #define C1SEN CM2CON1_bits.C1SEN
651 #define MC2OUT CM2CON1_bits.MC2OUT
652 #define ANS6 CM2CON1_bits.ANS6
653 #define SR0 CM2CON1_bits.SR0
654 #define MC1OUT CM2CON1_bits.MC1OUT
655 #define ANS7 CM2CON1_bits.ANS7
656 #define EEPGD CM2CON1_bits.EEPGD
657 #define SR1 CM2CON1_bits.SR1
659 // ----- INTCON bits --------------------
662 unsigned char RABIF:1;
663 unsigned char INTF:1;
664 unsigned char T0IF:1;
665 unsigned char RABIE:1;
666 unsigned char INTE:1;
667 unsigned char T0IE:1;
668 unsigned char PEIE:1;
672 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
674 #define RABIF INTCON_bits.RABIF
675 #define INTF INTCON_bits.INTF
676 #define T0IF INTCON_bits.T0IF
677 #define RABIE INTCON_bits.RABIE
678 #define INTE INTCON_bits.INTE
679 #define T0IE INTCON_bits.T0IE
680 #define PEIE INTCON_bits.PEIE
681 #define GIE INTCON_bits.GIE
683 // ----- OPTION_REG bits --------------------
690 unsigned char T0SE:1;
691 unsigned char T0CS:1;
692 unsigned char INTEDG:1;
693 unsigned char NOT_RABPU:1;
695 } __OPTION_REG_bits_t;
696 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
698 #define PS0 OPTION_REG_bits.PS0
699 #define PS1 OPTION_REG_bits.PS1
700 #define PS2 OPTION_REG_bits.PS2
701 #define PSA OPTION_REG_bits.PSA
702 #define T0SE OPTION_REG_bits.T0SE
703 #define T0CS OPTION_REG_bits.T0CS
704 #define INTEDG OPTION_REG_bits.INTEDG
705 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
707 // ----- OSCCON bits --------------------
713 unsigned char OSTS:1;
714 unsigned char IRCF0:1;
715 unsigned char IRCF1:1;
716 unsigned char IRCF2:1;
720 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
722 #define SCS OSCCON_bits.SCS
723 #define LTS OSCCON_bits.LTS
724 #define HTS OSCCON_bits.HTS
725 #define OSTS OSCCON_bits.OSTS
726 #define IRCF0 OSCCON_bits.IRCF0
727 #define IRCF1 OSCCON_bits.IRCF1
728 #define IRCF2 OSCCON_bits.IRCF2
730 // ----- OSCTUNE bits --------------------
733 unsigned char TUN0:1;
734 unsigned char TUN1:1;
735 unsigned char TUN2:1;
736 unsigned char TUN3:1;
737 unsigned char TUN4:1;
743 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
745 #define TUN0 OSCTUNE_bits.TUN0
746 #define TUN1 OSCTUNE_bits.TUN1
747 #define TUN2 OSCTUNE_bits.TUN2
748 #define TUN3 OSCTUNE_bits.TUN3
749 #define TUN4 OSCTUNE_bits.TUN4
751 // ----- PCON bits --------------------
754 unsigned char NOT_BOD:1;
755 unsigned char NOT_POR:1;
758 unsigned char SBODEN:1;
759 unsigned char ULPWUE:1;
764 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
766 #define NOT_BOD PCON_bits.NOT_BOD
767 #define NOT_POR PCON_bits.NOT_POR
768 #define SBODEN PCON_bits.SBODEN
769 #define ULPWUE PCON_bits.ULPWUE
771 // ----- PIE1 bits --------------------
774 unsigned char T1IE:1;
777 unsigned char SSPIE:1;
778 unsigned char TXIE:1;
779 unsigned char RCIE:1;
780 unsigned char ADIE:1;
784 unsigned char TMR1IE:1;
794 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
796 #define T1IE PIE1_bits.T1IE
797 #define TMR1IE PIE1_bits.TMR1IE
798 #define SSPIE PIE1_bits.SSPIE
799 #define TXIE PIE1_bits.TXIE
800 #define RCIE PIE1_bits.RCIE
801 #define ADIE PIE1_bits.ADIE
803 // ----- PIE2 bits --------------------
810 unsigned char EEIE:1;
811 unsigned char C1IE:1;
812 unsigned char C2IE:1;
813 unsigned char OSFIE:1;
816 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
818 #define EEIE PIE2_bits.EEIE
819 #define C1IE PIE2_bits.C1IE
820 #define C2IE PIE2_bits.C2IE
821 #define OSFIE PIE2_bits.OSFIE
823 // ----- PIR1 bits --------------------
826 unsigned char T1IF:1;
829 unsigned char SSPIF:1;
830 unsigned char TXIF:1;
831 unsigned char RCIF:1;
832 unsigned char ADIF:1;
836 unsigned char TMR1IF:1;
846 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
848 #define T1IF PIR1_bits.T1IF
849 #define TMR1IF PIR1_bits.TMR1IF
850 #define SSPIF PIR1_bits.SSPIF
851 #define TXIF PIR1_bits.TXIF
852 #define RCIF PIR1_bits.RCIF
853 #define ADIF PIR1_bits.ADIF
855 // ----- PIR2 bits --------------------
862 unsigned char EEIF:1;
863 unsigned char C1IF:1;
864 unsigned char C2IF:1;
865 unsigned char OSFIF:1;
868 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
870 #define EEIF PIR2_bits.EEIF
871 #define C1IF PIR2_bits.C1IF
872 #define C2IF PIR2_bits.C2IF
873 #define OSFIF PIR2_bits.OSFIF
875 // ----- RCSTA bits --------------------
878 unsigned char RX9D:1;
879 unsigned char OERR:1;
880 unsigned char FERR:1;
881 unsigned char ADDEN:1;
882 unsigned char CREN:1;
883 unsigned char SREN:1;
885 unsigned char SPEN:1;
888 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
890 #define RX9D RCSTA_bits.RX9D
891 #define OERR RCSTA_bits.OERR
892 #define FERR RCSTA_bits.FERR
893 #define ADDEN RCSTA_bits.ADDEN
894 #define CREN RCSTA_bits.CREN
895 #define SREN RCSTA_bits.SREN
896 #define RX9 RCSTA_bits.RX9
897 #define SPEN RCSTA_bits.SPEN
899 // ----- SPBRG bits --------------------
902 unsigned char BRG0:1;
903 unsigned char BRG1:1;
904 unsigned char BRG2:1;
905 unsigned char BRG3:1;
906 unsigned char BRG4:1;
907 unsigned char BRG5:1;
908 unsigned char BRG6:1;
909 unsigned char BRG7:1;
912 extern volatile __SPBRG_bits_t __at(SPBRG_ADDR) SPBRG_bits;
914 #define BRG0 SPBRG_bits.BRG0
915 #define BRG1 SPBRG_bits.BRG1
916 #define BRG2 SPBRG_bits.BRG2
917 #define BRG3 SPBRG_bits.BRG3
918 #define BRG4 SPBRG_bits.BRG4
919 #define BRG5 SPBRG_bits.BRG5
920 #define BRG6 SPBRG_bits.BRG6
921 #define BRG7 SPBRG_bits.BRG7
923 // ----- SPBRGH bits --------------------
926 unsigned char BRG8:1;
927 unsigned char BRG9:1;
928 unsigned char BRG10:1;
929 unsigned char BRG11:1;
930 unsigned char BRG12:1;
931 unsigned char BRG13:1;
932 unsigned char BRG14:1;
933 unsigned char BRG15:1;
936 extern volatile __SPBRGH_bits_t __at(SPBRGH_ADDR) SPBRGH_bits;
938 #define BRG8 SPBRGH_bits.BRG8
939 #define BRG9 SPBRGH_bits.BRG9
940 #define BRG10 SPBRGH_bits.BRG10
941 #define BRG11 SPBRGH_bits.BRG11
942 #define BRG12 SPBRGH_bits.BRG12
943 #define BRG13 SPBRGH_bits.BRG13
944 #define BRG14 SPBRGH_bits.BRG14
945 #define BRG15 SPBRGH_bits.BRG15
947 // ----- SSPCON bits --------------------
950 unsigned char SSPM0:1;
951 unsigned char SSPM1:1;
952 unsigned char SSPM2:1;
953 unsigned char SSPM3:1;
955 unsigned char SSPEN:1;
956 unsigned char SSPOV:1;
957 unsigned char WCOL:1;
960 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
962 #define SSPM0 SSPCON_bits.SSPM0
963 #define SSPM1 SSPCON_bits.SSPM1
964 #define SSPM2 SSPCON_bits.SSPM2
965 #define SSPM3 SSPCON_bits.SSPM3
966 #define CKP SSPCON_bits.CKP
967 #define SSPEN SSPCON_bits.SSPEN
968 #define SSPOV SSPCON_bits.SSPOV
969 #define WCOL SSPCON_bits.WCOL
971 // ----- SSPSTAT bits --------------------
976 unsigned char R_W_NOT:1;
979 unsigned char D_A_NOT:1;
984 unsigned char WPUA0:1;
985 unsigned char WPUA1:1;
986 unsigned char WPUA2:1;
987 unsigned char IOC3:1;
988 unsigned char WPUA4:1;
989 unsigned char WPUA5:1;
994 unsigned char IOC0:1;
995 unsigned char IOC1:1;
996 unsigned char IOC2:1;
997 unsigned char IOCA3:1;
998 unsigned char IOC4:1;
999 unsigned char IOC5:1;
1004 unsigned char IOCA0:1;
1005 unsigned char IOCA1:1;
1006 unsigned char IOCA2:1;
1008 unsigned char IOCA4:1;
1009 unsigned char IOCA5:1;
1014 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
1016 #define BF SSPSTAT_bits.BF
1017 #define WPUA0 SSPSTAT_bits.WPUA0
1018 #define IOC0 SSPSTAT_bits.IOC0
1019 #define IOCA0 SSPSTAT_bits.IOCA0
1020 #define UA SSPSTAT_bits.UA
1021 #define WPUA1 SSPSTAT_bits.WPUA1
1022 #define IOC1 SSPSTAT_bits.IOC1
1023 #define IOCA1 SSPSTAT_bits.IOCA1
1024 #define R_W_NOT SSPSTAT_bits.R_W_NOT
1025 #define WPUA2 SSPSTAT_bits.WPUA2
1026 #define IOC2 SSPSTAT_bits.IOC2
1027 #define IOCA2 SSPSTAT_bits.IOCA2
1028 #define S SSPSTAT_bits.S
1029 #define IOC3 SSPSTAT_bits.IOC3
1030 #define IOCA3 SSPSTAT_bits.IOCA3
1031 #define P SSPSTAT_bits.P
1032 #define WPUA4 SSPSTAT_bits.WPUA4
1033 #define IOC4 SSPSTAT_bits.IOC4
1034 #define IOCA4 SSPSTAT_bits.IOCA4
1035 #define D_A_NOT SSPSTAT_bits.D_A_NOT
1036 #define WPUA5 SSPSTAT_bits.WPUA5
1037 #define IOC5 SSPSTAT_bits.IOC5
1038 #define IOCA5 SSPSTAT_bits.IOCA5
1039 #define CKE SSPSTAT_bits.CKE
1040 #define SMP SSPSTAT_bits.SMP
1042 // ----- STATUS bits --------------------
1048 unsigned char NOT_PD:1;
1049 unsigned char NOT_TO:1;
1050 unsigned char RP0:1;
1051 unsigned char RP1:1;
1052 unsigned char IRP:1;
1055 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1057 #define C STATUS_bits.C
1058 #define DC STATUS_bits.DC
1059 #define Z STATUS_bits.Z
1060 #define NOT_PD STATUS_bits.NOT_PD
1061 #define NOT_TO STATUS_bits.NOT_TO
1062 #define RP0 STATUS_bits.RP0
1063 #define RP1 STATUS_bits.RP1
1064 #define IRP STATUS_bits.IRP
1066 // ----- T1CON bits --------------------
1069 unsigned char TMR1ON:1;
1070 unsigned char TMR1CS:1;
1071 unsigned char NOT_T1SYNC:1;
1072 unsigned char T1OSCEN:1;
1073 unsigned char T1CKPS0:1;
1074 unsigned char T1CKPS1:1;
1075 unsigned char TMR1GE:1;
1076 unsigned char T1GINV:1;
1079 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1081 #define TMR1ON T1CON_bits.TMR1ON
1082 #define TMR1CS T1CON_bits.TMR1CS
1083 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1084 #define T1OSCEN T1CON_bits.T1OSCEN
1085 #define T1CKPS0 T1CON_bits.T1CKPS0
1086 #define T1CKPS1 T1CON_bits.T1CKPS1
1087 #define TMR1GE T1CON_bits.TMR1GE
1088 #define T1GINV T1CON_bits.T1GINV
1090 // ----- TRISA bits --------------------
1093 unsigned char TRISA0:1;
1094 unsigned char TRISA1:1;
1095 unsigned char TRISA2:1;
1096 unsigned char TRISA3:1;
1097 unsigned char TRISA4:1;
1098 unsigned char TRISA5:1;
1103 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1105 #define TRISA0 TRISA_bits.TRISA0
1106 #define TRISA1 TRISA_bits.TRISA1
1107 #define TRISA2 TRISA_bits.TRISA2
1108 #define TRISA3 TRISA_bits.TRISA3
1109 #define TRISA4 TRISA_bits.TRISA4
1110 #define TRISA5 TRISA_bits.TRISA5
1112 // ----- TRISB bits --------------------
1119 unsigned char TRISB4:1;
1120 unsigned char TRISB5:1;
1121 unsigned char TRISB6:1;
1122 unsigned char TRISB7:1;
1125 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1127 #define TRISB4 TRISB_bits.TRISB4
1128 #define TRISB5 TRISB_bits.TRISB5
1129 #define TRISB6 TRISB_bits.TRISB6
1130 #define TRISB7 TRISB_bits.TRISB7
1132 // ----- TRISC bits --------------------
1135 unsigned char TRISC0:1;
1136 unsigned char TRISC1:1;
1137 unsigned char TRISC2:1;
1138 unsigned char TRISC3:1;
1139 unsigned char TRISC4:1;
1140 unsigned char TRISC5:1;
1141 unsigned char TRISC6:1;
1142 unsigned char TRISC7:1;
1145 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1147 #define TRISC0 TRISC_bits.TRISC0
1148 #define TRISC1 TRISC_bits.TRISC1
1149 #define TRISC2 TRISC_bits.TRISC2
1150 #define TRISC3 TRISC_bits.TRISC3
1151 #define TRISC4 TRISC_bits.TRISC4
1152 #define TRISC5 TRISC_bits.TRISC5
1153 #define TRISC6 TRISC_bits.TRISC6
1154 #define TRISC7 TRISC_bits.TRISC7
1156 // ----- TXSTA bits --------------------
1159 unsigned char TX9D:1;
1160 unsigned char TRMT:1;
1161 unsigned char BRGH:1;
1162 unsigned char SENB:1;
1163 unsigned char SYNC:1;
1164 unsigned char TXEN:1;
1165 unsigned char TX9:1;
1166 unsigned char CSRC:1;
1169 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1171 #define TX9D TXSTA_bits.TX9D
1172 #define TRMT TXSTA_bits.TRMT
1173 #define BRGH TXSTA_bits.BRGH
1174 #define SENB TXSTA_bits.SENB
1175 #define SYNC TXSTA_bits.SYNC
1176 #define TXEN TXSTA_bits.TXEN
1177 #define TX9 TXSTA_bits.TX9
1178 #define CSRC TXSTA_bits.CSRC
1180 // ----- VRCON bits --------------------
1183 unsigned char VR0:1;
1184 unsigned char VR1:1;
1185 unsigned char VR2:1;
1186 unsigned char VR3:1;
1187 unsigned char VP6EN:1;
1188 unsigned char VRR:1;
1189 unsigned char C2VREN:1;
1190 unsigned char C1VREN:1;
1193 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1195 #define VR0 VRCON_bits.VR0
1196 #define VR1 VRCON_bits.VR1
1197 #define VR2 VRCON_bits.VR2
1198 #define VR3 VRCON_bits.VR3
1199 #define VP6EN VRCON_bits.VP6EN
1200 #define VRR VRCON_bits.VRR
1201 #define C2VREN VRCON_bits.C2VREN
1202 #define C1VREN VRCON_bits.C1VREN
1204 // ----- WDTCON bits --------------------
1207 unsigned char SWDTEN:1;
1208 unsigned char WDTPS0:1;
1209 unsigned char WDTPS1:1;
1210 unsigned char WDTPS2:1;
1211 unsigned char WDTPS3:1;
1217 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1219 #define SWDTEN WDTCON_bits.SWDTEN
1220 #define WDTPS0 WDTCON_bits.WDTPS0
1221 #define WDTPS1 WDTCON_bits.WDTPS1
1222 #define WDTPS2 WDTCON_bits.WDTPS2
1223 #define WDTPS3 WDTCON_bits.WDTPS3
1225 // ----- WPUB bits --------------------
1232 unsigned char WPUB4:1;
1233 unsigned char WPUB5:1;
1234 unsigned char WPUB6:1;
1235 unsigned char WPUB7:1;
1242 unsigned char IOCB4:1;
1243 unsigned char IOCB5:1;
1244 unsigned char IOCB6:1;
1245 unsigned char IOCB7:1;
1248 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1250 #define WPUB4 WPUB_bits.WPUB4
1251 #define IOCB4 WPUB_bits.IOCB4
1252 #define WPUB5 WPUB_bits.WPUB5
1253 #define IOCB5 WPUB_bits.IOCB5
1254 #define WPUB6 WPUB_bits.WPUB6
1255 #define IOCB6 WPUB_bits.IOCB6
1256 #define WPUB7 WPUB_bits.WPUB7
1257 #define IOCB7 WPUB_bits.IOCB7